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Name Size
cpu.h 16.8 kB
exec.h 1.6 kB
helper.c 83.2 kB
helpers.h 17.1 kB
iwmmxt_helper.c 24.7 kB
machine.c 6.7 kB
neon_helper.c 52.8 kB
op_addsub.h 1.8 kB
op_helper.c 9.5 kB
translate.c 322.1 kB

Latest revisions

# Date Author Comment
ca27c052 03/07/2011 10:46 am Peter Maydell

target-arm: Implement a minimal set of cp14 debug registers

Newer ARM kernels try to probe for whether the CPU has hardware breakpoint
support. For this to work QEMU has to implement a minimal set of the cp14
debug registers. The architecture requires v7 cores to implement debug...
3849902c 03/07/2011 10:26 am Peter Maydell

target-arm: Use TCG temporary leak debugging facilities

Use the new TCG temporary leak debugging facilities to
check that each ARM instruction does not leak temporaries.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>
7d1b0095 03/07/2011 10:26 am Peter Maydell

target-arm: Remove ad-hoc leak checking code

This commit removes the ad-hoc resource leak checking code from
target-arm. This includes replacing all uses of new_tmp() with
tcg_temp_new_i32() and all uses of dead_tmp() with
tcg_temp_free_i32().

Signed-off-by: Peter Maydell <>...
f8bf8606 03/07/2011 12:37 am Adam Lackorzynski

target-arm: Implement cp15 VA->PA translation

Implement VA->PA translations by cp15-c7 that went through unchanged
previously.

Signed-off-by: Adam Lackorzynski <>
Signed-off-by: Aurelien Jarno <>
29501f1b 03/07/2011 12:30 am Peter Maydell

target-arm: Set carry flag correctly for Thumb2 ORNS

The code for Thumb2 ORNS (or negated and set flags) was trashing
a TCG input register which was needed later for use in calculating
flags, with the effect that the carry flag was always set with
the wrong sense. Fix this by using the TCG orc op instead of...
8387da81 03/06/2011 09:28 pm Peter Maydell

target-arm: Handle VMOV between two core and VFP single regs

Fix two bugs in the translation of the instructions VMOV sa,sb,rx,ry and
VMOV rx,ry,sa,sb (which copy between a pair of ARM core registers and a
pair of VFP single precision registers):

  • An incorrect condition meant these instruction patterns were being...
cc688901 03/06/2011 09:20 pm Peter Maydell

target-arm: Don't decode old cp15 WFI instructions on v7 cores

In v7 of the ARM architecture, WFI (wait for interrupt) is a first-class
instruction, but in previous versions this functionality was provided
via a cp15 coprocessor register. Add correct feature checks to the...
56bf4fe2 02/24/2011 09:53 am Christophe Lyon

target-arm: Introduce float64_256 and float64_512 constants.

These two constants will be used by helper functions such as recpe_f32
and rsqrte_f32.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>...
fe0e4872 02/24/2011 09:53 am Christophe Lyon

target-arm: fix support for VRECPE.

Now use the same algorithm as described in the ARM ARM.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>
e07be5d2 02/24/2011 09:53 am Christophe Lyon

target-arm: fix support for VRSQRTE.

Now use the same algorithm as described in the ARM ARM.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

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