Revision 60aa19ab
| b/hw/mips_malta.c | ||
|---|---|---|
| 30 | 30 |
#define BIOS_FILENAME "mipsel_bios.bin" |
| 31 | 31 |
#endif |
| 32 | 32 |
|
| 33 |
#ifdef MIPS_HAS_MIPS64
|
|
| 33 |
#ifdef TARGET_MIPS64
|
|
| 34 | 34 |
#define INITRD_LOAD_ADDR (int64_t)0x80800000 |
| 35 | 35 |
#else |
| 36 | 36 |
#define INITRD_LOAD_ADDR (int32_t)0x80800000 |
| ... | ... | |
| 662 | 662 |
|
| 663 | 663 |
/* init CPUs */ |
| 664 | 664 |
if (cpu_model == NULL) {
|
| 665 |
#ifdef MIPS_HAS_MIPS64
|
|
| 665 |
#ifdef TARGET_MIPS64
|
|
| 666 | 666 |
cpu_model = "R4000"; |
| 667 | 667 |
#else |
| 668 | 668 |
cpu_model = "4KEc"; |
| b/hw/mips_r4k.c | ||
|---|---|---|
| 15 | 15 |
#define BIOS_FILENAME "mipsel_bios.bin" |
| 16 | 16 |
#endif |
| 17 | 17 |
|
| 18 |
#ifdef MIPS_HAS_MIPS64
|
|
| 18 |
#ifdef TARGET_MIPS64
|
|
| 19 | 19 |
#define INITRD_LOAD_ADDR (int64_t)(int32_t)0x80800000 |
| 20 | 20 |
#else |
| 21 | 21 |
#define INITRD_LOAD_ADDR (int32_t)0x80800000 |
| ... | ... | |
| 142 | 142 |
|
| 143 | 143 |
/* init CPUs */ |
| 144 | 144 |
if (cpu_model == NULL) {
|
| 145 |
#ifdef MIPS_HAS_MIPS64
|
|
| 145 |
#ifdef TARGET_MIPS64
|
|
| 146 | 146 |
cpu_model = "R4000"; |
| 147 | 147 |
#else |
| 148 | 148 |
cpu_model = "4KEc"; |
| b/target-mips/exec.h | ||
|---|---|---|
| 65 | 65 |
{
|
| 66 | 66 |
} |
| 67 | 67 |
|
| 68 |
#ifdef MIPS_HAS_MIPS64
|
|
| 68 |
#ifdef TARGET_MIPS64
|
|
| 69 | 69 |
#if TARGET_LONG_BITS > HOST_LONG_BITS |
| 70 | 70 |
void do_dsll (void); |
| 71 | 71 |
void do_dsll32 (void); |
| ... | ... | |
| 92 | 92 |
void do_ddiv (void); |
| 93 | 93 |
void do_ddivu (void); |
| 94 | 94 |
#endif |
| 95 |
#ifdef MIPS_HAS_MIPS64
|
|
| 95 |
#ifdef TARGET_MIPS64
|
|
| 96 | 96 |
void do_dmult (void); |
| 97 | 97 |
void do_dmultu (void); |
| 98 | 98 |
#endif |
| ... | ... | |
| 114 | 114 |
void do_lwr_raw (uint32_t); |
| 115 | 115 |
uint32_t do_swl_raw (uint32_t); |
| 116 | 116 |
uint32_t do_swr_raw (uint32_t); |
| 117 |
#ifdef MIPS_HAS_MIPS64
|
|
| 117 |
#ifdef TARGET_MIPS64
|
|
| 118 | 118 |
void do_ldl_raw (uint64_t); |
| 119 | 119 |
void do_ldr_raw (uint64_t); |
| 120 | 120 |
uint64_t do_sdl_raw (uint64_t); |
| ... | ... | |
| 129 | 129 |
uint32_t do_swl_kernel (uint32_t); |
| 130 | 130 |
uint32_t do_swr_user (uint32_t); |
| 131 | 131 |
uint32_t do_swr_kernel (uint32_t); |
| 132 |
#ifdef MIPS_HAS_MIPS64
|
|
| 132 |
#ifdef TARGET_MIPS64
|
|
| 133 | 133 |
void do_ldl_user (uint64_t); |
| 134 | 134 |
void do_ldl_kernel (uint64_t); |
| 135 | 135 |
void do_ldr_user (uint64_t); |
| b/target-mips/mips-defs.h | ||
|---|---|---|
| 6 | 6 |
/* If we want to use host float regs... */ |
| 7 | 7 |
//#define USE_HOST_FLOAT_REGS |
| 8 | 8 |
|
| 9 |
/* 32 bits target */ |
|
| 10 |
#undef MIPS_HAS_MIPS64 |
|
| 11 |
//#define MIPS_HAS_MIPS64 1 |
|
| 12 | 9 |
/* real pages are variable size... */ |
| 13 | 10 |
#define TARGET_PAGE_BITS 12 |
| 14 | 11 |
/* Uses MIPS R4Kc TLB model */ |
| ... | ... | |
| 16 | 13 |
#define MIPS_TLB_NB 16 |
| 17 | 14 |
#define MIPS_TLB_MAX 128 |
| 18 | 15 |
|
| 19 |
#ifdef MIPS_HAS_MIPS64
|
|
| 16 |
#ifdef TARGET_MIPS64
|
|
| 20 | 17 |
#define TARGET_LONG_BITS 64 |
| 21 | 18 |
#else |
| 22 | 19 |
#define TARGET_LONG_BITS 32 |
| b/target-mips/op.c | ||
|---|---|---|
| 386 | 386 |
RETURN(); |
| 387 | 387 |
} |
| 388 | 388 |
|
| 389 |
#ifdef MIPS_HAS_MIPS64
|
|
| 389 |
#ifdef TARGET_MIPS64
|
|
| 390 | 390 |
/* Arithmetic */ |
| 391 | 391 |
void op_dadd (void) |
| 392 | 392 |
{
|
| ... | ... | |
| 464 | 464 |
RETURN(); |
| 465 | 465 |
} |
| 466 | 466 |
#endif |
| 467 |
#endif /* MIPS_HAS_MIPS64 */
|
|
| 467 |
#endif /* TARGET_MIPS64 */
|
|
| 468 | 468 |
|
| 469 | 469 |
/* Logical */ |
| 470 | 470 |
void op_and (void) |
| ... | ... | |
| 586 | 586 |
RETURN(); |
| 587 | 587 |
} |
| 588 | 588 |
|
| 589 |
#ifdef MIPS_HAS_MIPS64
|
|
| 589 |
#ifdef TARGET_MIPS64
|
|
| 590 | 590 |
|
| 591 | 591 |
#if TARGET_LONG_BITS > HOST_LONG_BITS |
| 592 | 592 |
/* Those might call libgcc functions. */ |
| ... | ... | |
| 891 | 891 |
} |
| 892 | 892 |
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
| 893 | 893 |
|
| 894 |
#ifdef MIPS_HAS_MIPS64
|
|
| 894 |
#ifdef TARGET_MIPS64
|
|
| 895 | 895 |
void op_dmult (void) |
| 896 | 896 |
{
|
| 897 | 897 |
CALL_FROM_TB0(do_dmult); |
| ... | ... | |
| 2213 | 2213 |
RETURN(); |
| 2214 | 2214 |
} |
| 2215 | 2215 |
|
| 2216 |
#ifdef MIPS_HAS_MIPS64
|
|
| 2216 |
#ifdef TARGET_MIPS64
|
|
| 2217 | 2217 |
void op_dext(void) |
| 2218 | 2218 |
{
|
| 2219 | 2219 |
unsigned int pos = PARAM1; |
| b/target-mips/op_helper.c | ||
|---|---|---|
| 79 | 79 |
#undef MEMSUFFIX |
| 80 | 80 |
#endif |
| 81 | 81 |
|
| 82 |
#ifdef MIPS_HAS_MIPS64
|
|
| 82 |
#ifdef TARGET_MIPS64
|
|
| 83 | 83 |
#if TARGET_LONG_BITS > HOST_LONG_BITS |
| 84 | 84 |
/* Those might call libgcc functions. */ |
| 85 | 85 |
void do_dsll (void) |
| ... | ... | |
| 161 | 161 |
T0 = T1; |
| 162 | 162 |
} |
| 163 | 163 |
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
| 164 |
#endif /* MIPS_HAS_MIPS64 */
|
|
| 164 |
#endif /* TARGET_MIPS64 */
|
|
| 165 | 165 |
|
| 166 | 166 |
/* 64 bits arithmetic for 32 bits hosts */ |
| 167 | 167 |
#if TARGET_LONG_BITS > HOST_LONG_BITS |
| ... | ... | |
| 219 | 219 |
} |
| 220 | 220 |
#endif |
| 221 | 221 |
|
| 222 |
#ifdef MIPS_HAS_MIPS64
|
|
| 222 |
#ifdef TARGET_MIPS64
|
|
| 223 | 223 |
void do_dmult (void) |
| 224 | 224 |
{
|
| 225 | 225 |
/* XXX */ |
| b/target-mips/op_helper_mem.c | ||
|---|---|---|
| 124 | 124 |
return tmp; |
| 125 | 125 |
} |
| 126 | 126 |
|
| 127 |
#ifdef MIPS_HAS_MIPS64
|
|
| 127 |
#ifdef TARGET_MIPS64
|
|
| 128 | 128 |
|
| 129 | 129 |
# ifdef TARGET_WORDS_BIGENDIAN |
| 130 | 130 |
#define GET_LMASK64(v) ((v) & 4) |
| ... | ... | |
| 298 | 298 |
return tmp; |
| 299 | 299 |
} |
| 300 | 300 |
|
| 301 |
#endif /* MIPS_HAS_MIPS64 */ |
|
| 301 |
#endif /* TARGET_MIPS64 */ |
|
| b/target-mips/op_mem.c | ||
|---|---|---|
| 126 | 126 |
RETURN(); |
| 127 | 127 |
} |
| 128 | 128 |
|
| 129 |
#ifdef MIPS_HAS_MIPS64
|
|
| 129 |
#ifdef TARGET_MIPS64
|
|
| 130 | 130 |
void glue(op_ld, MEMSUFFIX) (void) |
| 131 | 131 |
{
|
| 132 | 132 |
T0 = glue(ldq, MEMSUFFIX)(T0); |
| ... | ... | |
| 190 | 190 |
} |
| 191 | 191 |
RETURN(); |
| 192 | 192 |
} |
| 193 |
#endif /* MIPS_HAS_MIPS64 */
|
|
| 193 |
#endif /* TARGET_MIPS64 */
|
|
| 194 | 194 |
|
| 195 | 195 |
void glue(op_lwc1, MEMSUFFIX) (void) |
| 196 | 196 |
{
|
| b/target-mips/translate.c | ||
|---|---|---|
| 611 | 611 |
} |
| 612 | 612 |
#endif |
| 613 | 613 |
|
| 614 |
#ifdef MIPS_HAS_MIPS64
|
|
| 614 |
#ifdef TARGET_MIPS64
|
|
| 615 | 615 |
OP_LD_TABLE(d); |
| 616 | 616 |
OP_LD_TABLE(dl); |
| 617 | 617 |
OP_LD_TABLE(dr); |
| ... | ... | |
| 660 | 660 |
* memory access |
| 661 | 661 |
*/ |
| 662 | 662 |
switch (opc) {
|
| 663 |
#ifdef MIPS_HAS_MIPS64
|
|
| 663 |
#ifdef TARGET_MIPS64
|
|
| 664 | 664 |
case OPC_LD: |
| 665 | 665 |
op_ldst(ld); |
| 666 | 666 |
GEN_STORE_TN_REG(rt, T0); |
| ... | ... | |
| 872 | 872 |
gen_op_add(); |
| 873 | 873 |
opn = "addiu"; |
| 874 | 874 |
break; |
| 875 |
#ifdef MIPS_HAS_MIPS64
|
|
| 875 |
#ifdef TARGET_MIPS64
|
|
| 876 | 876 |
case OPC_DADDI: |
| 877 | 877 |
save_cpu_state(ctx, 1); |
| 878 | 878 |
gen_op_daddo(); |
| ... | ... | |
| 923 | 923 |
opn = "srl"; |
| 924 | 924 |
} |
| 925 | 925 |
break; |
| 926 |
#ifdef MIPS_HAS_MIPS64
|
|
| 926 |
#ifdef TARGET_MIPS64
|
|
| 927 | 927 |
case OPC_DSLL: |
| 928 | 928 |
gen_op_dsll(); |
| 929 | 929 |
opn = "dsll"; |
| ... | ... | |
| 1003 | 1003 |
gen_op_sub(); |
| 1004 | 1004 |
opn = "subu"; |
| 1005 | 1005 |
break; |
| 1006 |
#ifdef MIPS_HAS_MIPS64
|
|
| 1006 |
#ifdef TARGET_MIPS64
|
|
| 1007 | 1007 |
case OPC_DADD: |
| 1008 | 1008 |
save_cpu_state(ctx, 1); |
| 1009 | 1009 |
gen_op_daddo(); |
| ... | ... | |
| 1076 | 1076 |
opn = "srlv"; |
| 1077 | 1077 |
} |
| 1078 | 1078 |
break; |
| 1079 |
#ifdef MIPS_HAS_MIPS64
|
|
| 1079 |
#ifdef TARGET_MIPS64
|
|
| 1080 | 1080 |
case OPC_DSLLV: |
| 1081 | 1081 |
gen_op_dsllv(); |
| 1082 | 1082 |
opn = "dsllv"; |
| ... | ... | |
| 1168 | 1168 |
gen_op_multu(); |
| 1169 | 1169 |
opn = "multu"; |
| 1170 | 1170 |
break; |
| 1171 |
#ifdef MIPS_HAS_MIPS64
|
|
| 1171 |
#ifdef TARGET_MIPS64
|
|
| 1172 | 1172 |
case OPC_DDIV: |
| 1173 | 1173 |
gen_op_ddiv(); |
| 1174 | 1174 |
opn = "ddiv"; |
| ... | ... | |
| 1229 | 1229 |
gen_op_clz(); |
| 1230 | 1230 |
opn = "clz"; |
| 1231 | 1231 |
break; |
| 1232 |
#ifdef MIPS_HAS_MIPS64
|
|
| 1232 |
#ifdef TARGET_MIPS64
|
|
| 1233 | 1233 |
case OPC_DCLO: |
| 1234 | 1234 |
gen_op_dclo(); |
| 1235 | 1235 |
opn = "dclo"; |
| ... | ... | |
| 4538 | 4538 |
/* MIPS16 extension to MIPS32 */ |
| 4539 | 4539 |
/* SmartMIPS extension to MIPS32 */ |
| 4540 | 4540 |
|
| 4541 |
#ifdef MIPS_HAS_MIPS64
|
|
| 4541 |
#ifdef TARGET_MIPS64
|
|
| 4542 | 4542 |
/* Coprocessor 3 (FPU) */ |
| 4543 | 4543 |
|
| 4544 | 4544 |
/* MDMX extension to MIPS64 */ |
| ... | ... | |
| 4643 | 4643 |
} |
| 4644 | 4644 |
break; |
| 4645 | 4645 |
|
| 4646 |
#ifdef MIPS_HAS_MIPS64
|
|
| 4646 |
#ifdef TARGET_MIPS64
|
|
| 4647 | 4647 |
/* MIPS64 specific opcodes */ |
| 4648 | 4648 |
case OPC_DSLL: |
| 4649 | 4649 |
case OPC_DSRL ... OPC_DSRA: |
| ... | ... | |
| 4690 | 4690 |
} |
| 4691 | 4691 |
/* Treat as a noop */ |
| 4692 | 4692 |
break; |
| 4693 |
#ifdef MIPS_HAS_MIPS64
|
|
| 4693 |
#ifdef TARGET_MIPS64
|
|
| 4694 | 4694 |
case OPC_DCLZ ... OPC_DCLO: |
| 4695 | 4695 |
gen_cl(ctx, op1, rd, rs); |
| 4696 | 4696 |
break; |
| ... | ... | |
| 4757 | 4757 |
} |
| 4758 | 4758 |
GEN_STORE_TN_REG(rt, T0); |
| 4759 | 4759 |
break; |
| 4760 |
#ifdef MIPS_HAS_MIPS64
|
|
| 4760 |
#ifdef TARGET_MIPS64
|
|
| 4761 | 4761 |
case OPC_DEXTM ... OPC_DEXT: |
| 4762 | 4762 |
case OPC_DINSM ... OPC_DINS: |
| 4763 | 4763 |
gen_bitops(ctx, op1, rt, rs, sa, rd); |
| ... | ... | |
| 4812 | 4812 |
switch (op1) {
|
| 4813 | 4813 |
case OPC_MFC0: |
| 4814 | 4814 |
case OPC_MTC0: |
| 4815 |
#ifdef MIPS_HAS_MIPS64
|
|
| 4815 |
#ifdef TARGET_MIPS64
|
|
| 4816 | 4816 |
case OPC_DMFC0: |
| 4817 | 4817 |
case OPC_DMTC0: |
| 4818 | 4818 |
#endif |
| ... | ... | |
| 4898 | 4898 |
case OPC_CFC1: |
| 4899 | 4899 |
case OPC_MTC1: |
| 4900 | 4900 |
case OPC_CTC1: |
| 4901 |
#ifdef MIPS_HAS_MIPS64
|
|
| 4901 |
#ifdef TARGET_MIPS64
|
|
| 4902 | 4902 |
case OPC_DMFC1: |
| 4903 | 4903 |
case OPC_DMTC1: |
| 4904 | 4904 |
#endif |
| ... | ... | |
| 4948 | 4948 |
} |
| 4949 | 4949 |
break; |
| 4950 | 4950 |
|
| 4951 |
#ifdef MIPS_HAS_MIPS64
|
|
| 4951 |
#ifdef TARGET_MIPS64
|
|
| 4952 | 4952 |
/* MIPS64 opcodes */ |
| 4953 | 4953 |
case OPC_LWU: |
| 4954 | 4954 |
case OPC_LDL ... OPC_LDR: |
| ... | ... | |
| 5197 | 5197 |
} |
| 5198 | 5198 |
} |
| 5199 | 5199 |
|
| 5200 |
#if defined(MIPS_HAS_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
|
|
| 5200 |
#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
|
|
| 5201 | 5201 |
/* Debug help: The architecture requires 32bit code to maintain proper |
| 5202 | 5202 |
sign-extened values on 64bit machines. */ |
| 5203 | 5203 |
|
| ... | ... | |
| 5255 | 5255 |
env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); |
| 5256 | 5256 |
if (c0_status & (1 << CP0St_CU1)) |
| 5257 | 5257 |
fpu_dump_state(env, f, cpu_fprintf, flags); |
| 5258 |
#if defined(MIPS_HAS_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
|
|
| 5258 |
#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
|
|
| 5259 | 5259 |
cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags); |
| 5260 | 5260 |
#endif |
| 5261 | 5261 |
} |
| b/target-mips/translate_init.c | ||
|---|---|---|
| 74 | 74 |
/* MIPS CPU definitions */ |
| 75 | 75 |
static mips_def_t mips_defs[] = |
| 76 | 76 |
{
|
| 77 |
#ifndef MIPS_HAS_MIPS64
|
|
| 77 |
#ifndef TARGET_MIPS64
|
|
| 78 | 78 |
{
|
| 79 | 79 |
.name = "4Kc", |
| 80 | 80 |
.CP0_PRid = 0x00018000, |
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