tcp/mips: Change TCG_AREG0 (fp -> s0)
Register fp (frame pointer) is a bad choice for compilationswithout optimisation, because the compiler makes heavy useof this register (so the resulting code crashes).
Register s0 had been used for TCG_AREG1 in earlier releases,...
tcg/README: improve description of bswap*
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg-hppa: Don't try to calls to non-constant addresses.
PA-RISC uses procedure descriptors. We'd need to emit a call tothe millicode routine $$dyncall. However, this situation doesn'tactually arise, since we always have the descriptor available atTCG code generation time....
tcg-hppa: Fix in/out register overlap in add2/sub2.
Handle the output log part overlapping the input high parts.Also, improve sub2 to handle some constants the second input low part.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/ia64: fix tlb addend read
tcg-hppa: Finish the port.
Delete inline functions from tcg-target.h that don't need to be there,move the others to tcg-target.c. Add 'Z', 'I', 'J' constraints for0, signed 11-bit, and signed 5-bit respectively. Add GUEST_BASE supportsimilar to ppc64, with the value stored in a register. Add missing...
tcg/ppc64: Fix typo
Signed-off-by: malc <av1474@comtv.ru>
tcg/ppc: Fix typo
tcg/ppc: Implment bswap16/32
tcg/mips: fix 64-bit linux-user on big endian MIPS
tcg/mips: use seb/seh instructions on MIPS32R2
tcg/ppc: Implement eqv, nand and nor
Split TLB addend and target_phys_addr_t
Historically the qemu tlb "addend" field was used for both RAM and IO accesses,so needed to be able to hold both host addresses (unsigned long) and guestphysical addresses (target_phys_addr_t). However since the introduction of...
tcg/ppc: Fix not_i32
Thanks to Alexander Graf for bug report and a good reproducible testcase.
tcg/TODO: remove setcond
tcg: initial ia64 support
tcg/mips: fix branch offset during retranslation
Branch offsets should only be overwritten during relocation, to supportpartial retranslation.
tcg/arm: Replace qemu_ld32u (left over from previous commit)
Commit 86feb1c860dc38e9c89e787c5210e8191800385edid not change all occurrences of INDEX_op_qemu_ld32ufor tcg/arm.
Please note that I could not test this patch(I have currently no arm system available)....
tcg-mips: add guest base support
tcg/mips: implement the not_i32 op the same way as gcc
tcg-mips: implement nor
tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operandssign-extended in 64-bit registers (regardless of the "real" signof the operand). For that, we need to be able to distinguishbetween a 32-bit load with a 32-bit result and a 32-bit load with...
tcg: Allow target-specific implementation of NOR.
tcg: Allow target-specific implementation of NAND.
tcg: Allow target-specific implementation of EQV.
tcg: Use not_i32 to implement not_i64.
tcg: Change TCGType to an enumeration.
The TCGType name was already used consistently. Changing itto an enumeration instead of a set of defines aids debugging.
tcg: Use TCGCond where appropriate.
Use the TCGCond enumeration type in the brcond and setcondrelated prototypes in tcg-op.h and each code generator.
tcg: Name the opcode enumeration.
Give the enumeration formed from tcg-opc.h a name: TCGOpcode.Use that enumeration type instead of "int" whereever appropriate.
remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg-hppa: Fix 64-bit argument ordering
tcg/arm: don't save/restore r7 in prologue/epilogue
There is no need to save r7, it is used to store the addressof the env structure and is not modified by GCC.
tcg/arm: fix load/store definitions for 32-bit targets
tcg: protect div2 in tcg/tcg-opc.h
tcg: declare internal helpers as const and pure
TCG internal helpers only access to the values passed in arguments, anddo not modify the CPU internal state. Thus they can be declared asconst and pure.
tcg/arm: use helpers for divu/remu
tcg: add div/rem 32-bit helpers
Some targets like ARM would benefit to use 32-bit helpers fordiv/rem/divu/remu.
Create a #define for div2 so that targets can select betweendiv, div2 and helper implementation. Use the helper version if noneof the #define are present....
Fix build with -DNDEBUG in CFLAGS
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg/arm: implement andc op
tcg: update README with const and pure helpers
tcg/arm: correctly save/restore registers in prologue/epilogue
Since commit 6113d6d3169393c323ac4c82d756a850145a5e7a QEMU crasheson ARM hosts. This is not a bug of this commit, but a latent bugrevealed by this commit.
The TCG code is called through a procedure call using the prologue...
Fix Sparc host build breakage
Fix error: CC sparc-bsd-user/op_helper.oIn file included from /src/qemu/tcg/tcg.c:158:/src/qemu/tcg/sparc/tcg-target.c:728:5: "TARGET_PHYS_ADDR_BITS" is not defined
tcg/ppc64: Only define addend load helpers in softmmu case
Remove TLB from userspace
Remove TLB from userspace CPU structure.
Signed-off-by: Paul Brook <paul@codesourcery.com>
tcg/arm: merge the two sets of #define for optional ops
tcg/arm: accept immediate arguments for brcond/setcond
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
Add a missing break
tcg/arm: implement setcond2
tcg/arm: implement setcond
tcg/arm: fix div2/divu2
When restoring register values, increase the stack register for skippedvalues.
tcg/ppc: Fix right rotation
tcg/ppc64: Use C90 style comments
tcg/ppc: Implement some of the optional ops
tcg: fix build on 32-bit hppa, ppc and sparc hosts
The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64.
Signed-off-by: Jay Foad <jay.foad@gmail.com>Signed-off-by: malc <av1474@comtv.ru>
tcg: fix assertion with --enable-debug
On 32-bit hosts op_qemu_ld32s is unused. Remove it to fix thefollowing assertion failure:
qemu-alpha: tcg/tcg.c:1055:tcg_add_target_add_op_defs: Assertion `tcg_op_defs[op].used' failed.
Signed-off-by: Jay Foad <jay.foad@gmail.com>...
tcg: Add comments for all optional instructions not implemented.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg-sparc: Implement ORC.
tcg-sparc: Implement ANDC.
tcg: Optional target implementation of ORC.
Previously ORC was always implemented by tcg-op.h withan explicit NOT opcode. Allow a target implementation.
tcg: Optional target implementation of ANDC.
Previously ANDC was always implemented by tcg-op.h withan explicit NOT opcode. Allow a target implementation.
tcg-sparc: Implement not.
The fallback implementation of "ret = arg1 ^ -1" isn't idealbecause of the extra tcg op to load the minus one.
tcg-sparc: Implement neg.
The fallback implementation of "ret = 0 - arg1" isn't ideal,first because of the extra tcg op to load the zero, and secondbecause we fail to handle zero as %g0 for arg1 of the sub.
Signed-off-by: Richard Henderson <rth@twiddle.net>...
tcg/ppc: Consistently use calling convention selection macros
Use ppc host calling convention definitions to set TCG_TARGET_CALL_{ALIGN_ARGS,STACK_OFFSET}.
New version after malc's comments. (This avoids having to do #if defined linux || defined FreeBSD || defined FreeBSD_kernelfor the third case.)...
tcg: Add consistency checks for op definitions
When compiled with CONFIG_DEBUG_TCG, this code looksfor missing, duplicate and wrong entries in theop definitions.
Errors will raise an assertion at program start(all checks are done in the initial phase)....
tcg-sparc: Implement setcond, setcond2.
tcg: Add tcg_swap_cond.
Returns the condition as if with swapped comparison operands.
tcg/mips: fix crash in tcg_out_qemu_ld()
The address register is overriden when it corresponds to v0 and the fastpath is taken, which leads to a crash. Fix that by using the a0 registerinstead.
tcg/mips: implement setcond2
tcg/mips: implement setcond
tcg: move setcond* ops to non-optional section
setcond is not an optional op, move it to the non-optional section.
tcg: add setcondi pseudo-op
tcg/ppc64: implement setcond
tcg/ppc32: proper setcond implementation
tcg/ppc32: implement setcond2
tcg-i386: Implement setcond.
tcg-i386: Implement small forward branches.
There are places, like brcond2, where we know that the destinationof a forward branch will be within 127 bytes.
Add the R_386_PC8 relocation type to support this. Add a flag totcg_out_jxx and tcg_out_brcond* to enable it. Set the flag in the...
tcg: document double-word support opcodes.
The internal opcodes brcond2, add2, sub2, mulu2 were undocumented.Place these in a new section that clearly indicates that they arenot to be emitted by translators.
tcg: generic support for conditional set
Defines setcond_{i32,i64} and setcond2_i32 for 64-on-32-bit.
tcg: add tcg_invert_cond
It is very handy to have a reliable mapping of a condition to its inverse.
tcg-x86_64: implement setcond
tcg/x86_64: Avoid unnecessary REX.B prefixes.
The existing P_REXB internal opcode flag unconditionally emitsthe REX prefix. Technically it's not needed if the register inquestion is %al, %bl, %cl, %dl.
Eliding the prefix requires splitting the P_REXB flag into two,...
tcg/x86_64: Special-case all 32-bit AND operands.
This avoids an unnecessary REX.W prefix when dealing with ANDoperands that fit into a 32-bit quantity. The most common changeactually seen is movz[wb]q -> movz[wb]l.
Similarly, avoid REXW in ext{8,16}u_i64 tcg opcodes....
tcg-sparc: Implement ext32[su]_i64
The 32-bit right-shift instructions is defined to extend the shiftedoutput to 64-bits. A shift count of zero therefore is a simpleextension without actually shifting.
tcg-sparc: Implement division properly.
The {div,divu}2 opcodes are intended for systems for which thedivision instruction produces both quotient and remainder. Sparcis not such a system. Indeed, the remainder must be computed as
quot = a / b rem = a - (quot * b)...
tcg-sparc: Do not remove %o012 from 'r' constraint.
Only 'L' constraint needs that.
tcg-sparc: Implement add2, sub2, mulu2.
Add missing 32-bit double-word support opcodes.
tcg-sparc: Add tcg_out_arithc.
Add a function to handle the register-vs-immediate test for arithmetic.
Also, adjust the OP_32_64 macro so that it auto-indents properly.Rename the gen_arith32 label to gen_arith, since it handles 64-bitarithmetic as well....
tcg: Add tcg_unsigned_cond.
Returns an unsigned version of a signed condition;returns the original condition otherwise.
tcg-sparc: Implement brcond2.
Split out tcg_out_cmp and properly handle immediate arguments.Fix constraints on brcond to match what SUBCC accepts.Add tcg_out_brcond2_i32 for 32-bit host.
tcg-sparc: Use TCG_TARGET_REG_BITS in conditional compilation.
The test TCG_TARGET_REG_BITS==64 is exactly the feature that weare checking for, whereas something involving sparc_v9 orsparc_v8plus should be reserved for something ISA related,as with SMULX....
tcg-sparc: Improve tcg_out_movi for sparc64.
Generate sign-extended 32-bit constants with SETHI+XOR.Otherwise tidy the routine to avoid the need forconditional compilation and code duplication with movi_imm32.
tcg-sparc: Fix imm13 check in movi.
We were unnecessarily restricting imm13 constants to 12 bits.
tcg/ppc64: Fix loading of 32bit constants
TCG: Mac OS X support for ppc64 target
Darwin/ppc64 does not use function descriptors,adapt prologue and tcg_out_call accordingly.GPR2 is available for general use, so let's use it.
http://developer.apple.com/mac/library/documentation/DeveloperTools/Conceptual/LowLevelABI/110-64-bit_PowerPC_Function_Calling_Conventions/64bitPowerPC.html...
S/390 fake TCG implementation
Qemu won't let us run a KVM target without having host TCG support. Well, fornow we don't have any so let's implement a fake target that only stubs outeverything.
I tried to keep the patch as close to Uli's source as possible, so whenever...
tcg: initial mips support
Based on a patch from Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
tcg: fix tcg_regset_{set,reset}_reg with more than 32 registers
tcg/ppc64,x86_64: fix constraints of op_qemu_st64
This op only takes two arguments, not two.