Revision 61271e5c
| b/hw/cuda.c | ||
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*/ |
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#include "vl.h" |
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/* XXX: implement all timer modes */ |
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//#define DEBUG_CUDA |
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//#define DEBUG_CUDA_PACKET |
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|
| ... | ... | |
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#define IER_CLR 0 /* clear bits in IER */ |
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#define SR_INT 0x04 /* Shift register full/empty */ |
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#define T1_INT 0x40 /* Timer 1 interrupt */ |
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#define T2_INT 0x20 /* Timer 2 interrupt */ |
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|
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/* Bits in ACR */ |
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#define T1MODE 0xc0 /* Timer 1 mode */ |
| ... | ... | |
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#define RTC_OFFSET 2082844800 |
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|
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typedef struct CUDATimer {
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unsigned int latch; |
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int index; |
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uint16_t latch; |
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uint16_t counter_value; /* counter value at load time */ |
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int64_t load_time; |
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int64_t next_irq_time; |
| ... | ... | |
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d = muldiv64(qemu_get_clock(vm_clock) - s->load_time, |
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CUDA_TIMER_FREQ, ticks_per_sec); |
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if (d <= s->counter_value) {
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counter = d; |
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if (s->index == 0) {
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/* the timer goes down from latch to -1 (period of latch + 2) */ |
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if (d <= (s->counter_value + 1)) {
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counter = (s->counter_value - d) & 0xffff; |
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} else {
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counter = (d - (s->counter_value + 1)) % (s->latch + 2); |
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counter = (s->latch - counter) & 0xffff; |
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} |
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} else {
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counter = s->latch - 1 - ((d - s->counter_value) % s->latch);
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counter = (s->counter_value - d) & 0xffff;
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} |
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return counter; |
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} |
| ... | ... | |
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static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time) |
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{
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int64_t d, next_time, base; |
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int64_t d, next_time; |
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unsigned int counter; |
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|
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/* current counter value */ |
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d = muldiv64(current_time - s->load_time, |
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CUDA_TIMER_FREQ, ticks_per_sec); |
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if (d < s->counter_value) {
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next_time = s->counter_value + 1; |
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} else |
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{
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base = ((d - s->counter_value + 1) / s->latch); |
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base = (base * s->latch) + s->counter_value; |
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next_time = base + s->latch; |
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/* the timer goes down from latch to -1 (period of latch + 2) */ |
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if (d <= (s->counter_value + 1)) {
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counter = (s->counter_value - d) & 0xffff; |
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} else {
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counter = (d - (s->counter_value + 1)) % (s->latch + 2); |
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counter = (s->latch - counter) & 0xffff; |
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} |
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|
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/* Note: we consider the irq is raised on 0 */ |
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if (counter == 0xffff) {
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next_time = d + s->latch + 1; |
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} else if (counter == 0) {
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next_time = d + s->latch + 2; |
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} else {
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next_time = d + counter; |
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} |
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#if 0 |
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#ifdef DEBUG_CUDA |
| ... | ... | |
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break; |
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case 5: |
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val = get_counter(&s->timers[0]) >> 8; |
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s->ifr &= ~T1_INT; |
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cuda_update_irq(s); |
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break; |
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case 6: |
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val = s->timers[0].latch & 0xff; |
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break; |
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case 7: |
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/* XXX: check this */ |
|
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val = (s->timers[0].latch >> 8) & 0xff; |
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break; |
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case 8: |
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val = get_counter(&s->timers[1]) & 0xff; |
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s->ifr &= ~T2_INT; |
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break; |
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case 9: |
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val = get_counter(&s->timers[1]) >> 8; |
| ... | ... | |
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s->dira = val; |
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break; |
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case 4: |
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val = val | (get_counter(&s->timers[0]) & 0xff00);
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set_counter(s, &s->timers[0], val);
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s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
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cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
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|
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break; |
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case 5: |
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val = (val << 8) | (get_counter(&s->timers[0]) & 0xff); |
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set_counter(s, &s->timers[0], val); |
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s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
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s->ifr &= ~T1_INT; |
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set_counter(s, &s->timers[0], s->timers[0].latch); |
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break; |
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case 6: |
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s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
| ... | ... | |
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break; |
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case 7: |
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s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
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s->ifr &= ~T1_INT; |
|
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cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock)); |
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break; |
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case 8: |
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val = val | (get_counter(&s->timers[1]) & 0xff00);
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s->timers[1].latch = val;
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set_counter(s, &s->timers[1], val); |
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break; |
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case 9: |
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val = (val << 8) | (get_counter(&s->timers[1]) & 0xff); |
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set_counter(s, &s->timers[1], val); |
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set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch); |
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break; |
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case 10: |
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s->sr = val; |
| ... | ... | |
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s->irq_opaque = irq_opaque; |
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s->irq = irq; |
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s->timers[0].index = 0; |
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s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s); |
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s->timers[0].latch = 0x10000;
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s->timers[0].latch = 0xffff;
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set_counter(s, &s->timers[0], 0xffff); |
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s->timers[1].latch = 0x10000; |
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|
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s->timers[1].index = 1; |
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s->timers[1].latch = 0; |
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// s->ier = T1_INT | SR_INT; |
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s->ier = 0; |
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set_counter(s, &s->timers[1], 0xffff); |
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