root / hw / cuda.c @ 61271e5c
History | View | Annotate | Download (17.9 kB)
| 1 |
/*
|
|---|---|
| 2 |
* QEMU CUDA support
|
| 3 |
*
|
| 4 |
* Copyright (c) 2004 Fabrice Bellard
|
| 5 |
*
|
| 6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
| 7 |
* of this software and associated documentation files (the "Software"), to deal
|
| 8 |
* in the Software without restriction, including without limitation the rights
|
| 9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
| 10 |
* copies of the Software, and to permit persons to whom the Software is
|
| 11 |
* furnished to do so, subject to the following conditions:
|
| 12 |
*
|
| 13 |
* The above copyright notice and this permission notice shall be included in
|
| 14 |
* all copies or substantial portions of the Software.
|
| 15 |
*
|
| 16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
| 17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
| 18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
| 19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
| 20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
| 21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
| 22 |
* THE SOFTWARE.
|
| 23 |
*/
|
| 24 |
#include "vl.h" |
| 25 |
|
| 26 |
/* XXX: implement all timer modes */
|
| 27 |
|
| 28 |
//#define DEBUG_CUDA
|
| 29 |
//#define DEBUG_CUDA_PACKET
|
| 30 |
|
| 31 |
/* Bits in B data register: all active low */
|
| 32 |
#define TREQ 0x08 /* Transfer request (input) */ |
| 33 |
#define TACK 0x10 /* Transfer acknowledge (output) */ |
| 34 |
#define TIP 0x20 /* Transfer in progress (output) */ |
| 35 |
|
| 36 |
/* Bits in ACR */
|
| 37 |
#define SR_CTRL 0x1c /* Shift register control bits */ |
| 38 |
#define SR_EXT 0x0c /* Shift on external clock */ |
| 39 |
#define SR_OUT 0x10 /* Shift out if 1 */ |
| 40 |
|
| 41 |
/* Bits in IFR and IER */
|
| 42 |
#define IER_SET 0x80 /* set bits in IER */ |
| 43 |
#define IER_CLR 0 /* clear bits in IER */ |
| 44 |
#define SR_INT 0x04 /* Shift register full/empty */ |
| 45 |
#define T1_INT 0x40 /* Timer 1 interrupt */ |
| 46 |
#define T2_INT 0x20 /* Timer 2 interrupt */ |
| 47 |
|
| 48 |
/* Bits in ACR */
|
| 49 |
#define T1MODE 0xc0 /* Timer 1 mode */ |
| 50 |
#define T1MODE_CONT 0x40 /* continuous interrupts */ |
| 51 |
|
| 52 |
/* commands (1st byte) */
|
| 53 |
#define ADB_PACKET 0 |
| 54 |
#define CUDA_PACKET 1 |
| 55 |
#define ERROR_PACKET 2 |
| 56 |
#define TIMER_PACKET 3 |
| 57 |
#define POWER_PACKET 4 |
| 58 |
#define MACIIC_PACKET 5 |
| 59 |
#define PMU_PACKET 6 |
| 60 |
|
| 61 |
|
| 62 |
/* CUDA commands (2nd byte) */
|
| 63 |
#define CUDA_WARM_START 0x0 |
| 64 |
#define CUDA_AUTOPOLL 0x1 |
| 65 |
#define CUDA_GET_6805_ADDR 0x2 |
| 66 |
#define CUDA_GET_TIME 0x3 |
| 67 |
#define CUDA_GET_PRAM 0x7 |
| 68 |
#define CUDA_SET_6805_ADDR 0x8 |
| 69 |
#define CUDA_SET_TIME 0x9 |
| 70 |
#define CUDA_POWERDOWN 0xa |
| 71 |
#define CUDA_POWERUP_TIME 0xb |
| 72 |
#define CUDA_SET_PRAM 0xc |
| 73 |
#define CUDA_MS_RESET 0xd |
| 74 |
#define CUDA_SEND_DFAC 0xe |
| 75 |
#define CUDA_BATTERY_SWAP_SENSE 0x10 |
| 76 |
#define CUDA_RESET_SYSTEM 0x11 |
| 77 |
#define CUDA_SET_IPL 0x12 |
| 78 |
#define CUDA_FILE_SERVER_FLAG 0x13 |
| 79 |
#define CUDA_SET_AUTO_RATE 0x14 |
| 80 |
#define CUDA_GET_AUTO_RATE 0x16 |
| 81 |
#define CUDA_SET_DEVICE_LIST 0x19 |
| 82 |
#define CUDA_GET_DEVICE_LIST 0x1a |
| 83 |
#define CUDA_SET_ONE_SECOND_MODE 0x1b |
| 84 |
#define CUDA_SET_POWER_MESSAGES 0x21 |
| 85 |
#define CUDA_GET_SET_IIC 0x22 |
| 86 |
#define CUDA_WAKEUP 0x23 |
| 87 |
#define CUDA_TIMER_TICKLE 0x24 |
| 88 |
#define CUDA_COMBINED_FORMAT_IIC 0x25 |
| 89 |
|
| 90 |
#define CUDA_TIMER_FREQ (4700000 / 6) |
| 91 |
#define CUDA_ADB_POLL_FREQ 50 |
| 92 |
|
| 93 |
/* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
|
| 94 |
#define RTC_OFFSET 2082844800 |
| 95 |
|
| 96 |
typedef struct CUDATimer { |
| 97 |
int index;
|
| 98 |
uint16_t latch; |
| 99 |
uint16_t counter_value; /* counter value at load time */
|
| 100 |
int64_t load_time; |
| 101 |
int64_t next_irq_time; |
| 102 |
QEMUTimer *timer; |
| 103 |
} CUDATimer; |
| 104 |
|
| 105 |
typedef struct CUDAState { |
| 106 |
/* cuda registers */
|
| 107 |
uint8_t b; /* B-side data */
|
| 108 |
uint8_t a; /* A-side data */
|
| 109 |
uint8_t dirb; /* B-side direction (1=output) */
|
| 110 |
uint8_t dira; /* A-side direction (1=output) */
|
| 111 |
uint8_t sr; /* Shift register */
|
| 112 |
uint8_t acr; /* Auxiliary control register */
|
| 113 |
uint8_t pcr; /* Peripheral control register */
|
| 114 |
uint8_t ifr; /* Interrupt flag register */
|
| 115 |
uint8_t ier; /* Interrupt enable register */
|
| 116 |
uint8_t anh; /* A-side data, no handshake */
|
| 117 |
|
| 118 |
CUDATimer timers[2];
|
| 119 |
|
| 120 |
uint8_t last_b; /* last value of B register */
|
| 121 |
uint8_t last_acr; /* last value of B register */
|
| 122 |
|
| 123 |
int data_in_size;
|
| 124 |
int data_in_index;
|
| 125 |
int data_out_index;
|
| 126 |
|
| 127 |
SetIRQFunc *set_irq; |
| 128 |
int irq;
|
| 129 |
void *irq_opaque;
|
| 130 |
uint8_t autopoll; |
| 131 |
uint8_t data_in[128];
|
| 132 |
uint8_t data_out[16];
|
| 133 |
QEMUTimer *adb_poll_timer; |
| 134 |
} CUDAState; |
| 135 |
|
| 136 |
static CUDAState cuda_state;
|
| 137 |
ADBBusState adb_bus; |
| 138 |
|
| 139 |
static void cuda_update(CUDAState *s); |
| 140 |
static void cuda_receive_packet_from_host(CUDAState *s, |
| 141 |
const uint8_t *data, int len); |
| 142 |
static void cuda_timer_update(CUDAState *s, CUDATimer *ti, |
| 143 |
int64_t current_time); |
| 144 |
|
| 145 |
static void cuda_update_irq(CUDAState *s) |
| 146 |
{
|
| 147 |
if (s->ifr & s->ier & (SR_INT | T1_INT)) {
|
| 148 |
s->set_irq(s->irq_opaque, s->irq, 1);
|
| 149 |
} else {
|
| 150 |
s->set_irq(s->irq_opaque, s->irq, 0);
|
| 151 |
} |
| 152 |
} |
| 153 |
|
| 154 |
static unsigned int get_counter(CUDATimer *s) |
| 155 |
{
|
| 156 |
int64_t d; |
| 157 |
unsigned int counter; |
| 158 |
|
| 159 |
d = muldiv64(qemu_get_clock(vm_clock) - s->load_time, |
| 160 |
CUDA_TIMER_FREQ, ticks_per_sec); |
| 161 |
if (s->index == 0) { |
| 162 |
/* the timer goes down from latch to -1 (period of latch + 2) */
|
| 163 |
if (d <= (s->counter_value + 1)) { |
| 164 |
counter = (s->counter_value - d) & 0xffff;
|
| 165 |
} else {
|
| 166 |
counter = (d - (s->counter_value + 1)) % (s->latch + 2); |
| 167 |
counter = (s->latch - counter) & 0xffff;
|
| 168 |
} |
| 169 |
} else {
|
| 170 |
counter = (s->counter_value - d) & 0xffff;
|
| 171 |
} |
| 172 |
return counter;
|
| 173 |
} |
| 174 |
|
| 175 |
static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) |
| 176 |
{
|
| 177 |
#ifdef DEBUG_CUDA
|
| 178 |
printf("cuda: T%d.counter=%d\n",
|
| 179 |
1 + (ti->timer == NULL), val); |
| 180 |
#endif
|
| 181 |
ti->load_time = qemu_get_clock(vm_clock); |
| 182 |
ti->counter_value = val; |
| 183 |
cuda_timer_update(s, ti, ti->load_time); |
| 184 |
} |
| 185 |
|
| 186 |
static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
|
| 187 |
{
|
| 188 |
int64_t d, next_time; |
| 189 |
unsigned int counter; |
| 190 |
|
| 191 |
/* current counter value */
|
| 192 |
d = muldiv64(current_time - s->load_time, |
| 193 |
CUDA_TIMER_FREQ, ticks_per_sec); |
| 194 |
/* the timer goes down from latch to -1 (period of latch + 2) */
|
| 195 |
if (d <= (s->counter_value + 1)) { |
| 196 |
counter = (s->counter_value - d) & 0xffff;
|
| 197 |
} else {
|
| 198 |
counter = (d - (s->counter_value + 1)) % (s->latch + 2); |
| 199 |
counter = (s->latch - counter) & 0xffff;
|
| 200 |
} |
| 201 |
|
| 202 |
/* Note: we consider the irq is raised on 0 */
|
| 203 |
if (counter == 0xffff) { |
| 204 |
next_time = d + s->latch + 1;
|
| 205 |
} else if (counter == 0) { |
| 206 |
next_time = d + s->latch + 2;
|
| 207 |
} else {
|
| 208 |
next_time = d + counter; |
| 209 |
} |
| 210 |
#if 0
|
| 211 |
#ifdef DEBUG_CUDA
|
| 212 |
printf("latch=%d counter=%lld delta_next=%lld\n",
|
| 213 |
s->latch, d, next_time - d);
|
| 214 |
#endif
|
| 215 |
#endif
|
| 216 |
next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) + |
| 217 |
s->load_time; |
| 218 |
if (next_time <= current_time)
|
| 219 |
next_time = current_time + 1;
|
| 220 |
return next_time;
|
| 221 |
} |
| 222 |
|
| 223 |
static void cuda_timer_update(CUDAState *s, CUDATimer *ti, |
| 224 |
int64_t current_time) |
| 225 |
{
|
| 226 |
if (!ti->timer)
|
| 227 |
return;
|
| 228 |
if ((s->acr & T1MODE) != T1MODE_CONT) {
|
| 229 |
qemu_del_timer(ti->timer); |
| 230 |
} else {
|
| 231 |
ti->next_irq_time = get_next_irq_time(ti, current_time); |
| 232 |
qemu_mod_timer(ti->timer, ti->next_irq_time); |
| 233 |
} |
| 234 |
} |
| 235 |
|
| 236 |
static void cuda_timer1(void *opaque) |
| 237 |
{
|
| 238 |
CUDAState *s = opaque; |
| 239 |
CUDATimer *ti = &s->timers[0];
|
| 240 |
|
| 241 |
cuda_timer_update(s, ti, ti->next_irq_time); |
| 242 |
s->ifr |= T1_INT; |
| 243 |
cuda_update_irq(s); |
| 244 |
} |
| 245 |
|
| 246 |
static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr) |
| 247 |
{
|
| 248 |
CUDAState *s = opaque; |
| 249 |
uint32_t val; |
| 250 |
|
| 251 |
addr = (addr >> 9) & 0xf; |
| 252 |
switch(addr) {
|
| 253 |
case 0: |
| 254 |
val = s->b; |
| 255 |
break;
|
| 256 |
case 1: |
| 257 |
val = s->a; |
| 258 |
break;
|
| 259 |
case 2: |
| 260 |
val = s->dirb; |
| 261 |
break;
|
| 262 |
case 3: |
| 263 |
val = s->dira; |
| 264 |
break;
|
| 265 |
case 4: |
| 266 |
val = get_counter(&s->timers[0]) & 0xff; |
| 267 |
s->ifr &= ~T1_INT; |
| 268 |
cuda_update_irq(s); |
| 269 |
break;
|
| 270 |
case 5: |
| 271 |
val = get_counter(&s->timers[0]) >> 8; |
| 272 |
cuda_update_irq(s); |
| 273 |
break;
|
| 274 |
case 6: |
| 275 |
val = s->timers[0].latch & 0xff; |
| 276 |
break;
|
| 277 |
case 7: |
| 278 |
/* XXX: check this */
|
| 279 |
val = (s->timers[0].latch >> 8) & 0xff; |
| 280 |
break;
|
| 281 |
case 8: |
| 282 |
val = get_counter(&s->timers[1]) & 0xff; |
| 283 |
s->ifr &= ~T2_INT; |
| 284 |
break;
|
| 285 |
case 9: |
| 286 |
val = get_counter(&s->timers[1]) >> 8; |
| 287 |
break;
|
| 288 |
case 10: |
| 289 |
val = s->sr; |
| 290 |
s->ifr &= ~SR_INT; |
| 291 |
cuda_update_irq(s); |
| 292 |
break;
|
| 293 |
case 11: |
| 294 |
val = s->acr; |
| 295 |
break;
|
| 296 |
case 12: |
| 297 |
val = s->pcr; |
| 298 |
break;
|
| 299 |
case 13: |
| 300 |
val = s->ifr; |
| 301 |
break;
|
| 302 |
case 14: |
| 303 |
val = s->ier; |
| 304 |
break;
|
| 305 |
default:
|
| 306 |
case 15: |
| 307 |
val = s->anh; |
| 308 |
break;
|
| 309 |
} |
| 310 |
#ifdef DEBUG_CUDA
|
| 311 |
if (addr != 13 || val != 0) |
| 312 |
printf("cuda: read: reg=0x%x val=%02x\n", addr, val);
|
| 313 |
#endif
|
| 314 |
return val;
|
| 315 |
} |
| 316 |
|
| 317 |
static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 318 |
{
|
| 319 |
CUDAState *s = opaque; |
| 320 |
|
| 321 |
addr = (addr >> 9) & 0xf; |
| 322 |
#ifdef DEBUG_CUDA
|
| 323 |
printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
|
| 324 |
#endif
|
| 325 |
|
| 326 |
switch(addr) {
|
| 327 |
case 0: |
| 328 |
s->b = val; |
| 329 |
cuda_update(s); |
| 330 |
break;
|
| 331 |
case 1: |
| 332 |
s->a = val; |
| 333 |
break;
|
| 334 |
case 2: |
| 335 |
s->dirb = val; |
| 336 |
break;
|
| 337 |
case 3: |
| 338 |
s->dira = val; |
| 339 |
break;
|
| 340 |
case 4: |
| 341 |
s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
| 342 |
cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
|
| 343 |
break;
|
| 344 |
case 5: |
| 345 |
s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
| 346 |
s->ifr &= ~T1_INT; |
| 347 |
set_counter(s, &s->timers[0], s->timers[0].latch); |
| 348 |
break;
|
| 349 |
case 6: |
| 350 |
s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
| 351 |
cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
|
| 352 |
break;
|
| 353 |
case 7: |
| 354 |
s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
| 355 |
s->ifr &= ~T1_INT; |
| 356 |
cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
|
| 357 |
break;
|
| 358 |
case 8: |
| 359 |
s->timers[1].latch = val;
|
| 360 |
set_counter(s, &s->timers[1], val);
|
| 361 |
break;
|
| 362 |
case 9: |
| 363 |
set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch); |
| 364 |
break;
|
| 365 |
case 10: |
| 366 |
s->sr = val; |
| 367 |
break;
|
| 368 |
case 11: |
| 369 |
s->acr = val; |
| 370 |
cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
|
| 371 |
cuda_update(s); |
| 372 |
break;
|
| 373 |
case 12: |
| 374 |
s->pcr = val; |
| 375 |
break;
|
| 376 |
case 13: |
| 377 |
/* reset bits */
|
| 378 |
s->ifr &= ~val; |
| 379 |
cuda_update_irq(s); |
| 380 |
break;
|
| 381 |
case 14: |
| 382 |
#if 0
|
| 383 |
if (val & IER_SET) {
|
| 384 |
/* set bits */
|
| 385 |
s->ier |= val & 0x7f;
|
| 386 |
} else {
|
| 387 |
/* reset bits */
|
| 388 |
s->ier &= ~val;
|
| 389 |
}
|
| 390 |
#else
|
| 391 |
/* XXX: please explain me why the SPEC is not correct ! */
|
| 392 |
s->ier = val; |
| 393 |
#endif
|
| 394 |
cuda_update_irq(s); |
| 395 |
break;
|
| 396 |
default:
|
| 397 |
case 15: |
| 398 |
s->anh = val; |
| 399 |
break;
|
| 400 |
} |
| 401 |
} |
| 402 |
|
| 403 |
/* NOTE: TIP and TREQ are negated */
|
| 404 |
static void cuda_update(CUDAState *s) |
| 405 |
{
|
| 406 |
int packet_received, len;
|
| 407 |
|
| 408 |
packet_received = 0;
|
| 409 |
if (!(s->b & TIP)) {
|
| 410 |
/* transfer requested from host */
|
| 411 |
|
| 412 |
if (s->acr & SR_OUT) {
|
| 413 |
/* data output */
|
| 414 |
if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
|
| 415 |
if (s->data_out_index < sizeof(s->data_out)) { |
| 416 |
#ifdef DEBUG_CUDA
|
| 417 |
printf("cuda: send: %02x\n", s->sr);
|
| 418 |
#endif
|
| 419 |
s->data_out[s->data_out_index++] = s->sr; |
| 420 |
s->ifr |= SR_INT; |
| 421 |
cuda_update_irq(s); |
| 422 |
} |
| 423 |
} |
| 424 |
} else {
|
| 425 |
if (s->data_in_index < s->data_in_size) {
|
| 426 |
/* data input */
|
| 427 |
if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
|
| 428 |
s->sr = s->data_in[s->data_in_index++]; |
| 429 |
#ifdef DEBUG_CUDA
|
| 430 |
printf("cuda: recv: %02x\n", s->sr);
|
| 431 |
#endif
|
| 432 |
/* indicate end of transfer */
|
| 433 |
if (s->data_in_index >= s->data_in_size) {
|
| 434 |
s->b = (s->b | TREQ); |
| 435 |
} |
| 436 |
s->ifr |= SR_INT; |
| 437 |
cuda_update_irq(s); |
| 438 |
} |
| 439 |
} |
| 440 |
} |
| 441 |
} else {
|
| 442 |
/* no transfer requested: handle sync case */
|
| 443 |
if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
|
| 444 |
/* update TREQ state each time TACK change state */
|
| 445 |
if (s->b & TACK)
|
| 446 |
s->b = (s->b | TREQ); |
| 447 |
else
|
| 448 |
s->b = (s->b & ~TREQ); |
| 449 |
s->ifr |= SR_INT; |
| 450 |
cuda_update_irq(s); |
| 451 |
} else {
|
| 452 |
if (!(s->last_b & TIP)) {
|
| 453 |
/* handle end of host to cuda transfert */
|
| 454 |
packet_received = (s->data_out_index > 0);
|
| 455 |
/* always an IRQ at the end of transfert */
|
| 456 |
s->ifr |= SR_INT; |
| 457 |
cuda_update_irq(s); |
| 458 |
} |
| 459 |
/* signal if there is data to read */
|
| 460 |
if (s->data_in_index < s->data_in_size) {
|
| 461 |
s->b = (s->b & ~TREQ); |
| 462 |
} |
| 463 |
} |
| 464 |
} |
| 465 |
|
| 466 |
s->last_acr = s->acr; |
| 467 |
s->last_b = s->b; |
| 468 |
|
| 469 |
/* NOTE: cuda_receive_packet_from_host() can call cuda_update()
|
| 470 |
recursively */
|
| 471 |
if (packet_received) {
|
| 472 |
len = s->data_out_index; |
| 473 |
s->data_out_index = 0;
|
| 474 |
cuda_receive_packet_from_host(s, s->data_out, len); |
| 475 |
} |
| 476 |
} |
| 477 |
|
| 478 |
static void cuda_send_packet_to_host(CUDAState *s, |
| 479 |
const uint8_t *data, int len) |
| 480 |
{
|
| 481 |
#ifdef DEBUG_CUDA_PACKET
|
| 482 |
{
|
| 483 |
int i;
|
| 484 |
printf("cuda_send_packet_to_host:\n");
|
| 485 |
for(i = 0; i < len; i++) |
| 486 |
printf(" %02x", data[i]);
|
| 487 |
printf("\n");
|
| 488 |
} |
| 489 |
#endif
|
| 490 |
memcpy(s->data_in, data, len); |
| 491 |
s->data_in_size = len; |
| 492 |
s->data_in_index = 0;
|
| 493 |
cuda_update(s); |
| 494 |
s->ifr |= SR_INT; |
| 495 |
cuda_update_irq(s); |
| 496 |
} |
| 497 |
|
| 498 |
static void cuda_adb_poll(void *opaque) |
| 499 |
{
|
| 500 |
CUDAState *s = opaque; |
| 501 |
uint8_t obuf[ADB_MAX_OUT_LEN + 2];
|
| 502 |
int olen;
|
| 503 |
|
| 504 |
olen = adb_poll(&adb_bus, obuf + 2);
|
| 505 |
if (olen > 0) { |
| 506 |
obuf[0] = ADB_PACKET;
|
| 507 |
obuf[1] = 0x40; /* polled data */ |
| 508 |
cuda_send_packet_to_host(s, obuf, olen + 2);
|
| 509 |
} |
| 510 |
qemu_mod_timer(s->adb_poll_timer, |
| 511 |
qemu_get_clock(vm_clock) + |
| 512 |
(ticks_per_sec / CUDA_ADB_POLL_FREQ)); |
| 513 |
} |
| 514 |
|
| 515 |
static void cuda_receive_packet(CUDAState *s, |
| 516 |
const uint8_t *data, int len) |
| 517 |
{
|
| 518 |
uint8_t obuf[16];
|
| 519 |
int ti, autopoll;
|
| 520 |
|
| 521 |
switch(data[0]) { |
| 522 |
case CUDA_AUTOPOLL:
|
| 523 |
autopoll = (data[1] != 0); |
| 524 |
if (autopoll != s->autopoll) {
|
| 525 |
s->autopoll = autopoll; |
| 526 |
if (autopoll) {
|
| 527 |
qemu_mod_timer(s->adb_poll_timer, |
| 528 |
qemu_get_clock(vm_clock) + |
| 529 |
(ticks_per_sec / CUDA_ADB_POLL_FREQ)); |
| 530 |
} else {
|
| 531 |
qemu_del_timer(s->adb_poll_timer); |
| 532 |
} |
| 533 |
} |
| 534 |
obuf[0] = CUDA_PACKET;
|
| 535 |
obuf[1] = data[1]; |
| 536 |
cuda_send_packet_to_host(s, obuf, 2);
|
| 537 |
break;
|
| 538 |
case CUDA_GET_TIME:
|
| 539 |
case CUDA_SET_TIME:
|
| 540 |
/* XXX: add time support ? */
|
| 541 |
ti = time(NULL) + RTC_OFFSET;
|
| 542 |
obuf[0] = CUDA_PACKET;
|
| 543 |
obuf[1] = 0; |
| 544 |
obuf[2] = 0; |
| 545 |
obuf[3] = ti >> 24; |
| 546 |
obuf[4] = ti >> 16; |
| 547 |
obuf[5] = ti >> 8; |
| 548 |
obuf[6] = ti;
|
| 549 |
cuda_send_packet_to_host(s, obuf, 7);
|
| 550 |
break;
|
| 551 |
case CUDA_FILE_SERVER_FLAG:
|
| 552 |
case CUDA_SET_DEVICE_LIST:
|
| 553 |
case CUDA_SET_AUTO_RATE:
|
| 554 |
case CUDA_SET_POWER_MESSAGES:
|
| 555 |
obuf[0] = CUDA_PACKET;
|
| 556 |
obuf[1] = 0; |
| 557 |
cuda_send_packet_to_host(s, obuf, 2);
|
| 558 |
break;
|
| 559 |
case CUDA_POWERDOWN:
|
| 560 |
obuf[0] = CUDA_PACKET;
|
| 561 |
obuf[1] = 0; |
| 562 |
cuda_send_packet_to_host(s, obuf, 2);
|
| 563 |
qemu_system_shutdown_request(); |
| 564 |
break;
|
| 565 |
default:
|
| 566 |
break;
|
| 567 |
} |
| 568 |
} |
| 569 |
|
| 570 |
static void cuda_receive_packet_from_host(CUDAState *s, |
| 571 |
const uint8_t *data, int len) |
| 572 |
{
|
| 573 |
#ifdef DEBUG_CUDA_PACKET
|
| 574 |
{
|
| 575 |
int i;
|
| 576 |
printf("cuda_receive_packet_from_host:\n");
|
| 577 |
for(i = 0; i < len; i++) |
| 578 |
printf(" %02x", data[i]);
|
| 579 |
printf("\n");
|
| 580 |
} |
| 581 |
#endif
|
| 582 |
switch(data[0]) { |
| 583 |
case ADB_PACKET:
|
| 584 |
{
|
| 585 |
uint8_t obuf[ADB_MAX_OUT_LEN + 2];
|
| 586 |
int olen;
|
| 587 |
olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1); |
| 588 |
if (olen > 0) { |
| 589 |
obuf[0] = ADB_PACKET;
|
| 590 |
obuf[1] = 0x00; |
| 591 |
} else {
|
| 592 |
/* error */
|
| 593 |
obuf[0] = ADB_PACKET;
|
| 594 |
obuf[1] = -olen;
|
| 595 |
olen = 0;
|
| 596 |
} |
| 597 |
cuda_send_packet_to_host(s, obuf, olen + 2);
|
| 598 |
} |
| 599 |
break;
|
| 600 |
case CUDA_PACKET:
|
| 601 |
cuda_receive_packet(s, data + 1, len - 1); |
| 602 |
break;
|
| 603 |
} |
| 604 |
} |
| 605 |
|
| 606 |
static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
| 607 |
{
|
| 608 |
} |
| 609 |
|
| 610 |
static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
| 611 |
{
|
| 612 |
} |
| 613 |
|
| 614 |
static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr) |
| 615 |
{
|
| 616 |
return 0; |
| 617 |
} |
| 618 |
|
| 619 |
static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr) |
| 620 |
{
|
| 621 |
return 0; |
| 622 |
} |
| 623 |
|
| 624 |
static CPUWriteMemoryFunc *cuda_write[] = {
|
| 625 |
&cuda_writeb, |
| 626 |
&cuda_writew, |
| 627 |
&cuda_writel, |
| 628 |
}; |
| 629 |
|
| 630 |
static CPUReadMemoryFunc *cuda_read[] = {
|
| 631 |
&cuda_readb, |
| 632 |
&cuda_readw, |
| 633 |
&cuda_readl, |
| 634 |
}; |
| 635 |
|
| 636 |
int cuda_init(SetIRQFunc *set_irq, void *irq_opaque, int irq) |
| 637 |
{
|
| 638 |
CUDAState *s = &cuda_state; |
| 639 |
int cuda_mem_index;
|
| 640 |
|
| 641 |
s->set_irq = set_irq; |
| 642 |
s->irq_opaque = irq_opaque; |
| 643 |
s->irq = irq; |
| 644 |
|
| 645 |
s->timers[0].index = 0; |
| 646 |
s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
|
| 647 |
s->timers[0].latch = 0xffff; |
| 648 |
set_counter(s, &s->timers[0], 0xffff); |
| 649 |
|
| 650 |
s->timers[1].index = 1; |
| 651 |
s->timers[1].latch = 0; |
| 652 |
// s->ier = T1_INT | SR_INT;
|
| 653 |
s->ier = 0;
|
| 654 |
set_counter(s, &s->timers[1], 0xffff); |
| 655 |
|
| 656 |
s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s); |
| 657 |
cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
|
| 658 |
return cuda_mem_index;
|
| 659 |
} |