root / target-sh4 / op_helper.c @ 618ba8e6
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/*
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* SH4 emulation
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*
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* Copyright (c) 2005 Samuel Tardieu
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <assert.h> |
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#include <stdlib.h> |
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#include "exec.h" |
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#include "helper.h" |
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static void cpu_restore_state_from_retaddr(void *retaddr) |
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{ |
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TranslationBlock *tb; |
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unsigned long pc; |
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if (retaddr) {
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pc = (unsigned long) retaddr; |
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tb = tb_find_pc(pc); |
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if (tb) {
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/* the PC is inside the translated code. It means that we have
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a virtual CPU fault */
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cpu_restore_state(tb, env, pc); |
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} |
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} |
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} |
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#ifndef CONFIG_USER_ONLY
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#define MMUSUFFIX _mmu
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#define SHIFT 0 |
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#include "softmmu_template.h" |
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#define SHIFT 1 |
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#include "softmmu_template.h" |
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#define SHIFT 2 |
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#include "softmmu_template.h" |
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#define SHIFT 3 |
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#include "softmmu_template.h" |
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void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
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{ |
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CPUState *saved_env; |
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int ret;
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/* XXX: hack to restore env in all cases, even if not called from
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generated code */
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saved_env = env; |
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env = cpu_single_env; |
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ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
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if (ret) {
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/* now we have a real cpu fault */
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cpu_restore_state_from_retaddr(retaddr); |
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cpu_loop_exit(); |
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} |
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env = saved_env; |
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} |
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#endif
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void helper_ldtlb(void) |
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{ |
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#ifdef CONFIG_USER_ONLY
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/* XXXXX */
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cpu_abort(env, "Unhandled ldtlb");
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#else
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cpu_load_tlb(env); |
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#endif
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} |
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static inline void raise_exception(int index, void *retaddr) |
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{ |
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env->exception_index = index; |
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cpu_restore_state_from_retaddr(retaddr); |
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cpu_loop_exit(); |
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} |
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void helper_raise_illegal_instruction(void) |
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{ |
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raise_exception(0x180, GETPC());
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} |
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void helper_raise_slot_illegal_instruction(void) |
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{ |
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raise_exception(0x1a0, GETPC());
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} |
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void helper_raise_fpu_disable(void) |
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{ |
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raise_exception(0x800, GETPC());
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} |
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void helper_raise_slot_fpu_disable(void) |
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{ |
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raise_exception(0x820, GETPC());
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} |
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void helper_debug(void) |
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{ |
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env->exception_index = EXCP_DEBUG; |
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cpu_loop_exit(); |
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} |
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void helper_sleep(uint32_t next_pc)
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{ |
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env->halted = 1;
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env->in_sleep = 1;
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env->exception_index = EXCP_HLT; |
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env->pc = next_pc; |
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cpu_loop_exit(); |
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} |
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void helper_trapa(uint32_t tra)
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{ |
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env->tra = tra << 2;
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raise_exception(0x160, GETPC());
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} |
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void helper_movcal(uint32_t address, uint32_t value)
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{ |
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if (cpu_sh4_is_cached (env, address))
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{ |
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memory_content *r = malloc (sizeof(memory_content));
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r->address = address; |
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r->value = value; |
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r->next = NULL;
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*(env->movcal_backup_tail) = r; |
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env->movcal_backup_tail = &(r->next); |
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} |
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} |
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void helper_discard_movcal_backup(void) |
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{ |
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memory_content *current = env->movcal_backup; |
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while(current)
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{ |
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memory_content *next = current->next; |
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free (current); |
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env->movcal_backup = current = next; |
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if (current == NULL) |
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env->movcal_backup_tail = &(env->movcal_backup); |
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} |
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} |
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void helper_ocbi(uint32_t address)
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{ |
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memory_content **current = &(env->movcal_backup); |
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while (*current)
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{ |
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uint32_t a = (*current)->address; |
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if ((a & ~0x1F) == (address & ~0x1F)) |
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{ |
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memory_content *next = (*current)->next; |
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stl(a, (*current)->value); |
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if (next == NULL) |
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{ |
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env->movcal_backup_tail = current; |
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} |
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free (*current); |
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*current = next; |
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break;
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} |
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} |
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} |
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uint32_t helper_addc(uint32_t arg0, uint32_t arg1) |
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{ |
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uint32_t tmp0, tmp1; |
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tmp1 = arg0 + arg1; |
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tmp0 = arg1; |
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arg1 = tmp1 + (env->sr & 1);
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if (tmp0 > tmp1)
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env->sr |= SR_T; |
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else
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env->sr &= ~SR_T; |
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if (tmp1 > arg1)
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env->sr |= SR_T; |
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return arg1;
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} |
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uint32_t helper_addv(uint32_t arg0, uint32_t arg1) |
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{ |
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uint32_t dest, src, ans; |
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if ((int32_t) arg1 >= 0) |
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dest = 0;
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else
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dest = 1;
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if ((int32_t) arg0 >= 0) |
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src = 0;
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else
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src = 1;
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src += dest; |
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arg1 += arg0; |
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if ((int32_t) arg1 >= 0) |
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ans = 0;
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else
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ans = 1;
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ans += dest; |
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if (src == 0 || src == 2) { |
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if (ans == 1) |
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env->sr |= SR_T; |
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else
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env->sr &= ~SR_T; |
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} else
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env->sr &= ~SR_T; |
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return arg1;
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} |
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#define T (env->sr & SR_T)
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#define Q (env->sr & SR_Q ? 1 : 0) |
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#define M (env->sr & SR_M ? 1 : 0) |
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#define SETT env->sr |= SR_T
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#define CLRT env->sr &= ~SR_T
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#define SETQ env->sr |= SR_Q
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#define CLRQ env->sr &= ~SR_Q
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#define SETM env->sr |= SR_M
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#define CLRM env->sr &= ~SR_M
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uint32_t helper_div1(uint32_t arg0, uint32_t arg1) |
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{ |
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uint32_t tmp0, tmp2; |
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uint8_t old_q, tmp1 = 0xff;
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//printf("div1 arg0=0x%08x arg1=0x%08x M=%d Q=%d T=%d\n", arg0, arg1, M, Q, T);
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old_q = Q; |
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if ((0x80000000 & arg1) != 0) |
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SETQ; |
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else
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CLRQ; |
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tmp2 = arg0; |
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arg1 <<= 1;
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arg1 |= T; |
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switch (old_q) {
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case 0: |
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switch (M) {
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case 0: |
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tmp0 = arg1; |
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arg1 -= tmp2; |
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tmp1 = arg1 > tmp0; |
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switch (Q) {
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case 0: |
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if (tmp1)
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SETQ; |
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else
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CLRQ; |
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break;
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case 1: |
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if (tmp1 == 0) |
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SETQ; |
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else
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CLRQ; |
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break;
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} |
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break;
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case 1: |
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tmp0 = arg1; |
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arg1 += tmp2; |
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tmp1 = arg1 < tmp0; |
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switch (Q) {
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case 0: |
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if (tmp1 == 0) |
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SETQ; |
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else
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CLRQ; |
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break;
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case 1: |
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if (tmp1)
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SETQ; |
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else
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CLRQ; |
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break;
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} |
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break;
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} |
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break;
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case 1: |
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switch (M) {
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case 0: |
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tmp0 = arg1; |
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arg1 += tmp2; |
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tmp1 = arg1 < tmp0; |
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switch (Q) {
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case 0: |
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if (tmp1)
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SETQ; |
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else
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CLRQ; |
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break;
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case 1: |
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if (tmp1 == 0) |
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SETQ; |
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else
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CLRQ; |
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break;
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} |
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break;
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case 1: |
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tmp0 = arg1; |
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arg1 -= tmp2; |
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tmp1 = arg1 > tmp0; |
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switch (Q) {
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case 0: |
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if (tmp1 == 0) |
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SETQ; |
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else
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CLRQ; |
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break;
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case 1: |
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if (tmp1)
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SETQ; |
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else
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CLRQ; |
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break;
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} |
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break;
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} |
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break;
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} |
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if (Q == M)
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SETT; |
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else
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CLRT; |
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//printf("Output: arg1=0x%08x M=%d Q=%d T=%d\n", arg1, M, Q, T);
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return arg1;
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} |
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void helper_macl(uint32_t arg0, uint32_t arg1)
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{ |
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int64_t res; |
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res = ((uint64_t) env->mach << 32) | env->macl;
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res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1; |
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env->mach = (res >> 32) & 0xffffffff; |
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env->macl = res & 0xffffffff;
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if (env->sr & SR_S) {
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if (res < 0) |
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env->mach |= 0xffff0000;
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else
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env->mach &= 0x00007fff;
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} |
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} |
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void helper_macw(uint32_t arg0, uint32_t arg1)
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{ |
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int64_t res; |
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res = ((uint64_t) env->mach << 32) | env->macl;
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res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1; |
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env->mach = (res >> 32) & 0xffffffff; |
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env->macl = res & 0xffffffff;
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if (env->sr & SR_S) {
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if (res < -0x80000000) { |
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env->mach = 1;
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env->macl = 0x80000000;
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} else if (res > 0x000000007fffffff) { |
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env->mach = 1;
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env->macl = 0x7fffffff;
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} |
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} |
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} |
382 |
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uint32_t helper_subc(uint32_t arg0, uint32_t arg1) |
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{ |
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uint32_t tmp0, tmp1; |
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tmp1 = arg1 - arg0; |
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tmp0 = arg1; |
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arg1 = tmp1 - (env->sr & SR_T); |
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if (tmp0 < tmp1)
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env->sr |= SR_T; |
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else
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env->sr &= ~SR_T; |
394 |
if (tmp1 < arg1)
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env->sr |= SR_T; |
396 |
return arg1;
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} |
398 |
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uint32_t helper_subv(uint32_t arg0, uint32_t arg1) |
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{ |
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int32_t dest, src, ans; |
402 |
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if ((int32_t) arg1 >= 0) |
404 |
dest = 0;
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405 |
else
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406 |
dest = 1;
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407 |
if ((int32_t) arg0 >= 0) |
408 |
src = 0;
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else
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src = 1;
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src += dest; |
412 |
arg1 -= arg0; |
413 |
if ((int32_t) arg1 >= 0) |
414 |
ans = 0;
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else
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ans = 1;
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417 |
ans += dest; |
418 |
if (src == 1) { |
419 |
if (ans == 1) |
420 |
env->sr |= SR_T; |
421 |
else
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422 |
env->sr &= ~SR_T; |
423 |
} else
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424 |
env->sr &= ~SR_T; |
425 |
return arg1;
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} |
427 |
|
428 |
static inline void set_t(void) |
429 |
{ |
430 |
env->sr |= SR_T; |
431 |
} |
432 |
|
433 |
static inline void clr_t(void) |
434 |
{ |
435 |
env->sr &= ~SR_T; |
436 |
} |
437 |
|
438 |
void helper_ld_fpscr(uint32_t val)
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439 |
{ |
440 |
env->fpscr = val & FPSCR_MASK; |
441 |
if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
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442 |
set_float_rounding_mode(float_round_to_zero, &env->fp_status); |
443 |
} else {
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444 |
set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
445 |
} |
446 |
set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
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447 |
} |
448 |
|
449 |
static void update_fpscr(void *retaddr) |
450 |
{ |
451 |
int xcpt, cause, enable;
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452 |
|
453 |
xcpt = get_float_exception_flags(&env->fp_status); |
454 |
|
455 |
/* Clear the flag entries */
|
456 |
env->fpscr &= ~FPSCR_FLAG_MASK; |
457 |
|
458 |
if (unlikely(xcpt)) {
|
459 |
if (xcpt & float_flag_invalid) {
|
460 |
env->fpscr |= FPSCR_FLAG_V; |
461 |
} |
462 |
if (xcpt & float_flag_divbyzero) {
|
463 |
env->fpscr |= FPSCR_FLAG_Z; |
464 |
} |
465 |
if (xcpt & float_flag_overflow) {
|
466 |
env->fpscr |= FPSCR_FLAG_O; |
467 |
} |
468 |
if (xcpt & float_flag_underflow) {
|
469 |
env->fpscr |= FPSCR_FLAG_U; |
470 |
} |
471 |
if (xcpt & float_flag_inexact) {
|
472 |
env->fpscr |= FPSCR_FLAG_I; |
473 |
} |
474 |
|
475 |
/* Accumulate in cause entries */
|
476 |
env->fpscr |= (env->fpscr & FPSCR_FLAG_MASK) |
477 |
<< (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT); |
478 |
|
479 |
/* Generate an exception if enabled */
|
480 |
cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT; |
481 |
enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT; |
482 |
if (cause & enable) {
|
483 |
cpu_restore_state_from_retaddr(retaddr); |
484 |
env->exception_index = 0x120;
|
485 |
cpu_loop_exit(); |
486 |
} |
487 |
} |
488 |
} |
489 |
|
490 |
float32 helper_fabs_FT(float32 t0) |
491 |
{ |
492 |
return float32_abs(t0);
|
493 |
} |
494 |
|
495 |
float64 helper_fabs_DT(float64 t0) |
496 |
{ |
497 |
return float64_abs(t0);
|
498 |
} |
499 |
|
500 |
float32 helper_fadd_FT(float32 t0, float32 t1) |
501 |
{ |
502 |
set_float_exception_flags(0, &env->fp_status);
|
503 |
t0 = float32_add(t0, t1, &env->fp_status); |
504 |
update_fpscr(GETPC()); |
505 |
return t0;
|
506 |
} |
507 |
|
508 |
float64 helper_fadd_DT(float64 t0, float64 t1) |
509 |
{ |
510 |
set_float_exception_flags(0, &env->fp_status);
|
511 |
t0 = float64_add(t0, t1, &env->fp_status); |
512 |
update_fpscr(GETPC()); |
513 |
return t0;
|
514 |
} |
515 |
|
516 |
void helper_fcmp_eq_FT(float32 t0, float32 t1)
|
517 |
{ |
518 |
int relation;
|
519 |
|
520 |
set_float_exception_flags(0, &env->fp_status);
|
521 |
relation = float32_compare(t0, t1, &env->fp_status); |
522 |
if (unlikely(relation == float_relation_unordered)) {
|
523 |
update_fpscr(GETPC()); |
524 |
} else if (relation == float_relation_equal) { |
525 |
set_t(); |
526 |
} else {
|
527 |
clr_t(); |
528 |
} |
529 |
} |
530 |
|
531 |
void helper_fcmp_eq_DT(float64 t0, float64 t1)
|
532 |
{ |
533 |
int relation;
|
534 |
|
535 |
set_float_exception_flags(0, &env->fp_status);
|
536 |
relation = float64_compare(t0, t1, &env->fp_status); |
537 |
if (unlikely(relation == float_relation_unordered)) {
|
538 |
update_fpscr(GETPC()); |
539 |
} else if (relation == float_relation_equal) { |
540 |
set_t(); |
541 |
} else {
|
542 |
clr_t(); |
543 |
} |
544 |
} |
545 |
|
546 |
void helper_fcmp_gt_FT(float32 t0, float32 t1)
|
547 |
{ |
548 |
int relation;
|
549 |
|
550 |
set_float_exception_flags(0, &env->fp_status);
|
551 |
relation = float32_compare(t0, t1, &env->fp_status); |
552 |
if (unlikely(relation == float_relation_unordered)) {
|
553 |
update_fpscr(GETPC()); |
554 |
} else if (relation == float_relation_greater) { |
555 |
set_t(); |
556 |
} else {
|
557 |
clr_t(); |
558 |
} |
559 |
} |
560 |
|
561 |
void helper_fcmp_gt_DT(float64 t0, float64 t1)
|
562 |
{ |
563 |
int relation;
|
564 |
|
565 |
set_float_exception_flags(0, &env->fp_status);
|
566 |
relation = float64_compare(t0, t1, &env->fp_status); |
567 |
if (unlikely(relation == float_relation_unordered)) {
|
568 |
update_fpscr(GETPC()); |
569 |
} else if (relation == float_relation_greater) { |
570 |
set_t(); |
571 |
} else {
|
572 |
clr_t(); |
573 |
} |
574 |
} |
575 |
|
576 |
float64 helper_fcnvsd_FT_DT(float32 t0) |
577 |
{ |
578 |
float64 ret; |
579 |
set_float_exception_flags(0, &env->fp_status);
|
580 |
ret = float32_to_float64(t0, &env->fp_status); |
581 |
update_fpscr(GETPC()); |
582 |
return ret;
|
583 |
} |
584 |
|
585 |
float32 helper_fcnvds_DT_FT(float64 t0) |
586 |
{ |
587 |
float32 ret; |
588 |
set_float_exception_flags(0, &env->fp_status);
|
589 |
ret = float64_to_float32(t0, &env->fp_status); |
590 |
update_fpscr(GETPC()); |
591 |
return ret;
|
592 |
} |
593 |
|
594 |
float32 helper_fdiv_FT(float32 t0, float32 t1) |
595 |
{ |
596 |
set_float_exception_flags(0, &env->fp_status);
|
597 |
t0 = float32_div(t0, t1, &env->fp_status); |
598 |
update_fpscr(GETPC()); |
599 |
return t0;
|
600 |
} |
601 |
|
602 |
float64 helper_fdiv_DT(float64 t0, float64 t1) |
603 |
{ |
604 |
set_float_exception_flags(0, &env->fp_status);
|
605 |
t0 = float64_div(t0, t1, &env->fp_status); |
606 |
update_fpscr(GETPC()); |
607 |
return t0;
|
608 |
} |
609 |
|
610 |
float32 helper_float_FT(uint32_t t0) |
611 |
{ |
612 |
float32 ret; |
613 |
set_float_exception_flags(0, &env->fp_status);
|
614 |
ret = int32_to_float32(t0, &env->fp_status); |
615 |
update_fpscr(GETPC()); |
616 |
return ret;
|
617 |
} |
618 |
|
619 |
float64 helper_float_DT(uint32_t t0) |
620 |
{ |
621 |
float64 ret; |
622 |
set_float_exception_flags(0, &env->fp_status);
|
623 |
ret = int32_to_float64(t0, &env->fp_status); |
624 |
update_fpscr(GETPC()); |
625 |
return ret;
|
626 |
} |
627 |
|
628 |
float32 helper_fmac_FT(float32 t0, float32 t1, float32 t2) |
629 |
{ |
630 |
set_float_exception_flags(0, &env->fp_status);
|
631 |
t0 = float32_mul(t0, t1, &env->fp_status); |
632 |
t0 = float32_add(t0, t2, &env->fp_status); |
633 |
update_fpscr(GETPC()); |
634 |
return t0;
|
635 |
} |
636 |
|
637 |
float32 helper_fmul_FT(float32 t0, float32 t1) |
638 |
{ |
639 |
set_float_exception_flags(0, &env->fp_status);
|
640 |
t0 = float32_mul(t0, t1, &env->fp_status); |
641 |
update_fpscr(GETPC()); |
642 |
return t0;
|
643 |
} |
644 |
|
645 |
float64 helper_fmul_DT(float64 t0, float64 t1) |
646 |
{ |
647 |
set_float_exception_flags(0, &env->fp_status);
|
648 |
t0 = float64_mul(t0, t1, &env->fp_status); |
649 |
update_fpscr(GETPC()); |
650 |
return t0;
|
651 |
} |
652 |
|
653 |
float32 helper_fneg_T(float32 t0) |
654 |
{ |
655 |
return float32_chs(t0);
|
656 |
} |
657 |
|
658 |
float32 helper_fsqrt_FT(float32 t0) |
659 |
{ |
660 |
set_float_exception_flags(0, &env->fp_status);
|
661 |
t0 = float32_sqrt(t0, &env->fp_status); |
662 |
update_fpscr(GETPC()); |
663 |
return t0;
|
664 |
} |
665 |
|
666 |
float64 helper_fsqrt_DT(float64 t0) |
667 |
{ |
668 |
set_float_exception_flags(0, &env->fp_status);
|
669 |
t0 = float64_sqrt(t0, &env->fp_status); |
670 |
update_fpscr(GETPC()); |
671 |
return t0;
|
672 |
} |
673 |
|
674 |
float32 helper_fsub_FT(float32 t0, float32 t1) |
675 |
{ |
676 |
set_float_exception_flags(0, &env->fp_status);
|
677 |
t0 = float32_sub(t0, t1, &env->fp_status); |
678 |
update_fpscr(GETPC()); |
679 |
return t0;
|
680 |
} |
681 |
|
682 |
float64 helper_fsub_DT(float64 t0, float64 t1) |
683 |
{ |
684 |
set_float_exception_flags(0, &env->fp_status);
|
685 |
t0 = float64_sub(t0, t1, &env->fp_status); |
686 |
update_fpscr(GETPC()); |
687 |
return t0;
|
688 |
} |
689 |
|
690 |
uint32_t helper_ftrc_FT(float32 t0) |
691 |
{ |
692 |
uint32_t ret; |
693 |
set_float_exception_flags(0, &env->fp_status);
|
694 |
ret = float32_to_int32_round_to_zero(t0, &env->fp_status); |
695 |
update_fpscr(GETPC()); |
696 |
return ret;
|
697 |
} |
698 |
|
699 |
uint32_t helper_ftrc_DT(float64 t0) |
700 |
{ |
701 |
uint32_t ret; |
702 |
set_float_exception_flags(0, &env->fp_status);
|
703 |
ret = float64_to_int32_round_to_zero(t0, &env->fp_status); |
704 |
update_fpscr(GETPC()); |
705 |
return ret;
|
706 |
} |
707 |
|
708 |
void helper_fipr(uint32_t m, uint32_t n)
|
709 |
{ |
710 |
int bank, i;
|
711 |
float32 r, p; |
712 |
|
713 |
bank = (env->sr & FPSCR_FR) ? 16 : 0; |
714 |
r = float32_zero; |
715 |
set_float_exception_flags(0, &env->fp_status);
|
716 |
|
717 |
for (i = 0 ; i < 4 ; i++) { |
718 |
p = float32_mul(env->fregs[bank + m + i], |
719 |
env->fregs[bank + n + i], |
720 |
&env->fp_status); |
721 |
r = float32_add(r, p, &env->fp_status); |
722 |
} |
723 |
update_fpscr(GETPC()); |
724 |
|
725 |
env->fregs[bank + n + 3] = r;
|
726 |
} |
727 |
|
728 |
void helper_ftrv(uint32_t n)
|
729 |
{ |
730 |
int bank_matrix, bank_vector;
|
731 |
int i, j;
|
732 |
float32 r[4];
|
733 |
float32 p; |
734 |
|
735 |
bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16; |
736 |
bank_vector = (env->sr & FPSCR_FR) ? 16 : 0; |
737 |
set_float_exception_flags(0, &env->fp_status);
|
738 |
for (i = 0 ; i < 4 ; i++) { |
739 |
r[i] = float32_zero; |
740 |
for (j = 0 ; j < 4 ; j++) { |
741 |
p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
|
742 |
env->fregs[bank_vector + j], |
743 |
&env->fp_status); |
744 |
r[i] = float32_add(r[i], p, &env->fp_status); |
745 |
} |
746 |
} |
747 |
update_fpscr(GETPC()); |
748 |
|
749 |
for (i = 0 ; i < 4 ; i++) { |
750 |
env->fregs[bank_vector + i] = r[i]; |
751 |
} |
752 |
} |