Revision 61b24405 hw/ppc4xx_devs.c
| b/hw/ppc4xx_devs.c | ||
|---|---|---|
| 532 | 532 |
|
| 533 | 533 |
return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ); |
| 534 | 534 |
} |
| 535 |
|
|
| 536 |
/*****************************************************************************/ |
|
| 537 |
/* SDRAM controller */ |
|
| 538 |
typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; |
|
| 539 |
struct ppc4xx_sdram_t {
|
|
| 540 |
uint32_t addr; |
|
| 541 |
int nbanks; |
|
| 542 |
target_phys_addr_t ram_bases[4]; |
|
| 543 |
target_phys_addr_t ram_sizes[4]; |
|
| 544 |
uint32_t besr0; |
|
| 545 |
uint32_t besr1; |
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| 546 |
uint32_t bear; |
|
| 547 |
uint32_t cfg; |
|
| 548 |
uint32_t status; |
|
| 549 |
uint32_t rtr; |
|
| 550 |
uint32_t pmit; |
|
| 551 |
uint32_t bcr[4]; |
|
| 552 |
uint32_t tr; |
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| 553 |
uint32_t ecccfg; |
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| 554 |
uint32_t eccesr; |
|
| 555 |
qemu_irq irq; |
|
| 556 |
}; |
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| 557 |
|
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| 558 |
enum {
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| 559 |
SDRAM0_CFGADDR = 0x010, |
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| 560 |
SDRAM0_CFGDATA = 0x011, |
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| 561 |
}; |
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| 562 |
|
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| 563 |
/* XXX: TOFIX: some patches have made this code become inconsistent: |
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| 564 |
* there are type inconsistencies, mixing target_phys_addr_t, target_ulong |
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| 565 |
* and uint32_t |
|
| 566 |
*/ |
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| 567 |
static uint32_t sdram_bcr (target_phys_addr_t ram_base, |
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| 568 |
target_phys_addr_t ram_size) |
|
| 569 |
{
|
|
| 570 |
uint32_t bcr; |
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| 571 |
|
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| 572 |
switch (ram_size) {
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| 573 |
case (4 * 1024 * 1024): |
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| 574 |
bcr = 0x00000000; |
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| 575 |
break; |
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| 576 |
case (8 * 1024 * 1024): |
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| 577 |
bcr = 0x00020000; |
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| 578 |
break; |
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| 579 |
case (16 * 1024 * 1024): |
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| 580 |
bcr = 0x00040000; |
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| 581 |
break; |
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| 582 |
case (32 * 1024 * 1024): |
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| 583 |
bcr = 0x00060000; |
|
| 584 |
break; |
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| 585 |
case (64 * 1024 * 1024): |
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| 586 |
bcr = 0x00080000; |
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| 587 |
break; |
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| 588 |
case (128 * 1024 * 1024): |
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| 589 |
bcr = 0x000A0000; |
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| 590 |
break; |
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| 591 |
case (256 * 1024 * 1024): |
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| 592 |
bcr = 0x000C0000; |
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| 593 |
break; |
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| 594 |
default: |
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| 595 |
printf("%s: invalid RAM size " PADDRX "\n", __func__, ram_size);
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| 596 |
return 0x00000000; |
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| 597 |
} |
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| 598 |
bcr |= ram_base & 0xFF800000; |
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| 599 |
bcr |= 1; |
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| 600 |
|
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| 601 |
return bcr; |
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| 602 |
} |
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| 603 |
|
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| 604 |
static always_inline target_phys_addr_t sdram_base (uint32_t bcr) |
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| 605 |
{
|
|
| 606 |
return bcr & 0xFF800000; |
|
| 607 |
} |
|
| 608 |
|
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| 609 |
static target_ulong sdram_size (uint32_t bcr) |
|
| 610 |
{
|
|
| 611 |
target_ulong size; |
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| 612 |
int sh; |
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| 613 |
|
|
| 614 |
sh = (bcr >> 17) & 0x7; |
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| 615 |
if (sh == 7) |
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| 616 |
size = -1; |
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| 617 |
else |
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| 618 |
size = (4 * 1024 * 1024) << sh; |
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| 619 |
|
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| 620 |
return size; |
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| 621 |
} |
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| 622 |
|
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| 623 |
static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled) |
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| 624 |
{
|
|
| 625 |
if (*bcrp & 0x00000001) {
|
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| 626 |
/* Unmap RAM */ |
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| 627 |
#ifdef DEBUG_SDRAM |
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| 628 |
printf("%s: unmap RAM area " PADDRX " " ADDRX "\n",
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| 629 |
__func__, sdram_base(*bcrp), sdram_size(*bcrp)); |
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| 630 |
#endif |
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| 631 |
cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp), |
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| 632 |
IO_MEM_UNASSIGNED); |
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| 633 |
} |
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| 634 |
*bcrp = bcr & 0xFFDEE001; |
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| 635 |
if (enabled && (bcr & 0x00000001)) {
|
|
| 636 |
#ifdef DEBUG_SDRAM |
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| 637 |
printf("%s: Map RAM area " PADDRX " " ADDRX "\n",
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| 638 |
__func__, sdram_base(bcr), sdram_size(bcr)); |
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| 639 |
#endif |
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| 640 |
cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr), |
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| 641 |
sdram_base(bcr) | IO_MEM_RAM); |
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| 642 |
} |
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| 643 |
} |
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| 644 |
|
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| 645 |
static void sdram_map_bcr (ppc4xx_sdram_t *sdram) |
|
| 646 |
{
|
|
| 647 |
int i; |
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| 648 |
|
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| 649 |
for (i = 0; i < sdram->nbanks; i++) {
|
|
| 650 |
if (sdram->ram_sizes[i] != 0) {
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| 651 |
sdram_set_bcr(&sdram->bcr[i], |
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| 652 |
sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]), |
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| 653 |
1); |
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| 654 |
} else {
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| 655 |
sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0); |
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| 656 |
} |
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| 657 |
} |
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| 658 |
} |
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| 659 |
|
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| 660 |
static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) |
|
| 661 |
{
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| 662 |
int i; |
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| 663 |
|
|
| 664 |
for (i = 0; i < sdram->nbanks; i++) {
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| 665 |
#ifdef DEBUG_SDRAM |
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| 666 |
printf("%s: Unmap RAM area " PADDRX " " ADDRX "\n",
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| 667 |
__func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i])); |
|
| 668 |
#endif |
|
| 669 |
cpu_register_physical_memory(sdram_base(sdram->bcr[i]), |
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| 670 |
sdram_size(sdram->bcr[i]), |
|
| 671 |
IO_MEM_UNASSIGNED); |
|
| 672 |
} |
|
| 673 |
} |
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| 674 |
|
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| 675 |
static target_ulong dcr_read_sdram (void *opaque, int dcrn) |
|
| 676 |
{
|
|
| 677 |
ppc4xx_sdram_t *sdram; |
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| 678 |
target_ulong ret; |
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| 679 |
|
|
| 680 |
sdram = opaque; |
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| 681 |
switch (dcrn) {
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| 682 |
case SDRAM0_CFGADDR: |
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| 683 |
ret = sdram->addr; |
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| 684 |
break; |
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| 685 |
case SDRAM0_CFGDATA: |
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| 686 |
switch (sdram->addr) {
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| 687 |
case 0x00: /* SDRAM_BESR0 */ |
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| 688 |
ret = sdram->besr0; |
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| 689 |
break; |
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| 690 |
case 0x08: /* SDRAM_BESR1 */ |
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| 691 |
ret = sdram->besr1; |
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| 692 |
break; |
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| 693 |
case 0x10: /* SDRAM_BEAR */ |
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| 694 |
ret = sdram->bear; |
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| 695 |
break; |
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| 696 |
case 0x20: /* SDRAM_CFG */ |
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| 697 |
ret = sdram->cfg; |
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| 698 |
break; |
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| 699 |
case 0x24: /* SDRAM_STATUS */ |
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| 700 |
ret = sdram->status; |
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| 701 |
break; |
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| 702 |
case 0x30: /* SDRAM_RTR */ |
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| 703 |
ret = sdram->rtr; |
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| 704 |
break; |
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| 705 |
case 0x34: /* SDRAM_PMIT */ |
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| 706 |
ret = sdram->pmit; |
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| 707 |
break; |
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| 708 |
case 0x40: /* SDRAM_B0CR */ |
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| 709 |
ret = sdram->bcr[0]; |
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| 710 |
break; |
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| 711 |
case 0x44: /* SDRAM_B1CR */ |
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| 712 |
ret = sdram->bcr[1]; |
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| 713 |
break; |
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| 714 |
case 0x48: /* SDRAM_B2CR */ |
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| 715 |
ret = sdram->bcr[2]; |
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| 716 |
break; |
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| 717 |
case 0x4C: /* SDRAM_B3CR */ |
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| 718 |
ret = sdram->bcr[3]; |
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| 719 |
break; |
|
| 720 |
case 0x80: /* SDRAM_TR */ |
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| 721 |
ret = -1; /* ? */ |
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| 722 |
break; |
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| 723 |
case 0x94: /* SDRAM_ECCCFG */ |
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| 724 |
ret = sdram->ecccfg; |
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| 725 |
break; |
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| 726 |
case 0x98: /* SDRAM_ECCESR */ |
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| 727 |
ret = sdram->eccesr; |
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| 728 |
break; |
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| 729 |
default: /* Error */ |
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| 730 |
ret = -1; |
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| 731 |
break; |
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| 732 |
} |
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| 733 |
break; |
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| 734 |
default: |
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| 735 |
/* Avoid gcc warning */ |
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| 736 |
ret = 0x00000000; |
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| 737 |
break; |
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| 738 |
} |
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| 739 |
|
|
| 740 |
return ret; |
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| 741 |
} |
|
| 742 |
|
|
| 743 |
static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val) |
|
| 744 |
{
|
|
| 745 |
ppc4xx_sdram_t *sdram; |
|
| 746 |
|
|
| 747 |
sdram = opaque; |
|
| 748 |
switch (dcrn) {
|
|
| 749 |
case SDRAM0_CFGADDR: |
|
| 750 |
sdram->addr = val; |
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| 751 |
break; |
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| 752 |
case SDRAM0_CFGDATA: |
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| 753 |
switch (sdram->addr) {
|
|
| 754 |
case 0x00: /* SDRAM_BESR0 */ |
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| 755 |
sdram->besr0 &= ~val; |
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| 756 |
break; |
|
| 757 |
case 0x08: /* SDRAM_BESR1 */ |
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| 758 |
sdram->besr1 &= ~val; |
|
| 759 |
break; |
|
| 760 |
case 0x10: /* SDRAM_BEAR */ |
|
| 761 |
sdram->bear = val; |
|
| 762 |
break; |
|
| 763 |
case 0x20: /* SDRAM_CFG */ |
|
| 764 |
val &= 0xFFE00000; |
|
| 765 |
if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
|
|
| 766 |
#ifdef DEBUG_SDRAM |
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| 767 |
printf("%s: enable SDRAM controller\n", __func__);
|
|
| 768 |
#endif |
|
| 769 |
/* validate all RAM mappings */ |
|
| 770 |
sdram_map_bcr(sdram); |
|
| 771 |
sdram->status &= ~0x80000000; |
|
| 772 |
} else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
|
|
| 773 |
#ifdef DEBUG_SDRAM |
|
| 774 |
printf("%s: disable SDRAM controller\n", __func__);
|
|
| 775 |
#endif |
|
| 776 |
/* invalidate all RAM mappings */ |
|
| 777 |
sdram_unmap_bcr(sdram); |
|
| 778 |
sdram->status |= 0x80000000; |
|
| 779 |
} |
|
| 780 |
if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) |
|
| 781 |
sdram->status |= 0x40000000; |
|
| 782 |
else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) |
|
| 783 |
sdram->status &= ~0x40000000; |
|
| 784 |
sdram->cfg = val; |
|
| 785 |
break; |
|
| 786 |
case 0x24: /* SDRAM_STATUS */ |
|
| 787 |
/* Read-only register */ |
|
| 788 |
break; |
|
| 789 |
case 0x30: /* SDRAM_RTR */ |
|
| 790 |
sdram->rtr = val & 0x3FF80000; |
|
| 791 |
break; |
|
| 792 |
case 0x34: /* SDRAM_PMIT */ |
|
| 793 |
sdram->pmit = (val & 0xF8000000) | 0x07C00000; |
|
| 794 |
break; |
|
| 795 |
case 0x40: /* SDRAM_B0CR */ |
|
| 796 |
sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000); |
|
| 797 |
break; |
|
| 798 |
case 0x44: /* SDRAM_B1CR */ |
|
| 799 |
sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000); |
|
| 800 |
break; |
|
| 801 |
case 0x48: /* SDRAM_B2CR */ |
|
| 802 |
sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000); |
|
| 803 |
break; |
|
| 804 |
case 0x4C: /* SDRAM_B3CR */ |
|
| 805 |
sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000); |
|
| 806 |
break; |
|
| 807 |
case 0x80: /* SDRAM_TR */ |
|
| 808 |
sdram->tr = val & 0x018FC01F; |
|
| 809 |
break; |
|
| 810 |
case 0x94: /* SDRAM_ECCCFG */ |
|
| 811 |
sdram->ecccfg = val & 0x00F00000; |
|
| 812 |
break; |
|
| 813 |
case 0x98: /* SDRAM_ECCESR */ |
|
| 814 |
val &= 0xFFF0F000; |
|
| 815 |
if (sdram->eccesr == 0 && val != 0) |
|
| 816 |
qemu_irq_raise(sdram->irq); |
|
| 817 |
else if (sdram->eccesr != 0 && val == 0) |
|
| 818 |
qemu_irq_lower(sdram->irq); |
|
| 819 |
sdram->eccesr = val; |
|
| 820 |
break; |
|
| 821 |
default: /* Error */ |
|
| 822 |
break; |
|
| 823 |
} |
|
| 824 |
break; |
|
| 825 |
} |
|
| 826 |
} |
|
| 827 |
|
|
| 828 |
static void sdram_reset (void *opaque) |
|
| 829 |
{
|
|
| 830 |
ppc4xx_sdram_t *sdram; |
|
| 831 |
|
|
| 832 |
sdram = opaque; |
|
| 833 |
sdram->addr = 0x00000000; |
|
| 834 |
sdram->bear = 0x00000000; |
|
| 835 |
sdram->besr0 = 0x00000000; /* No error */ |
|
| 836 |
sdram->besr1 = 0x00000000; /* No error */ |
|
| 837 |
sdram->cfg = 0x00000000; |
|
| 838 |
sdram->ecccfg = 0x00000000; /* No ECC */ |
|
| 839 |
sdram->eccesr = 0x00000000; /* No error */ |
|
| 840 |
sdram->pmit = 0x07C00000; |
|
| 841 |
sdram->rtr = 0x05F00000; |
|
| 842 |
sdram->tr = 0x00854009; |
|
| 843 |
/* We pre-initialize RAM banks */ |
|
| 844 |
sdram->status = 0x00000000; |
|
| 845 |
sdram->cfg = 0x00800000; |
|
| 846 |
sdram_unmap_bcr(sdram); |
|
| 847 |
} |
|
| 848 |
|
|
| 849 |
void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks, |
|
| 850 |
target_phys_addr_t *ram_bases, |
|
| 851 |
target_phys_addr_t *ram_sizes, |
|
| 852 |
int do_init) |
|
| 853 |
{
|
|
| 854 |
ppc4xx_sdram_t *sdram; |
|
| 855 |
|
|
| 856 |
sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t)); |
|
| 857 |
if (sdram != NULL) {
|
|
| 858 |
sdram->irq = irq; |
|
| 859 |
sdram->nbanks = nbanks; |
|
| 860 |
memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t)); |
|
| 861 |
memcpy(sdram->ram_bases, ram_bases, |
|
| 862 |
nbanks * sizeof(target_phys_addr_t)); |
|
| 863 |
memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t)); |
|
| 864 |
memcpy(sdram->ram_sizes, ram_sizes, |
|
| 865 |
nbanks * sizeof(target_phys_addr_t)); |
|
| 866 |
sdram_reset(sdram); |
|
| 867 |
qemu_register_reset(&sdram_reset, sdram); |
|
| 868 |
ppc_dcr_register(env, SDRAM0_CFGADDR, |
|
| 869 |
sdram, &dcr_read_sdram, &dcr_write_sdram); |
|
| 870 |
ppc_dcr_register(env, SDRAM0_CFGDATA, |
|
| 871 |
sdram, &dcr_read_sdram, &dcr_write_sdram); |
|
| 872 |
if (do_init) |
|
| 873 |
sdram_map_bcr(sdram); |
|
| 874 |
} |
|
| 875 |
} |
|
Also available in: Unified diff