Revision 61c04807

b/target-ppc/helper.h
1
#ifndef DEF_HELPER
2
#define DEF_HELPER(ret, name, params) ret name params;
3
#endif
4

  
5
DEF_HELPER(target_ulong, do_load_cr, (void))
6
DEF_HELPER(void, do_print_mem_EA, (target_ulong))
7
DEF_HELPER(void, do_store_cr, (uint32_t))
8

  
9
#if !defined (CONFIG_USER_ONLY)
10
DEF_HELPER(void, do_store_msr, (target_ulong))
11
#if defined(TARGET_PPC64)
12
DEF_HELPER(void, do_store_msr_32, (target_ulong))
13
#endif
14
#endif
15

  
16
DEF_HELPER(target_ulong, do_popcntb, (target_ulong))
17
#if defined(TARGET_PPC64)
18
DEF_HELPER(target_ulong, do_popcntb_64, (target_ulong))
19
#endif
20

  
21

  
b/target-ppc/op.c
122 122
#define REG 31
123 123
#include "op_template.h"
124 124

  
125
void OPPROTO op_print_mem_EA (void)
126
{
127
    do_print_mem_EA(T0);
128
    RETURN();
129
}
130

  
131 125
/* PowerPC state maintenance operations */
132 126
/* set_Rc0 */
133 127
void OPPROTO op_set_Rc0 (void)
......
136 130
    RETURN();
137 131
}
138 132

  
139
/* Constants load */
140
void OPPROTO op_reset_T0 (void)
141
{
142
    T0 = 0;
143
    RETURN();
144
}
145

  
146 133
void OPPROTO op_set_T0 (void)
147 134
{
148 135
    T0 = (uint32_t)PARAM1;
......
203 190
    do_raise_exception_err(PARAM1, PARAM2);
204 191
}
205 192

  
206
void OPPROTO op_update_nip (void)
207
{
208
    env->nip = (uint32_t)PARAM1;
209
    RETURN();
210
}
211

  
212
#if defined(TARGET_PPC64)
213
void OPPROTO op_update_nip_64 (void)
214
{
215
    env->nip = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
216
    RETURN();
217
}
218
#endif
219

  
220 193
void OPPROTO op_debug (void)
221 194
{
222 195
    do_raise_exception(EXCP_DEBUG);
223 196
}
224 197

  
225
/* Load/store special registers */
226
void OPPROTO op_load_cr (void)
227
{
228
    do_load_cr();
229
    RETURN();
230
}
231

  
232
void OPPROTO op_store_cr (void)
233
{
234
    do_store_cr(PARAM1);
235
    RETURN();
236
}
237

  
238
void OPPROTO op_load_cro (void)
239
{
240
    T0 = env->crf[PARAM1];
241
    RETURN();
242
}
243

  
244
void OPPROTO op_store_cro (void)
245
{
246
    env->crf[PARAM1] = T0;
247
    RETURN();
248
}
249

  
250 198
void OPPROTO op_load_xer_cr (void)
251 199
{
252 200
    T0 = (xer_so << 3) | (xer_ov << 2) | (xer_ca << 1);
......
352 300
}
353 301
#endif
354 302

  
355
void OPPROTO op_load_msr (void)
356
{
357
    T0 = env->msr;
358
    RETURN();
359
}
360

  
361
void OPPROTO op_store_msr (void)
362
{
363
    do_store_msr();
364
    RETURN();
365
}
366

  
367
#if defined (TARGET_PPC64)
368
void OPPROTO op_store_msr_32 (void)
369
{
370
    T0 = (env->msr & ~0xFFFFFFFFULL) | (T0 & 0xFFFFFFFF);
371
    do_store_msr();
372
    RETURN();
373
}
374
#endif
375

  
376 303
void OPPROTO op_update_riee (void)
377 304
{
378 305
    /* We don't call do_store_msr here as we won't trigger
......
1377 1304
    RETURN();
1378 1305
}
1379 1306

  
1380
void OPPROTO op_popcntb (void)
1381
{
1382
    do_popcntb();
1383
    RETURN();
1384
}
1385

  
1386
#if defined(TARGET_PPC64)
1387
void OPPROTO op_popcntb_64 (void)
1388
{
1389
    do_popcntb_64();
1390
    RETURN();
1391
}
1392
#endif
1393

  
1394 1307
/***                            Integer logical                            ***/
1395 1308
/* and */
1396 1309
void OPPROTO op_and (void)
b/target-ppc/op_helper.c
68 68

  
69 69
/*****************************************************************************/
70 70
/* Registers load and stores */
71
void do_load_cr (void)
71
target_ulong do_load_cr (void)
72 72
{
73
    T0 = (env->crf[0] << 28) |
74
        (env->crf[1] << 24) |
75
        (env->crf[2] << 20) |
76
        (env->crf[3] << 16) |
77
        (env->crf[4] << 12) |
78
        (env->crf[5] << 8) |
79
        (env->crf[6] << 4) |
80
        (env->crf[7] << 0);
73
    return (env->crf[0] << 28) |
74
           (env->crf[1] << 24) |
75
           (env->crf[2] << 20) |
76
           (env->crf[3] << 16) |
77
           (env->crf[4] << 12) |
78
           (env->crf[5] << 8) |
79
           (env->crf[6] << 4) |
80
           (env->crf[7] << 0);
81 81
}
82 82

  
83 83
void do_store_cr (uint32_t mask)
......
429 429
}
430 430
#endif
431 431

  
432
void do_popcntb (void)
432
target_ulong do_popcntb (target_ulong t0)
433 433
{
434 434
    uint32_t ret;
435 435
    int i;
436 436

  
437 437
    ret = 0;
438 438
    for (i = 0; i < 32; i += 8)
439
        ret |= ctpop8((T0 >> i) & 0xFF) << i;
440
    T0 = ret;
439
        ret |= ctpop8((t0 >> i) & 0xFF) << i;
440
    return ret;
441 441
}
442 442

  
443 443
#if defined(TARGET_PPC64)
444
void do_popcntb_64 (void)
444
target_ulong do_popcntb_64 (target_ulong t0)
445 445
{
446 446
    uint64_t ret;
447 447
    int i;
448 448

  
449 449
    ret = 0;
450 450
    for (i = 0; i < 64; i += 8)
451
        ret |= ctpop8((T0 >> i) & 0xFF) << i;
452
    T0 = ret;
451
        ret |= ctpop8((t0 >> i) & 0xFF) << i;
452
    return ret;
453 453
}
454 454
#endif
455 455

  
......
1404 1404
#if !defined (CONFIG_USER_ONLY)
1405 1405
void cpu_dump_rfi (target_ulong RA, target_ulong msr);
1406 1406

  
1407
void do_store_msr (void)
1407
void do_store_msr (target_ulong t0)
1408 1408
{
1409
    T0 = hreg_store_msr(env, T0, 0);
1410
    if (T0 != 0) {
1409
    t0 = hreg_store_msr(env, t0, 0);
1410
    if (t0 != 0) {
1411 1411
        env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1412
        do_raise_exception(T0);
1412
        do_raise_exception(t0);
1413 1413
    }
1414 1414
}
1415 1415

  
1416
#if defined (TARGET_PPC64)
1417
void do_store_msr_32 (target_ulong t0)
1418
{
1419
    t0 = (env->msr & ~0xFFFFFFFFULL) | (t0 & 0xFFFFFFFF);
1420
    do_store_msr(t0);
1421
}
1422
#endif
1423

  
1416 1424
static always_inline void __do_rfi (target_ulong nip, target_ulong msr,
1417 1425
                                    target_ulong msrm, int keep_msrh)
1418 1426
{
b/target-ppc/op_helper.h
51 51
void do_print_mem_EA (target_ulong EA);
52 52

  
53 53
/* Registers load and stores */
54
void do_load_cr (void);
55 54
void do_store_cr (uint32_t mask);
56 55
#if defined(TARGET_PPC64)
57 56
void do_store_pri (int prio);
......
88 87
void do_subfzeo_64 (void);
89 88
void do_srad (void);
90 89
#endif
91
void do_popcntb (void);
92
#if defined(TARGET_PPC64)
93
void do_popcntb_64 (void);
94
#endif
95 90

  
96 91
/* Floating-point arithmetic helpers */
97 92
void do_compute_fprf (int set_class);
......
138 133
void do_td (int flags);
139 134
#endif
140 135
#if !defined(CONFIG_USER_ONLY)
141
void do_store_msr (void);
142 136
void do_rfi (void);
143 137
#if defined(TARGET_PPC64)
144 138
void do_rfid (void);
b/target-ppc/translate.c
26 26
#include "cpu.h"
27 27
#include "exec-all.h"
28 28
#include "disas.h"
29
#include "helper.h"
29 30
#include "tcg-op.h"
30 31
#include "qemu-common.h"
31 32

  
......
65 66
    cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
66 67
    cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
67 68
#endif
69

  
70
    /* register helpers */
71
#undef DEF_HELPER
72
#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
73
#include "helper.h"
74

  
68 75
    done_init = 1;
69 76
}
70 77

  
78
static inline void tcg_gen_helper_0_i(void *func, TCGv arg)
79
{
80
    TCGv tmp = tcg_const_i32(arg);
81

  
82
    tcg_gen_helper_0_1(func, tmp);
83
    tcg_temp_free(tmp);
84
}
85

  
86

  
71 87
#if defined(OPTIMIZE_FPRF_UPDATE)
72 88
static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
73 89
static uint16_t **gen_fprf_ptr;
......
249 265

  
250 266
static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
251 267
{
268
    TCGv tmp;
252 269
#if defined(TARGET_PPC64)
253 270
    if (ctx->sf_mode)
254
        gen_op_update_nip_64(nip >> 32, nip);
271
        tmp = tcg_const_i64(nip);
255 272
    else
256 273
#endif
257
        gen_op_update_nip(nip);
274
        tmp = tcg_const_i32((uint32_t)nip);
275

  
276
    tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUState, nip));
277
    tcg_temp_free(tmp);
258 278
}
259 279

  
260 280
#define GEN_EXCP(ctx, excp, error)                                            \
......
1305 1325
        gen_op_load_gpr_T1(rB(ctx->opcode));
1306 1326
        gen_op_xor();
1307 1327
    } else {
1308
        gen_op_reset_T0();
1328
        tcg_gen_movi_tl(cpu_T[0], 0);
1309 1329
    }
1310 1330
    gen_op_store_T0_gpr(rA(ctx->opcode));
1311 1331
    if (unlikely(Rc(ctx->opcode) != 0))
......
1376 1396
    gen_op_load_gpr_T0(rS(ctx->opcode));
1377 1397
#if defined(TARGET_PPC64)
1378 1398
    if (ctx->sf_mode)
1379
        gen_op_popcntb_64();
1399
        tcg_gen_helper_1_1(do_popcntb_64, cpu_T[0], cpu_T[0]);
1380 1400
    else
1381 1401
#endif
1382
        gen_op_popcntb();
1402
        tcg_gen_helper_1_1(do_popcntb, cpu_T[0], cpu_T[0]);
1383 1403
    gen_op_store_T0_gpr(rA(ctx->opcode));
1384 1404
}
1385 1405

  
......
2100 2120
            gen_op_addi(simm);
2101 2121
    }
2102 2122
#ifdef DEBUG_MEMORY_ACCESSES
2103
    gen_op_print_mem_EA();
2123
    tcg_gen_helper_0_0(do_print_mem_EA);
2104 2124
#endif
2105 2125
}
2106 2126

  
......
2114 2134
        gen_op_add();
2115 2135
    }
2116 2136
#ifdef DEBUG_MEMORY_ACCESSES
2117
    gen_op_print_mem_EA();
2137
    tcg_gen_helper_0_0(do_print_mem_EA);
2118 2138
#endif
2119 2139
}
2120 2140

  
2121 2141
static always_inline void gen_addr_register (DisasContext *ctx)
2122 2142
{
2123 2143
    if (rA(ctx->opcode) == 0) {
2124
        gen_op_reset_T0();
2144
        tcg_gen_movi_tl(cpu_T[0], 0);
2125 2145
    } else {
2126 2146
        gen_op_load_gpr_T0(rA(ctx->opcode));
2127 2147
    }
2128 2148
#ifdef DEBUG_MEMORY_ACCESSES
2129
    gen_op_print_mem_EA();
2149
    tcg_gen_helper_0_0(do_print_mem_EA);
2130 2150
#endif
2131 2151
}
2132 2152

  
......
3225 3245
        crm = CRM(ctx->opcode);
3226 3246
        if (likely((crm ^ (crm - 1)) == 0)) {
3227 3247
            crn = ffs(crm);
3228
            gen_op_load_cro(7 - crn);
3248
            tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUState, crf[7 - crn]));
3229 3249
        }
3230 3250
    } else {
3231
        gen_op_load_cr();
3251
        tcg_gen_helper_1_0(do_load_cr, cpu_T[0]);
3232 3252
    }
3233 3253
    gen_op_store_T0_gpr(rD(ctx->opcode));
3234 3254
}
......
3243 3263
        GEN_EXCP_PRIVREG(ctx);
3244 3264
        return;
3245 3265
    }
3246
    gen_op_load_msr();
3266
    tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUState, msr));
3247 3267
    gen_op_store_T0_gpr(rD(ctx->opcode));
3248 3268
#endif
3249 3269
}
......
3327 3347
    if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3328 3348
        crn = ffs(crm);
3329 3349
        gen_op_srli_T0(crn * 4);
3330
        gen_op_andi_T0(0xF);
3331
        gen_op_store_cro(7 - crn);
3350
        tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xF);
3351
        tcg_gen_st8_tl(cpu_T[0], cpu_env, offsetof(CPUState, crf[7 - crn]));
3332 3352
    } else {
3333
        gen_op_store_cr(crm);
3353
        tcg_gen_helper_0_i(do_store_cr, crm);
3334 3354
    }
3335 3355
}
3336 3356

  
......
3355 3375
         *      directly from ppc_store_msr
3356 3376
         */
3357 3377
        gen_update_nip(ctx, ctx->nip);
3358
        gen_op_store_msr();
3378
        tcg_gen_helper_0_1(do_store_msr, cpu_T[0]);
3359 3379
        /* Must stop the translation as machine state (may have) changed */
3360 3380
        /* Note that mtmsr is not always defined as context-synchronizing */
3361 3381
        ctx->exception = POWERPC_EXCP_STOP;
......
3385 3405
        gen_update_nip(ctx, ctx->nip);
3386 3406
#if defined(TARGET_PPC64)
3387 3407
        if (!ctx->sf_mode)
3388
            gen_op_store_msr_32();
3408
            tcg_gen_helper_0_1(do_store_msr_32, cpu_T[0]);
3389 3409
        else
3390 3410
#endif
3391
            gen_op_store_msr();
3411
            tcg_gen_helper_0_1(do_store_msr, cpu_T[0]);
3392 3412
        /* Must stop the translation as machine state (may have) changed */
3393 3413
        /* Note that mtmsrd is not always defined as context-synchronizing */
3394 3414
        ctx->exception = POWERPC_EXCP_STOP;

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