Revision 61d3cf93 hw/usb-ohci.c
| b/hw/usb-ohci.c | ||
|---|---|---|
| 30 | 30 |
#include "qemu-timer.h" |
| 31 | 31 |
#include "usb.h" |
| 32 | 32 |
#include "pci.h" |
| 33 |
#include "pxa.h" |
|
| 34 |
#include "devices.h" |
|
| 35 | 33 |
#include "usb-ohci.h" |
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#include "sysbus.h" |
|
| 35 |
#include "qdev-addr.h" |
|
| 36 | 36 |
|
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//#define DEBUG_OHCI |
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/* Dump packet contents. */ |
| ... | ... | |
| 59 | 59 |
uint32_t ctrl; |
| 60 | 60 |
} OHCIPort; |
| 61 | 61 |
|
| 62 |
enum ohci_type {
|
|
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OHCI_TYPE_PCI, |
|
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OHCI_TYPE_PXA, |
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OHCI_TYPE_SM501, |
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}; |
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|
|
| 68 | 62 |
typedef struct {
|
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USBBus bus; |
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qemu_irq irq; |
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enum ohci_type type; |
|
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int mem; |
| 73 | 66 |
int num_ports; |
| 74 | 67 |
const char *name; |
| ... | ... | |
| 1662 | 1655 |
}; |
| 1663 | 1656 |
|
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static void usb_ohci_init(OHCIState *ohci, DeviceState *dev, |
| 1665 |
int num_ports, int devfn, |
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qemu_irq irq, enum ohci_type type, |
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const char *name, uint32_t localmem_base) |
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int num_ports, uint32_t localmem_base) |
|
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{
|
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int i; |
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|
| ... | ... | |
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|
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ohci->mem = cpu_register_io_memory(ohci_readfn, ohci_writefn, ohci); |
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ohci->localmem_base = localmem_base; |
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ohci->name = name; |
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| 1690 | 1680 |
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ohci->irq = irq; |
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ohci->type = type; |
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ohci->name = dev->info->name; |
|
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|
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usb_bus_new(&ohci->bus, dev); |
| 1695 | 1684 |
ohci->num_ports = num_ports; |
| ... | ... | |
| 1726 | 1715 |
/* TODO: RST# value should be 0. */ |
| 1727 | 1716 |
ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ |
| 1728 | 1717 |
|
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usb_ohci_init(&ohci->state, &dev->qdev, num_ports, |
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ohci->pci_dev.devfn, ohci->pci_dev.irq[0], |
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OHCI_TYPE_PCI, ohci->pci_dev.name, 0); |
|
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usb_ohci_init(&ohci->state, &dev->qdev, num_ports, 0); |
|
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ohci->state.irq = ohci->pci_dev.irq[0]; |
|
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|
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/* TODO: avoid cast below by using dev */ |
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pci_register_bar((struct PCIDevice *)ohci, 0, 256, |
| ... | ... | |
| 1741 | 1729 |
pci_create_simple(bus, devfn, "pci-ohci"); |
| 1742 | 1730 |
} |
| 1743 | 1731 |
|
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void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn, |
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qemu_irq irq) |
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{
|
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OHCIState *ohci = (OHCIState *)qemu_mallocz(sizeof(OHCIState)); |
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|
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usb_ohci_init(ohci, NULL /* FIXME */, num_ports, devfn, irq, |
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OHCI_TYPE_PXA, "OHCI USB", 0); |
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|
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cpu_register_physical_memory(base, 0x1000, ohci->mem); |
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} |
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typedef struct {
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SysBusDevice busdev; |
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OHCIState ohci; |
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uint32_t num_ports; |
|
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target_phys_addr_t dma_offset; |
|
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} OHCISysBusState; |
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|
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void usb_ohci_init_sm501(uint32_t mmio_base, uint32_t localmem_base, |
|
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int num_ports, int devfn, qemu_irq irq) |
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static int ohci_init_pxa(SysBusDevice *dev) |
|
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{
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OHCIState *ohci = (OHCIState *)qemu_mallocz(sizeof(OHCIState));
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OHCISysBusState *s = FROM_SYSBUS(OHCISysBusState, dev);
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usb_ohci_init(ohci, NULL /* FIXME */, num_ports, devfn, irq, |
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OHCI_TYPE_SM501, "OHCI USB", localmem_base); |
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usb_ohci_init(&s->ohci, &dev->qdev, s->num_ports, s->dma_offset); |
|
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sysbus_init_irq(dev, &s->ohci.irq); |
|
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sysbus_init_mmio(dev, 0x1000, s->ohci.mem); |
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| 1762 | 1746 |
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cpu_register_physical_memory(mmio_base, 0x1000, ohci->mem);
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return 0;
|
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} |
| 1765 | 1749 |
|
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static PCIDeviceInfo ohci_info = {
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static PCIDeviceInfo ohci_pci_info = {
|
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.qdev.name = "pci-ohci", |
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.qdev.desc = "Apple USB Controller", |
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.qdev.size = sizeof(OHCIPCIState), |
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.init = usb_ohci_initfn_pci, |
| 1771 | 1755 |
}; |
| 1772 | 1756 |
|
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static SysBusDeviceInfo ohci_sysbus_info = {
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.init = ohci_init_pxa, |
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.qdev.name = "sysbus-ohci", |
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.qdev.desc = "OHCI USB Controller", |
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.qdev.size = sizeof(OHCISysBusState), |
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
|
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DEFINE_PROP_TADDR("dma-offset", OHCISysBusState, dma_offset, 3),
|
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DEFINE_PROP_END_OF_LIST(), |
|
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} |
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}; |
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|
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static void ohci_register(void) |
| 1774 | 1770 |
{
|
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pci_qdev_register(&ohci_info); |
|
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pci_qdev_register(&ohci_pci_info); |
|
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sysbus_register_withprop(&ohci_sysbus_info); |
|
| 1776 | 1773 |
} |
| 1777 | 1774 |
device_init(ohci_register); |
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