root / target-mips / helper.c @ 6276c767
History | View | Annotate | Download (19 kB)
1 | 6af0bf9c | bellard | /*
|
---|---|---|---|
2 | 6af0bf9c | bellard | * MIPS emulation helpers for qemu.
|
3 | 5fafdf24 | ths | *
|
4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
|
5 | 6af0bf9c | bellard | *
|
6 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
|
7 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
|
9 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
|
10 | 6af0bf9c | bellard | *
|
11 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
|
12 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | 6af0bf9c | bellard | * Lesser General Public License for more details.
|
15 | 6af0bf9c | bellard | *
|
16 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
|
17 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
|
18 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
19 | 6af0bf9c | bellard | */
|
20 | e37e863f | bellard | #include <stdarg.h> |
21 | e37e863f | bellard | #include <stdlib.h> |
22 | e37e863f | bellard | #include <stdio.h> |
23 | e37e863f | bellard | #include <string.h> |
24 | e37e863f | bellard | #include <inttypes.h> |
25 | e37e863f | bellard | #include <signal.h> |
26 | e37e863f | bellard | #include <assert.h> |
27 | e37e863f | bellard | |
28 | e37e863f | bellard | #include "cpu.h" |
29 | e37e863f | bellard | #include "exec-all.h" |
30 | 6af0bf9c | bellard | |
31 | 43057ab1 | bellard | enum {
|
32 | 43057ab1 | bellard | TLBRET_DIRTY = -4,
|
33 | 43057ab1 | bellard | TLBRET_INVALID = -3,
|
34 | 43057ab1 | bellard | TLBRET_NOMATCH = -2,
|
35 | 43057ab1 | bellard | TLBRET_BADADDR = -1,
|
36 | 43057ab1 | bellard | TLBRET_MATCH = 0
|
37 | 43057ab1 | bellard | }; |
38 | 43057ab1 | bellard | |
39 | 29929e34 | ths | /* no MMU emulation */
|
40 | 29929e34 | ths | int no_mmu_map_address (CPUState *env, target_ulong *physical, int *prot, |
41 | 6af0bf9c | bellard | target_ulong address, int rw, int access_type) |
42 | 6af0bf9c | bellard | { |
43 | 29929e34 | ths | *physical = address; |
44 | 29929e34 | ths | *prot = PAGE_READ | PAGE_WRITE; |
45 | 29929e34 | ths | return TLBRET_MATCH;
|
46 | 29929e34 | ths | } |
47 | 29929e34 | ths | |
48 | 29929e34 | ths | /* fixed mapping MMU emulation */
|
49 | 29929e34 | ths | int fixed_mmu_map_address (CPUState *env, target_ulong *physical, int *prot, |
50 | 29929e34 | ths | target_ulong address, int rw, int access_type) |
51 | 29929e34 | ths | { |
52 | 29929e34 | ths | if (address <= (int32_t)0x7FFFFFFFUL) { |
53 | 29929e34 | ths | if (!(env->CP0_Status & (1 << CP0St_ERL))) |
54 | 29929e34 | ths | *physical = address + 0x40000000UL;
|
55 | 29929e34 | ths | else
|
56 | 29929e34 | ths | *physical = address; |
57 | 29929e34 | ths | } else if (address <= (int32_t)0xBFFFFFFFUL) |
58 | 29929e34 | ths | *physical = address & 0x1FFFFFFF;
|
59 | 29929e34 | ths | else
|
60 | 29929e34 | ths | *physical = address; |
61 | 29929e34 | ths | |
62 | 29929e34 | ths | *prot = PAGE_READ | PAGE_WRITE; |
63 | 29929e34 | ths | return TLBRET_MATCH;
|
64 | 29929e34 | ths | } |
65 | 29929e34 | ths | |
66 | 29929e34 | ths | /* MIPS32/MIPS64 R4000-style MMU emulation */
|
67 | 29929e34 | ths | int r4k_map_address (CPUState *env, target_ulong *physical, int *prot, |
68 | 29929e34 | ths | target_ulong address, int rw, int access_type) |
69 | 29929e34 | ths | { |
70 | 925fd0f2 | ths | uint8_t ASID = env->CP0_EntryHi & 0xFF;
|
71 | 3b1c8be4 | ths | int i;
|
72 | 6af0bf9c | bellard | |
73 | ead9360e | ths | for (i = 0; i < env->tlb->tlb_in_use; i++) { |
74 | ead9360e | ths | r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i]; |
75 | 3b1c8be4 | ths | /* 1k pages are not supported. */
|
76 | f2e9ebef | ths | target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
77 | 3b1c8be4 | ths | target_ulong tag = address & ~mask; |
78 | f2e9ebef | ths | target_ulong VPN = tlb->VPN & ~mask; |
79 | 540635ba | ths | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
80 | e034e2c3 | ths | tag &= env->SEGMask; |
81 | 100ce988 | ths | #endif
|
82 | 3b1c8be4 | ths | |
83 | 6af0bf9c | bellard | /* Check ASID, virtual page number & size */
|
84 | f2e9ebef | ths | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
85 | 6af0bf9c | bellard | /* TLB match */
|
86 | f2e9ebef | ths | int n = !!(address & mask & ~(mask >> 1)); |
87 | 6af0bf9c | bellard | /* Check access rights */
|
88 | f2e9ebef | ths | if (!(n ? tlb->V1 : tlb->V0))
|
89 | 43057ab1 | bellard | return TLBRET_INVALID;
|
90 | f2e9ebef | ths | if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { |
91 | 3b1c8be4 | ths | *physical = tlb->PFN[n] | (address & (mask >> 1));
|
92 | 9fb63ac2 | bellard | *prot = PAGE_READ; |
93 | 98c1b82b | pbrook | if (n ? tlb->D1 : tlb->D0)
|
94 | 9fb63ac2 | bellard | *prot |= PAGE_WRITE; |
95 | 43057ab1 | bellard | return TLBRET_MATCH;
|
96 | 6af0bf9c | bellard | } |
97 | 43057ab1 | bellard | return TLBRET_DIRTY;
|
98 | 6af0bf9c | bellard | } |
99 | 6af0bf9c | bellard | } |
100 | 43057ab1 | bellard | return TLBRET_NOMATCH;
|
101 | 6af0bf9c | bellard | } |
102 | 6af0bf9c | bellard | |
103 | 43057ab1 | bellard | static int get_physical_address (CPUState *env, target_ulong *physical, |
104 | 43057ab1 | bellard | int *prot, target_ulong address,
|
105 | 43057ab1 | bellard | int rw, int access_type) |
106 | 6af0bf9c | bellard | { |
107 | b4ab4b4e | ths | /* User mode can only access useg/xuseg */
|
108 | 43057ab1 | bellard | int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
|
109 | 671880e6 | ths | int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
|
110 | 671880e6 | ths | int kernel_mode = !user_mode && !supervisor_mode;
|
111 | 540635ba | ths | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
112 | b4ab4b4e | ths | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
113 | b4ab4b4e | ths | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; |
114 | b4ab4b4e | ths | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
115 | b4ab4b4e | ths | #endif
|
116 | 43057ab1 | bellard | int ret = TLBRET_MATCH;
|
117 | 43057ab1 | bellard | |
118 | 6af0bf9c | bellard | #if 0
|
119 | 6af0bf9c | bellard | if (logfile) {
|
120 | 6af0bf9c | bellard | fprintf(logfile, "user mode %d h %08x\n",
|
121 | 6af0bf9c | bellard | user_mode, env->hflags);
|
122 | 6af0bf9c | bellard | }
|
123 | 6af0bf9c | bellard | #endif
|
124 | b4ab4b4e | ths | |
125 | b4ab4b4e | ths | if (address <= (int32_t)0x7FFFFFFFUL) { |
126 | b4ab4b4e | ths | /* useg */
|
127 | 996ba2cc | ths | if (env->CP0_Status & (1 << CP0St_ERL)) { |
128 | 29929e34 | ths | *physical = address & 0xFFFFFFFF;
|
129 | 6af0bf9c | bellard | *prot = PAGE_READ | PAGE_WRITE; |
130 | 996ba2cc | ths | } else {
|
131 | ead9360e | ths | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
132 | 6af0bf9c | bellard | } |
133 | 540635ba | ths | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
134 | 89fc88da | ths | } else if (address < 0x4000000000000000ULL) { |
135 | b4ab4b4e | ths | /* xuseg */
|
136 | e034e2c3 | ths | if (UX && address < (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { |
137 | ead9360e | ths | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
138 | b4ab4b4e | ths | } else {
|
139 | b4ab4b4e | ths | ret = TLBRET_BADADDR; |
140 | b4ab4b4e | ths | } |
141 | 89fc88da | ths | } else if (address < 0x8000000000000000ULL) { |
142 | b4ab4b4e | ths | /* xsseg */
|
143 | 671880e6 | ths | if ((supervisor_mode || kernel_mode) &&
|
144 | 671880e6 | ths | SX && address < (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
|
145 | ead9360e | ths | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
146 | b4ab4b4e | ths | } else {
|
147 | b4ab4b4e | ths | ret = TLBRET_BADADDR; |
148 | b4ab4b4e | ths | } |
149 | 89fc88da | ths | } else if (address < 0xC000000000000000ULL) { |
150 | b4ab4b4e | ths | /* xkphys */
|
151 | 89fc88da | ths | /* XXX: Assumes PABITS = 36 (correct for MIPS64R1) */
|
152 | 671880e6 | ths | if (kernel_mode && KX &&
|
153 | 89fc88da | ths | (address & 0x07FFFFFFFFFFFFFFULL) < 0x0000000FFFFFFFFFULL) { |
154 | 89fc88da | ths | *physical = address & 0x0000000FFFFFFFFFULL;
|
155 | b4ab4b4e | ths | *prot = PAGE_READ | PAGE_WRITE; |
156 | b4ab4b4e | ths | } else {
|
157 | b4ab4b4e | ths | ret = TLBRET_BADADDR; |
158 | b4ab4b4e | ths | } |
159 | 89fc88da | ths | } else if (address < 0xFFFFFFFF80000000ULL) { |
160 | b4ab4b4e | ths | /* xkseg */
|
161 | 671880e6 | ths | if (kernel_mode && KX &&
|
162 | 671880e6 | ths | address < (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
|
163 | ead9360e | ths | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
164 | b4ab4b4e | ths | } else {
|
165 | b4ab4b4e | ths | ret = TLBRET_BADADDR; |
166 | b4ab4b4e | ths | } |
167 | b4ab4b4e | ths | #endif
|
168 | 5dc4b744 | ths | } else if (address < (int32_t)0xA0000000UL) { |
169 | 6af0bf9c | bellard | /* kseg0 */
|
170 | 671880e6 | ths | if (kernel_mode) {
|
171 | 671880e6 | ths | *physical = address - (int32_t)0x80000000UL;
|
172 | 671880e6 | ths | *prot = PAGE_READ | PAGE_WRITE; |
173 | 671880e6 | ths | } else {
|
174 | 671880e6 | ths | ret = TLBRET_BADADDR; |
175 | 671880e6 | ths | } |
176 | 5dc4b744 | ths | } else if (address < (int32_t)0xC0000000UL) { |
177 | 6af0bf9c | bellard | /* kseg1 */
|
178 | 671880e6 | ths | if (kernel_mode) {
|
179 | 671880e6 | ths | *physical = address - (int32_t)0xA0000000UL;
|
180 | 671880e6 | ths | *prot = PAGE_READ | PAGE_WRITE; |
181 | 671880e6 | ths | } else {
|
182 | 671880e6 | ths | ret = TLBRET_BADADDR; |
183 | 671880e6 | ths | } |
184 | 5dc4b744 | ths | } else if (address < (int32_t)0xE0000000UL) { |
185 | 89fc88da | ths | /* sseg (kseg2) */
|
186 | 671880e6 | ths | if (supervisor_mode || kernel_mode) {
|
187 | 671880e6 | ths | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
188 | 671880e6 | ths | } else {
|
189 | 671880e6 | ths | ret = TLBRET_BADADDR; |
190 | 671880e6 | ths | } |
191 | 6af0bf9c | bellard | } else {
|
192 | 6af0bf9c | bellard | /* kseg3 */
|
193 | 6af0bf9c | bellard | /* XXX: debug segment is not emulated */
|
194 | 671880e6 | ths | if (kernel_mode) {
|
195 | 671880e6 | ths | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
196 | 671880e6 | ths | } else {
|
197 | 671880e6 | ths | ret = TLBRET_BADADDR; |
198 | 671880e6 | ths | } |
199 | 6af0bf9c | bellard | } |
200 | 6af0bf9c | bellard | #if 0
|
201 | 6af0bf9c | bellard | if (logfile) {
|
202 | 3594c774 | ths | fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
|
203 | c570fd16 | ths | address, rw, access_type, *physical, *prot, ret);
|
204 | 6af0bf9c | bellard | }
|
205 | 6af0bf9c | bellard | #endif
|
206 | 6af0bf9c | bellard | |
207 | 6af0bf9c | bellard | return ret;
|
208 | 6af0bf9c | bellard | } |
209 | 6af0bf9c | bellard | |
210 | 5fafdf24 | ths | #if defined(CONFIG_USER_ONLY)
|
211 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
212 | 6af0bf9c | bellard | { |
213 | 6af0bf9c | bellard | return addr;
|
214 | 6af0bf9c | bellard | } |
215 | 6af0bf9c | bellard | #else
|
216 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
217 | 6af0bf9c | bellard | { |
218 | 6af0bf9c | bellard | target_ulong phys_addr; |
219 | 6af0bf9c | bellard | int prot;
|
220 | 6af0bf9c | bellard | |
221 | 6af0bf9c | bellard | if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) |
222 | 6af0bf9c | bellard | return -1; |
223 | 6af0bf9c | bellard | return phys_addr;
|
224 | 6af0bf9c | bellard | } |
225 | 6af0bf9c | bellard | |
226 | 6af0bf9c | bellard | void cpu_mips_init_mmu (CPUState *env)
|
227 | 6af0bf9c | bellard | { |
228 | 6af0bf9c | bellard | } |
229 | 6af0bf9c | bellard | #endif /* !defined(CONFIG_USER_ONLY) */ |
230 | 6af0bf9c | bellard | |
231 | 6af0bf9c | bellard | int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
232 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
233 | 6af0bf9c | bellard | { |
234 | 6af0bf9c | bellard | target_ulong physical; |
235 | 6af0bf9c | bellard | int prot;
|
236 | 6af0bf9c | bellard | int exception = 0, error_code = 0; |
237 | 6af0bf9c | bellard | int access_type;
|
238 | 6af0bf9c | bellard | int ret = 0; |
239 | 6af0bf9c | bellard | |
240 | 6af0bf9c | bellard | if (logfile) {
|
241 | 4ad40f36 | bellard | #if 0
|
242 | 6af0bf9c | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
243 | 4ad40f36 | bellard | #endif
|
244 | 6ebbf390 | j_mayer | fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n", |
245 | 6ebbf390 | j_mayer | __func__, env->PC[env->current_tc], address, rw, mmu_idx, is_softmmu); |
246 | 6af0bf9c | bellard | } |
247 | 4ad40f36 | bellard | |
248 | 4ad40f36 | bellard | rw &= 1;
|
249 | 4ad40f36 | bellard | |
250 | 6af0bf9c | bellard | /* data access */
|
251 | 6af0bf9c | bellard | /* XXX: put correct access by using cpu_restore_state()
|
252 | 6af0bf9c | bellard | correctly */
|
253 | 6af0bf9c | bellard | access_type = ACCESS_INT; |
254 | 6af0bf9c | bellard | if (env->user_mode_only) {
|
255 | 6af0bf9c | bellard | /* user mode only emulation */
|
256 | 43057ab1 | bellard | ret = TLBRET_NOMATCH; |
257 | 6af0bf9c | bellard | goto do_fault;
|
258 | 6af0bf9c | bellard | } |
259 | 6af0bf9c | bellard | ret = get_physical_address(env, &physical, &prot, |
260 | 6af0bf9c | bellard | address, rw, access_type); |
261 | 6af0bf9c | bellard | if (logfile) {
|
262 | 3594c774 | ths | fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n", |
263 | 6af0bf9c | bellard | __func__, address, ret, physical, prot); |
264 | 6af0bf9c | bellard | } |
265 | 43057ab1 | bellard | if (ret == TLBRET_MATCH) {
|
266 | 43057ab1 | bellard | ret = tlb_set_page(env, address & TARGET_PAGE_MASK, |
267 | 43057ab1 | bellard | physical & TARGET_PAGE_MASK, prot, |
268 | 6ebbf390 | j_mayer | mmu_idx, is_softmmu); |
269 | 6af0bf9c | bellard | } else if (ret < 0) { |
270 | 6af0bf9c | bellard | do_fault:
|
271 | 6af0bf9c | bellard | switch (ret) {
|
272 | 6af0bf9c | bellard | default:
|
273 | 43057ab1 | bellard | case TLBRET_BADADDR:
|
274 | 6af0bf9c | bellard | /* Reference to kernel address from user mode or supervisor mode */
|
275 | 6af0bf9c | bellard | /* Reference to supervisor address from user mode */
|
276 | 6af0bf9c | bellard | if (rw)
|
277 | 6af0bf9c | bellard | exception = EXCP_AdES; |
278 | 6af0bf9c | bellard | else
|
279 | 6af0bf9c | bellard | exception = EXCP_AdEL; |
280 | 6af0bf9c | bellard | break;
|
281 | 43057ab1 | bellard | case TLBRET_NOMATCH:
|
282 | 6af0bf9c | bellard | /* No TLB match for a mapped address */
|
283 | 6af0bf9c | bellard | if (rw)
|
284 | 6af0bf9c | bellard | exception = EXCP_TLBS; |
285 | 6af0bf9c | bellard | else
|
286 | 6af0bf9c | bellard | exception = EXCP_TLBL; |
287 | 6af0bf9c | bellard | error_code = 1;
|
288 | 6af0bf9c | bellard | break;
|
289 | 43057ab1 | bellard | case TLBRET_INVALID:
|
290 | 6af0bf9c | bellard | /* TLB match with no valid bit */
|
291 | 6af0bf9c | bellard | if (rw)
|
292 | 6af0bf9c | bellard | exception = EXCP_TLBS; |
293 | 6af0bf9c | bellard | else
|
294 | 6af0bf9c | bellard | exception = EXCP_TLBL; |
295 | 6af0bf9c | bellard | break;
|
296 | 43057ab1 | bellard | case TLBRET_DIRTY:
|
297 | 6af0bf9c | bellard | /* TLB match but 'D' bit is cleared */
|
298 | 6af0bf9c | bellard | exception = EXCP_LTLBL; |
299 | 6af0bf9c | bellard | break;
|
300 | 3b46e624 | ths | |
301 | 6af0bf9c | bellard | } |
302 | 6af0bf9c | bellard | /* Raise exception */
|
303 | 6af0bf9c | bellard | env->CP0_BadVAddr = address; |
304 | 100ce988 | ths | env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
|
305 | 4ad40f36 | bellard | ((address >> 9) & 0x007ffff0); |
306 | 6af0bf9c | bellard | env->CP0_EntryHi = |
307 | 43057ab1 | bellard | (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); |
308 | 540635ba | ths | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
309 | e034e2c3 | ths | env->CP0_EntryHi &= env->SEGMask; |
310 | e034e2c3 | ths | env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | |
311 | e034e2c3 | ths | ((address & 0xC00000000000ULL) >> (env->SEGBITS - 9)) | |
312 | e034e2c3 | ths | ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9); |
313 | 100ce988 | ths | #endif
|
314 | 6af0bf9c | bellard | env->exception_index = exception; |
315 | 6af0bf9c | bellard | env->error_code = error_code; |
316 | 6af0bf9c | bellard | ret = 1;
|
317 | 6af0bf9c | bellard | } |
318 | 6af0bf9c | bellard | |
319 | 6af0bf9c | bellard | return ret;
|
320 | 6af0bf9c | bellard | } |
321 | 6af0bf9c | bellard | |
322 | ca7c2b1b | ths | #if defined(CONFIG_USER_ONLY)
|
323 | ca7c2b1b | ths | void do_interrupt (CPUState *env)
|
324 | ca7c2b1b | ths | { |
325 | ca7c2b1b | ths | env->exception_index = EXCP_NONE; |
326 | ca7c2b1b | ths | } |
327 | ca7c2b1b | ths | #else
|
328 | 6af0bf9c | bellard | void do_interrupt (CPUState *env)
|
329 | 6af0bf9c | bellard | { |
330 | aa328add | ths | target_ulong offset; |
331 | 6af0bf9c | bellard | int cause = -1; |
332 | 6af0bf9c | bellard | |
333 | 6af0bf9c | bellard | if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
334 | 3594c774 | ths | fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n", |
335 | ead9360e | ths | __func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index); |
336 | 6af0bf9c | bellard | } |
337 | 6af0bf9c | bellard | if (env->exception_index == EXCP_EXT_INTERRUPT &&
|
338 | 6af0bf9c | bellard | (env->hflags & MIPS_HFLAG_DM)) |
339 | 6af0bf9c | bellard | env->exception_index = EXCP_DINT; |
340 | 6af0bf9c | bellard | offset = 0x180;
|
341 | 6af0bf9c | bellard | switch (env->exception_index) {
|
342 | 6af0bf9c | bellard | case EXCP_DSS:
|
343 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DSS;
|
344 | 6af0bf9c | bellard | /* Debug single step cannot be raised inside a delay slot and
|
345 | 6af0bf9c | bellard | * resume will always occur on the next instruction
|
346 | 6af0bf9c | bellard | * (but we assume the pc has always been updated during
|
347 | 6af0bf9c | bellard | * code translation).
|
348 | 6af0bf9c | bellard | */
|
349 | ead9360e | ths | env->CP0_DEPC = env->PC[env->current_tc]; |
350 | 6af0bf9c | bellard | goto enter_debug_mode;
|
351 | 6af0bf9c | bellard | case EXCP_DINT:
|
352 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DINT;
|
353 | 6af0bf9c | bellard | goto set_DEPC;
|
354 | 6af0bf9c | bellard | case EXCP_DIB:
|
355 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DIB;
|
356 | 6af0bf9c | bellard | goto set_DEPC;
|
357 | 6af0bf9c | bellard | case EXCP_DBp:
|
358 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DBp;
|
359 | 6af0bf9c | bellard | goto set_DEPC;
|
360 | 6af0bf9c | bellard | case EXCP_DDBS:
|
361 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DDBS;
|
362 | 6af0bf9c | bellard | goto set_DEPC;
|
363 | 6af0bf9c | bellard | case EXCP_DDBL:
|
364 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DDBL;
|
365 | 6af0bf9c | bellard | set_DEPC:
|
366 | 4ad40f36 | bellard | if (env->hflags & MIPS_HFLAG_BMASK) {
|
367 | 6af0bf9c | bellard | /* If the exception was raised from a delay slot,
|
368 | aa328add | ths | come back to the jump. */
|
369 | ead9360e | ths | env->CP0_DEPC = env->PC[env->current_tc] - 4;
|
370 | 4ad40f36 | bellard | env->hflags &= ~MIPS_HFLAG_BMASK; |
371 | 6af0bf9c | bellard | } else {
|
372 | ead9360e | ths | env->CP0_DEPC = env->PC[env->current_tc]; |
373 | 6af0bf9c | bellard | } |
374 | 6af0bf9c | bellard | enter_debug_mode:
|
375 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
376 | 623a930e | ths | env->hflags &= ~(MIPS_HFLAG_KSU); |
377 | 6af0bf9c | bellard | /* EJTAG probe trap enable is not implemented... */
|
378 | 0a6de750 | ths | if (!(env->CP0_Status & (1 << CP0St_EXL))) |
379 | 0a6de750 | ths | env->CP0_Cause &= ~(1 << CP0Ca_BD);
|
380 | ead9360e | ths | env->PC[env->current_tc] = (int32_t)0xBFC00480;
|
381 | 6af0bf9c | bellard | break;
|
382 | 6af0bf9c | bellard | case EXCP_RESET:
|
383 | aa328add | ths | cpu_reset(env); |
384 | aa328add | ths | break;
|
385 | 6af0bf9c | bellard | case EXCP_SRESET:
|
386 | 24c7b0e3 | ths | env->CP0_Status |= (1 << CP0St_SR);
|
387 | fd88b6ab | ths | memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo)); |
388 | 6af0bf9c | bellard | goto set_error_EPC;
|
389 | 6af0bf9c | bellard | case EXCP_NMI:
|
390 | 24c7b0e3 | ths | env->CP0_Status |= (1 << CP0St_NMI);
|
391 | 6af0bf9c | bellard | set_error_EPC:
|
392 | 4ad40f36 | bellard | if (env->hflags & MIPS_HFLAG_BMASK) {
|
393 | 6af0bf9c | bellard | /* If the exception was raised from a delay slot,
|
394 | aa328add | ths | come back to the jump. */
|
395 | ead9360e | ths | env->CP0_ErrorEPC = env->PC[env->current_tc] - 4;
|
396 | ecd78a0a | pbrook | env->hflags &= ~MIPS_HFLAG_BMASK; |
397 | 6af0bf9c | bellard | } else {
|
398 | ead9360e | ths | env->CP0_ErrorEPC = env->PC[env->current_tc]; |
399 | 6af0bf9c | bellard | } |
400 | 24c7b0e3 | ths | env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); |
401 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
402 | 623a930e | ths | env->hflags &= ~(MIPS_HFLAG_KSU); |
403 | 0a6de750 | ths | if (!(env->CP0_Status & (1 << CP0St_EXL))) |
404 | 0a6de750 | ths | env->CP0_Cause &= ~(1 << CP0Ca_BD);
|
405 | ead9360e | ths | env->PC[env->current_tc] = (int32_t)0xBFC00000;
|
406 | 6af0bf9c | bellard | break;
|
407 | 6af0bf9c | bellard | case EXCP_MCHECK:
|
408 | 6af0bf9c | bellard | cause = 24;
|
409 | 6af0bf9c | bellard | goto set_EPC;
|
410 | 6af0bf9c | bellard | case EXCP_EXT_INTERRUPT:
|
411 | 6af0bf9c | bellard | cause = 0;
|
412 | 6af0bf9c | bellard | if (env->CP0_Cause & (1 << CP0Ca_IV)) |
413 | 6af0bf9c | bellard | offset = 0x200;
|
414 | 6af0bf9c | bellard | goto set_EPC;
|
415 | 6af0bf9c | bellard | case EXCP_DWATCH:
|
416 | 6af0bf9c | bellard | cause = 23;
|
417 | 6af0bf9c | bellard | /* XXX: TODO: manage defered watch exceptions */
|
418 | 6af0bf9c | bellard | goto set_EPC;
|
419 | 6af0bf9c | bellard | case EXCP_AdEL:
|
420 | 6af0bf9c | bellard | cause = 4;
|
421 | 6af0bf9c | bellard | goto set_EPC;
|
422 | beb811bd | ths | case EXCP_AdES:
|
423 | beb811bd | ths | cause = 5;
|
424 | beb811bd | ths | goto set_EPC;
|
425 | 6af0bf9c | bellard | case EXCP_TLBL:
|
426 | 6af0bf9c | bellard | cause = 2;
|
427 | 100ce988 | ths | if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { |
428 | 540635ba | ths | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
429 | 100ce988 | ths | int R = env->CP0_BadVAddr >> 62; |
430 | 100ce988 | ths | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
431 | 100ce988 | ths | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; |
432 | 100ce988 | ths | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
433 | 100ce988 | ths | |
434 | 100ce988 | ths | if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) |
435 | 100ce988 | ths | offset = 0x080;
|
436 | 100ce988 | ths | else
|
437 | 100ce988 | ths | #endif
|
438 | 100ce988 | ths | offset = 0x000;
|
439 | 100ce988 | ths | } |
440 | 6af0bf9c | bellard | goto set_EPC;
|
441 | 6af0bf9c | bellard | case EXCP_IBE:
|
442 | 6af0bf9c | bellard | cause = 6;
|
443 | 6af0bf9c | bellard | goto set_EPC;
|
444 | 6af0bf9c | bellard | case EXCP_DBE:
|
445 | 6af0bf9c | bellard | cause = 7;
|
446 | 6af0bf9c | bellard | goto set_EPC;
|
447 | 6af0bf9c | bellard | case EXCP_SYSCALL:
|
448 | 6af0bf9c | bellard | cause = 8;
|
449 | 6af0bf9c | bellard | goto set_EPC;
|
450 | 6af0bf9c | bellard | case EXCP_BREAK:
|
451 | 6af0bf9c | bellard | cause = 9;
|
452 | 6af0bf9c | bellard | goto set_EPC;
|
453 | 6af0bf9c | bellard | case EXCP_RI:
|
454 | 6af0bf9c | bellard | cause = 10;
|
455 | 6af0bf9c | bellard | goto set_EPC;
|
456 | 6af0bf9c | bellard | case EXCP_CpU:
|
457 | 6af0bf9c | bellard | cause = 11;
|
458 | 39d51eb8 | ths | env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
|
459 | 39d51eb8 | ths | (env->error_code << CP0Ca_CE); |
460 | 6af0bf9c | bellard | goto set_EPC;
|
461 | 6af0bf9c | bellard | case EXCP_OVERFLOW:
|
462 | 6af0bf9c | bellard | cause = 12;
|
463 | 6af0bf9c | bellard | goto set_EPC;
|
464 | 6af0bf9c | bellard | case EXCP_TRAP:
|
465 | 6af0bf9c | bellard | cause = 13;
|
466 | 6af0bf9c | bellard | goto set_EPC;
|
467 | 5a5012ec | ths | case EXCP_FPE:
|
468 | 5a5012ec | ths | cause = 15;
|
469 | 5a5012ec | ths | goto set_EPC;
|
470 | 6af0bf9c | bellard | case EXCP_LTLBL:
|
471 | 6af0bf9c | bellard | cause = 1;
|
472 | 6af0bf9c | bellard | goto set_EPC;
|
473 | 6af0bf9c | bellard | case EXCP_TLBS:
|
474 | 6af0bf9c | bellard | cause = 3;
|
475 | 100ce988 | ths | if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { |
476 | 540635ba | ths | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
477 | 100ce988 | ths | int R = env->CP0_BadVAddr >> 62; |
478 | 100ce988 | ths | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
479 | 100ce988 | ths | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; |
480 | 100ce988 | ths | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
481 | 100ce988 | ths | |
482 | 100ce988 | ths | if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) |
483 | 100ce988 | ths | offset = 0x080;
|
484 | 100ce988 | ths | else
|
485 | 100ce988 | ths | #endif
|
486 | 100ce988 | ths | offset = 0x000;
|
487 | 100ce988 | ths | } |
488 | 6276c767 | ths | goto set_EPC;
|
489 | 6276c767 | ths | case EXCP_THREAD:
|
490 | 6276c767 | ths | cause = 25;
|
491 | 6af0bf9c | bellard | set_EPC:
|
492 | 24c7b0e3 | ths | if (!(env->CP0_Status & (1 << CP0St_EXL))) { |
493 | 24c7b0e3 | ths | if (env->hflags & MIPS_HFLAG_BMASK) {
|
494 | 24c7b0e3 | ths | /* If the exception was raised from a delay slot,
|
495 | 24c7b0e3 | ths | come back to the jump. */
|
496 | ead9360e | ths | env->CP0_EPC = env->PC[env->current_tc] - 4;
|
497 | 39d51eb8 | ths | env->CP0_Cause |= (1 << CP0Ca_BD);
|
498 | 24c7b0e3 | ths | } else {
|
499 | ead9360e | ths | env->CP0_EPC = env->PC[env->current_tc]; |
500 | 24c7b0e3 | ths | env->CP0_Cause &= ~(1 << CP0Ca_BD);
|
501 | 24c7b0e3 | ths | } |
502 | 24c7b0e3 | ths | env->CP0_Status |= (1 << CP0St_EXL);
|
503 | 08fa4bab | ths | env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
504 | 623a930e | ths | env->hflags &= ~(MIPS_HFLAG_KSU); |
505 | 6af0bf9c | bellard | } |
506 | c53f4a62 | ths | env->hflags &= ~MIPS_HFLAG_BMASK; |
507 | aa328add | ths | if (env->CP0_Status & (1 << CP0St_BEV)) { |
508 | ead9360e | ths | env->PC[env->current_tc] = (int32_t)0xBFC00200;
|
509 | aa328add | ths | } else {
|
510 | ead9360e | ths | env->PC[env->current_tc] = (int32_t)(env->CP0_EBase & ~0x3ff);
|
511 | aa328add | ths | } |
512 | ead9360e | ths | env->PC[env->current_tc] += offset; |
513 | e58c8ba5 | ths | env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
|
514 | 6af0bf9c | bellard | break;
|
515 | 6af0bf9c | bellard | default:
|
516 | 6af0bf9c | bellard | if (logfile) {
|
517 | 6af0bf9c | bellard | fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
|
518 | 6af0bf9c | bellard | env->exception_index); |
519 | 6af0bf9c | bellard | } |
520 | 6af0bf9c | bellard | printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
|
521 | 6af0bf9c | bellard | exit(1);
|
522 | 6af0bf9c | bellard | } |
523 | 6af0bf9c | bellard | if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
524 | 3594c774 | ths | fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n" |
525 | 3594c774 | ths | " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", |
526 | ead9360e | ths | __func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index, |
527 | 6af0bf9c | bellard | env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, |
528 | 6af0bf9c | bellard | env->CP0_DEPC); |
529 | 6af0bf9c | bellard | } |
530 | 6af0bf9c | bellard | env->exception_index = EXCP_NONE; |
531 | 6af0bf9c | bellard | } |
532 | ca7c2b1b | ths | #endif /* !defined(CONFIG_USER_ONLY) */ |
533 | 2ee4aed8 | bellard | |
534 | 29929e34 | ths | void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra) |
535 | 2ee4aed8 | bellard | { |
536 | 29929e34 | ths | r4k_tlb_t *tlb; |
537 | 3b1c8be4 | ths | target_ulong addr; |
538 | 3b1c8be4 | ths | target_ulong end; |
539 | 3b1c8be4 | ths | uint8_t ASID = env->CP0_EntryHi & 0xFF;
|
540 | 3b1c8be4 | ths | target_ulong mask; |
541 | 2ee4aed8 | bellard | |
542 | ead9360e | ths | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
543 | f2e9ebef | ths | /* The qemu TLB is flushed when the ASID changes, so no need to
|
544 | 2ee4aed8 | bellard | flush these entries again. */
|
545 | 2ee4aed8 | bellard | if (tlb->G == 0 && tlb->ASID != ASID) { |
546 | 2ee4aed8 | bellard | return;
|
547 | 2ee4aed8 | bellard | } |
548 | 2ee4aed8 | bellard | |
549 | ead9360e | ths | if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
|
550 | 2ee4aed8 | bellard | /* For tlbwr, we can shadow the discarded entry into
|
551 | 2ee4aed8 | bellard | a new (fake) TLB entry, as long as the guest can not
|
552 | 2ee4aed8 | bellard | tell that it's there. */
|
553 | ead9360e | ths | env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb; |
554 | ead9360e | ths | env->tlb->tlb_in_use++; |
555 | 2ee4aed8 | bellard | return;
|
556 | 2ee4aed8 | bellard | } |
557 | 2ee4aed8 | bellard | |
558 | 3b1c8be4 | ths | /* 1k pages are not supported. */
|
559 | f2e9ebef | ths | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
560 | 3b1c8be4 | ths | if (tlb->V0) {
|
561 | f2e9ebef | ths | addr = tlb->VPN & ~mask; |
562 | 540635ba | ths | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
563 | e034e2c3 | ths | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
564 | 100ce988 | ths | addr |= 0x3FFFFF0000000000ULL;
|
565 | 100ce988 | ths | } |
566 | 100ce988 | ths | #endif
|
567 | 3b1c8be4 | ths | end = addr | (mask >> 1);
|
568 | 3b1c8be4 | ths | while (addr < end) {
|
569 | 3b1c8be4 | ths | tlb_flush_page (env, addr); |
570 | 3b1c8be4 | ths | addr += TARGET_PAGE_SIZE; |
571 | 3b1c8be4 | ths | } |
572 | 3b1c8be4 | ths | } |
573 | 3b1c8be4 | ths | if (tlb->V1) {
|
574 | f2e9ebef | ths | addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); |
575 | 540635ba | ths | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
576 | e034e2c3 | ths | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
577 | 100ce988 | ths | addr |= 0x3FFFFF0000000000ULL;
|
578 | 100ce988 | ths | } |
579 | 100ce988 | ths | #endif
|
580 | 3b1c8be4 | ths | end = addr | mask; |
581 | 3b1c8be4 | ths | while (addr < end) {
|
582 | 3b1c8be4 | ths | tlb_flush_page (env, addr); |
583 | 3b1c8be4 | ths | addr += TARGET_PAGE_SIZE; |
584 | 3b1c8be4 | ths | } |
585 | 3b1c8be4 | ths | } |
586 | 2ee4aed8 | bellard | } |