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1 | 2f062c72 | ths | /*
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2 | 2f062c72 | ths | * QEMU SCI/SCIF serial port emulation
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3 | 2f062c72 | ths | *
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4 | 2f062c72 | ths | * Copyright (c) 2007 Magnus Damm
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5 | 2f062c72 | ths | *
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6 | 2f062c72 | ths | * Based on serial.c - QEMU 16450 UART emulation
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7 | 2f062c72 | ths | * Copyright (c) 2003-2004 Fabrice Bellard
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8 | 2f062c72 | ths | *
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9 | 2f062c72 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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10 | 2f062c72 | ths | * of this software and associated documentation files (the "Software"), to deal
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11 | 2f062c72 | ths | * in the Software without restriction, including without limitation the rights
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12 | 2f062c72 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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13 | 2f062c72 | ths | * copies of the Software, and to permit persons to whom the Software is
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14 | 2f062c72 | ths | * furnished to do so, subject to the following conditions:
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15 | 2f062c72 | ths | *
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16 | 2f062c72 | ths | * The above copyright notice and this permission notice shall be included in
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17 | 2f062c72 | ths | * all copies or substantial portions of the Software.
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18 | 2f062c72 | ths | *
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19 | 2f062c72 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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20 | 2f062c72 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 | 2f062c72 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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22 | 2f062c72 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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23 | 2f062c72 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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24 | 2f062c72 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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25 | 2f062c72 | ths | * THE SOFTWARE.
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26 | 2f062c72 | ths | */
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27 | 87ecb68b | pbrook | #include "hw.h" |
28 | 87ecb68b | pbrook | #include "sh.h" |
29 | 87ecb68b | pbrook | #include "qemu-char.h" |
30 | 2f062c72 | ths | #include <assert.h> |
31 | 2f062c72 | ths | |
32 | 2f062c72 | ths | //#define DEBUG_SERIAL
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33 | 2f062c72 | ths | |
34 | 2f062c72 | ths | #define SH_SERIAL_FLAG_TEND (1 << 0) |
35 | 2f062c72 | ths | #define SH_SERIAL_FLAG_TDE (1 << 1) |
36 | 2f062c72 | ths | #define SH_SERIAL_FLAG_RDF (1 << 2) |
37 | 2f062c72 | ths | #define SH_SERIAL_FLAG_BRK (1 << 3) |
38 | 2f062c72 | ths | #define SH_SERIAL_FLAG_DR (1 << 4) |
39 | 2f062c72 | ths | |
40 | 63242a00 | aurel32 | #define SH_RX_FIFO_LENGTH (16) |
41 | 63242a00 | aurel32 | |
42 | 2f062c72 | ths | typedef struct { |
43 | 2f062c72 | ths | uint8_t smr; |
44 | 2f062c72 | ths | uint8_t brr; |
45 | 2f062c72 | ths | uint8_t scr; |
46 | 2f062c72 | ths | uint8_t dr; /* ftdr / tdr */
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47 | 2f062c72 | ths | uint8_t sr; /* fsr / ssr */
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48 | 2f062c72 | ths | uint16_t fcr; |
49 | 2f062c72 | ths | uint8_t sptr; |
50 | 2f062c72 | ths | |
51 | 63242a00 | aurel32 | uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
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52 | 2f062c72 | ths | uint8_t rx_cnt; |
53 | 63242a00 | aurel32 | uint8_t rx_tail; |
54 | 63242a00 | aurel32 | uint8_t rx_head; |
55 | 2f062c72 | ths | |
56 | 2f062c72 | ths | target_phys_addr_t base; |
57 | 2f062c72 | ths | int freq;
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58 | 2f062c72 | ths | int feat;
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59 | 2f062c72 | ths | int flags;
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60 | 63242a00 | aurel32 | int rtrg;
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61 | 2f062c72 | ths | |
62 | 2f062c72 | ths | CharDriverState *chr; |
63 | bf5b7423 | aurel32 | |
64 | bf5b7423 | aurel32 | struct intc_source *eri;
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65 | bf5b7423 | aurel32 | struct intc_source *rxi;
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66 | bf5b7423 | aurel32 | struct intc_source *txi;
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67 | bf5b7423 | aurel32 | struct intc_source *tei;
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68 | bf5b7423 | aurel32 | struct intc_source *bri;
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69 | 2f062c72 | ths | } sh_serial_state; |
70 | 2f062c72 | ths | |
71 | 63242a00 | aurel32 | static void sh_serial_clear_fifo(sh_serial_state * s) |
72 | 63242a00 | aurel32 | { |
73 | 63242a00 | aurel32 | memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
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74 | 63242a00 | aurel32 | s->rx_cnt = 0;
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75 | 63242a00 | aurel32 | s->rx_head = 0;
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76 | 63242a00 | aurel32 | s->rx_tail = 0;
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77 | 63242a00 | aurel32 | } |
78 | 63242a00 | aurel32 | |
79 | 2f062c72 | ths | static void sh_serial_ioport_write(void *opaque, uint32_t offs, uint32_t val) |
80 | 2f062c72 | ths | { |
81 | 2f062c72 | ths | sh_serial_state *s = opaque; |
82 | 2f062c72 | ths | unsigned char ch; |
83 | 2f062c72 | ths | |
84 | 2f062c72 | ths | #ifdef DEBUG_SERIAL
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85 | 2f062c72 | ths | printf("sh_serial: write base=0x%08lx offs=0x%02x val=0x%02x\n",
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86 | 2f062c72 | ths | (unsigned long) s->base, offs, val); |
87 | 2f062c72 | ths | #endif
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88 | 2f062c72 | ths | switch(offs) {
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89 | 2f062c72 | ths | case 0x00: /* SMR */ |
90 | 2f062c72 | ths | s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff); |
91 | 2f062c72 | ths | return;
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92 | 2f062c72 | ths | case 0x04: /* BRR */ |
93 | 2f062c72 | ths | s->brr = val; |
94 | 2f062c72 | ths | return;
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95 | 2f062c72 | ths | case 0x08: /* SCR */ |
96 | 63242a00 | aurel32 | /* TODO : For SH7751, SCIF mask should be 0xfb. */
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97 | bf5b7423 | aurel32 | s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff); |
98 | 2f062c72 | ths | if (!(val & (1 << 5))) |
99 | 2f062c72 | ths | s->flags |= SH_SERIAL_FLAG_TEND; |
100 | bf5b7423 | aurel32 | if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
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101 | bf5b7423 | aurel32 | if ((val & (1 << 7)) && !(s->txi->asserted)) |
102 | bf5b7423 | aurel32 | sh_intc_toggle_source(s->txi, 0, 1); |
103 | bf5b7423 | aurel32 | else if (!(val & (1 << 7)) && s->txi->asserted) |
104 | bf5b7423 | aurel32 | sh_intc_toggle_source(s->txi, 0, -1); |
105 | bf5b7423 | aurel32 | } |
106 | 63242a00 | aurel32 | if (!(val & (1 << 6)) && s->rxi->asserted) { |
107 | 63242a00 | aurel32 | sh_intc_toggle_source(s->rxi, 0, -1); |
108 | 63242a00 | aurel32 | } |
109 | 2f062c72 | ths | return;
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110 | 2f062c72 | ths | case 0x0c: /* FTDR / TDR */ |
111 | 2f062c72 | ths | if (s->chr) {
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112 | 2f062c72 | ths | ch = val; |
113 | 2f062c72 | ths | qemu_chr_write(s->chr, &ch, 1);
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114 | 2f062c72 | ths | } |
115 | 2f062c72 | ths | s->dr = val; |
116 | 2f062c72 | ths | s->flags &= ~SH_SERIAL_FLAG_TDE; |
117 | 2f062c72 | ths | return;
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118 | 2f062c72 | ths | #if 0
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119 | 2f062c72 | ths | case 0x14: /* FRDR / RDR */
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120 | 2f062c72 | ths | ret = 0;
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121 | 2f062c72 | ths | break;
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122 | 2f062c72 | ths | #endif
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123 | 2f062c72 | ths | } |
124 | 2f062c72 | ths | if (s->feat & SH_SERIAL_FEAT_SCIF) {
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125 | 2f062c72 | ths | switch(offs) {
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126 | 2f062c72 | ths | case 0x10: /* FSR */ |
127 | 2f062c72 | ths | if (!(val & (1 << 6))) |
128 | 2f062c72 | ths | s->flags &= ~SH_SERIAL_FLAG_TEND; |
129 | 2f062c72 | ths | if (!(val & (1 << 5))) |
130 | 2f062c72 | ths | s->flags &= ~SH_SERIAL_FLAG_TDE; |
131 | 2f062c72 | ths | if (!(val & (1 << 4))) |
132 | 2f062c72 | ths | s->flags &= ~SH_SERIAL_FLAG_BRK; |
133 | 2f062c72 | ths | if (!(val & (1 << 1))) |
134 | 2f062c72 | ths | s->flags &= ~SH_SERIAL_FLAG_RDF; |
135 | 2f062c72 | ths | if (!(val & (1 << 0))) |
136 | 2f062c72 | ths | s->flags &= ~SH_SERIAL_FLAG_DR; |
137 | 63242a00 | aurel32 | |
138 | 63242a00 | aurel32 | if (!(val & (1 << 1)) || !(val & (1 << 0))) { |
139 | 63242a00 | aurel32 | if (s->rxi && s->rxi->asserted) {
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140 | 63242a00 | aurel32 | sh_intc_toggle_source(s->rxi, 0, -1); |
141 | 63242a00 | aurel32 | } |
142 | 63242a00 | aurel32 | } |
143 | 2f062c72 | ths | return;
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144 | 2f062c72 | ths | case 0x18: /* FCR */ |
145 | 2f062c72 | ths | s->fcr = val; |
146 | 63242a00 | aurel32 | switch ((val >> 6) & 3) { |
147 | 63242a00 | aurel32 | case 0: |
148 | 63242a00 | aurel32 | s->rtrg = 1;
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149 | 63242a00 | aurel32 | break;
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150 | 63242a00 | aurel32 | case 1: |
151 | 63242a00 | aurel32 | s->rtrg = 4;
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152 | 63242a00 | aurel32 | break;
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153 | 63242a00 | aurel32 | case 2: |
154 | 63242a00 | aurel32 | s->rtrg = 8;
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155 | 63242a00 | aurel32 | break;
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156 | 63242a00 | aurel32 | case 3: |
157 | 63242a00 | aurel32 | s->rtrg = 14;
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158 | 63242a00 | aurel32 | break;
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159 | 63242a00 | aurel32 | } |
160 | 63242a00 | aurel32 | if (val & (1 << 1)) { |
161 | 63242a00 | aurel32 | sh_serial_clear_fifo(s); |
162 | 63242a00 | aurel32 | s->sr &= ~(1 << 1); |
163 | 63242a00 | aurel32 | } |
164 | 63242a00 | aurel32 | |
165 | 2f062c72 | ths | return;
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166 | 2f062c72 | ths | case 0x20: /* SPTR */ |
167 | 63242a00 | aurel32 | s->sptr = val & 0xf3;
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168 | 2f062c72 | ths | return;
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169 | 2f062c72 | ths | case 0x24: /* LSR */ |
170 | 2f062c72 | ths | return;
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171 | 2f062c72 | ths | } |
172 | 2f062c72 | ths | } |
173 | 2f062c72 | ths | else {
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174 | 2f062c72 | ths | #if 0
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175 | 2f062c72 | ths | switch(offs) {
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176 | 2f062c72 | ths | case 0x0c:
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177 | 2f062c72 | ths | ret = s->dr;
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178 | 2f062c72 | ths | break;
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179 | 2f062c72 | ths | case 0x10:
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180 | 2f062c72 | ths | ret = 0;
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181 | 2f062c72 | ths | break;
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182 | 2f062c72 | ths | case 0x1c:
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183 | 2f062c72 | ths | ret = s->sptr;
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184 | 2f062c72 | ths | break;
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185 | 2f062c72 | ths | }
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186 | 2f062c72 | ths | #endif
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187 | 2f062c72 | ths | } |
188 | 2f062c72 | ths | |
189 | 2f062c72 | ths | fprintf(stderr, "sh_serial: unsupported write to 0x%02x\n", offs);
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190 | 2f062c72 | ths | assert(0);
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191 | 2f062c72 | ths | } |
192 | 2f062c72 | ths | |
193 | 2f062c72 | ths | static uint32_t sh_serial_ioport_read(void *opaque, uint32_t offs) |
194 | 2f062c72 | ths | { |
195 | 2f062c72 | ths | sh_serial_state *s = opaque; |
196 | 2f062c72 | ths | uint32_t ret = ~0;
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197 | 2f062c72 | ths | |
198 | 2f062c72 | ths | #if 0
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199 | 2f062c72 | ths | switch(offs) {
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200 | 2f062c72 | ths | case 0x00:
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201 | 2f062c72 | ths | ret = s->smr;
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202 | 2f062c72 | ths | break;
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203 | 2f062c72 | ths | case 0x04:
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204 | 2f062c72 | ths | ret = s->brr;
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205 | 2f062c72 | ths | break;
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206 | 2f062c72 | ths | case 0x08:
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207 | 2f062c72 | ths | ret = s->scr;
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208 | 2f062c72 | ths | break;
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209 | 2f062c72 | ths | case 0x14:
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210 | 2f062c72 | ths | ret = 0;
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211 | 2f062c72 | ths | break;
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212 | 2f062c72 | ths | }
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213 | 2f062c72 | ths | #endif
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214 | 2f062c72 | ths | if (s->feat & SH_SERIAL_FEAT_SCIF) {
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215 | 2f062c72 | ths | switch(offs) {
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216 | bf5b7423 | aurel32 | case 0x00: /* SMR */ |
217 | bf5b7423 | aurel32 | ret = s->smr; |
218 | bf5b7423 | aurel32 | break;
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219 | bf5b7423 | aurel32 | case 0x08: /* SCR */ |
220 | bf5b7423 | aurel32 | ret = s->scr; |
221 | bf5b7423 | aurel32 | break;
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222 | 2f062c72 | ths | case 0x10: /* FSR */ |
223 | 2f062c72 | ths | ret = 0;
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224 | 2f062c72 | ths | if (s->flags & SH_SERIAL_FLAG_TEND)
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225 | 2f062c72 | ths | ret |= (1 << 6); |
226 | 2f062c72 | ths | if (s->flags & SH_SERIAL_FLAG_TDE)
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227 | 2f062c72 | ths | ret |= (1 << 5); |
228 | 2f062c72 | ths | if (s->flags & SH_SERIAL_FLAG_BRK)
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229 | 2f062c72 | ths | ret |= (1 << 4); |
230 | 2f062c72 | ths | if (s->flags & SH_SERIAL_FLAG_RDF)
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231 | 2f062c72 | ths | ret |= (1 << 1); |
232 | 2f062c72 | ths | if (s->flags & SH_SERIAL_FLAG_DR)
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233 | 2f062c72 | ths | ret |= (1 << 0); |
234 | 2f062c72 | ths | |
235 | 63242a00 | aurel32 | if (s->scr & (1 << 5)) |
236 | 2f062c72 | ths | s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND; |
237 | 2f062c72 | ths | |
238 | 2f062c72 | ths | break;
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239 | 63242a00 | aurel32 | case 0x14: |
240 | 63242a00 | aurel32 | if (s->rx_cnt > 0) { |
241 | 63242a00 | aurel32 | ret = s->rx_fifo[s->rx_tail++]; |
242 | 63242a00 | aurel32 | s->rx_cnt--; |
243 | 63242a00 | aurel32 | if (s->rx_tail == SH_RX_FIFO_LENGTH)
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244 | 63242a00 | aurel32 | s->rx_tail = 0;
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245 | 63242a00 | aurel32 | if (s->rx_cnt < s->rtrg)
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246 | 63242a00 | aurel32 | s->flags &= ~SH_SERIAL_FLAG_RDF; |
247 | 63242a00 | aurel32 | } |
248 | 63242a00 | aurel32 | break;
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249 | 2f062c72 | ths | #if 0
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250 | 2f062c72 | ths | case 0x18:
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251 | 2f062c72 | ths | ret = s->fcr;
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252 | 2f062c72 | ths | break;
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253 | 2f062c72 | ths | #endif
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254 | 2f062c72 | ths | case 0x1c: |
255 | 2f062c72 | ths | ret = s->rx_cnt; |
256 | 2f062c72 | ths | break;
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257 | 2f062c72 | ths | case 0x20: |
258 | 2f062c72 | ths | ret = s->sptr; |
259 | 2f062c72 | ths | break;
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260 | 2f062c72 | ths | case 0x24: |
261 | 2f062c72 | ths | ret = 0;
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262 | 2f062c72 | ths | break;
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263 | 2f062c72 | ths | } |
264 | 2f062c72 | ths | } |
265 | 2f062c72 | ths | else {
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266 | 2f062c72 | ths | #if 0
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267 | 2f062c72 | ths | switch(offs) {
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268 | 2f062c72 | ths | case 0x0c:
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269 | 2f062c72 | ths | ret = s->dr;
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270 | 2f062c72 | ths | break;
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271 | 2f062c72 | ths | case 0x10:
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272 | 2f062c72 | ths | ret = 0;
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273 | 2f062c72 | ths | break;
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274 | 63242a00 | aurel32 | case 0x14:
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275 | 63242a00 | aurel32 | ret = s->rx_fifo[0];
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276 | 63242a00 | aurel32 | break;
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277 | 2f062c72 | ths | case 0x1c:
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278 | 2f062c72 | ths | ret = s->sptr;
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279 | 2f062c72 | ths | break;
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280 | 2f062c72 | ths | }
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281 | 2f062c72 | ths | #endif
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282 | 2f062c72 | ths | } |
283 | 2f062c72 | ths | #ifdef DEBUG_SERIAL
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284 | 2f062c72 | ths | printf("sh_serial: read base=0x%08lx offs=0x%02x val=0x%x\n",
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285 | 2f062c72 | ths | (unsigned long) s->base, offs, ret); |
286 | 2f062c72 | ths | #endif
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287 | 2f062c72 | ths | |
288 | 2f062c72 | ths | if (ret & ~((1 << 16) - 1)) { |
289 | 2f062c72 | ths | fprintf(stderr, "sh_serial: unsupported read from 0x%02x\n", offs);
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290 | 2f062c72 | ths | assert(0);
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291 | 2f062c72 | ths | } |
292 | 2f062c72 | ths | |
293 | 2f062c72 | ths | return ret;
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294 | 2f062c72 | ths | } |
295 | 2f062c72 | ths | |
296 | 2f062c72 | ths | static int sh_serial_can_receive(sh_serial_state *s) |
297 | 2f062c72 | ths | { |
298 | 63242a00 | aurel32 | return s->scr & (1 << 4); |
299 | 2f062c72 | ths | } |
300 | 2f062c72 | ths | |
301 | 2f062c72 | ths | static void sh_serial_receive_byte(sh_serial_state *s, int ch) |
302 | 2f062c72 | ths | { |
303 | 63242a00 | aurel32 | if (s->feat & SH_SERIAL_FEAT_SCIF) {
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304 | 63242a00 | aurel32 | if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
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305 | 63242a00 | aurel32 | s->rx_fifo[s->rx_head++] = ch; |
306 | 63242a00 | aurel32 | if (s->rx_head == SH_RX_FIFO_LENGTH)
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307 | 63242a00 | aurel32 | s->rx_head = 0;
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308 | 63242a00 | aurel32 | s->rx_cnt++; |
309 | 63242a00 | aurel32 | if (s->rx_cnt >= s->rtrg) {
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310 | 63242a00 | aurel32 | s->flags |= SH_SERIAL_FLAG_RDF; |
311 | 63242a00 | aurel32 | if (s->scr & (1 << 6) && s->rxi) { |
312 | 63242a00 | aurel32 | sh_intc_toggle_source(s->rxi, 0, 1); |
313 | 63242a00 | aurel32 | } |
314 | 63242a00 | aurel32 | } |
315 | 63242a00 | aurel32 | } |
316 | 63242a00 | aurel32 | } else {
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317 | 63242a00 | aurel32 | s->rx_fifo[0] = ch;
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318 | 63242a00 | aurel32 | } |
319 | 2f062c72 | ths | } |
320 | 2f062c72 | ths | |
321 | 2f062c72 | ths | static void sh_serial_receive_break(sh_serial_state *s) |
322 | 2f062c72 | ths | { |
323 | 63242a00 | aurel32 | if (s->feat & SH_SERIAL_FEAT_SCIF)
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324 | 63242a00 | aurel32 | s->sr |= (1 << 4); |
325 | 2f062c72 | ths | } |
326 | 2f062c72 | ths | |
327 | 2f062c72 | ths | static int sh_serial_can_receive1(void *opaque) |
328 | 2f062c72 | ths | { |
329 | 2f062c72 | ths | sh_serial_state *s = opaque; |
330 | 2f062c72 | ths | return sh_serial_can_receive(s);
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331 | 2f062c72 | ths | } |
332 | 2f062c72 | ths | |
333 | 2f062c72 | ths | static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size) |
334 | 2f062c72 | ths | { |
335 | 2f062c72 | ths | sh_serial_state *s = opaque; |
336 | 2f062c72 | ths | sh_serial_receive_byte(s, buf[0]);
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337 | 2f062c72 | ths | } |
338 | 2f062c72 | ths | |
339 | 2f062c72 | ths | static void sh_serial_event(void *opaque, int event) |
340 | 2f062c72 | ths | { |
341 | 2f062c72 | ths | sh_serial_state *s = opaque; |
342 | 2f062c72 | ths | if (event == CHR_EVENT_BREAK)
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343 | 2f062c72 | ths | sh_serial_receive_break(s); |
344 | 2f062c72 | ths | } |
345 | 2f062c72 | ths | |
346 | 9596ebb7 | pbrook | static uint32_t sh_serial_read (void *opaque, target_phys_addr_t addr) |
347 | 2f062c72 | ths | { |
348 | 2f062c72 | ths | sh_serial_state *s = opaque; |
349 | 2f062c72 | ths | return sh_serial_ioport_read(s, addr - s->base);
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350 | 2f062c72 | ths | } |
351 | 2f062c72 | ths | |
352 | 9596ebb7 | pbrook | static void sh_serial_write (void *opaque, |
353 | 9596ebb7 | pbrook | target_phys_addr_t addr, uint32_t value) |
354 | 2f062c72 | ths | { |
355 | 2f062c72 | ths | sh_serial_state *s = opaque; |
356 | 2f062c72 | ths | sh_serial_ioport_write(s, addr - s->base, value); |
357 | 2f062c72 | ths | } |
358 | 2f062c72 | ths | |
359 | 2f062c72 | ths | static CPUReadMemoryFunc *sh_serial_readfn[] = {
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360 | 2f062c72 | ths | &sh_serial_read, |
361 | 2f062c72 | ths | &sh_serial_read, |
362 | 2f062c72 | ths | &sh_serial_read, |
363 | 2f062c72 | ths | }; |
364 | 2f062c72 | ths | |
365 | 2f062c72 | ths | static CPUWriteMemoryFunc *sh_serial_writefn[] = {
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366 | 2f062c72 | ths | &sh_serial_write, |
367 | 2f062c72 | ths | &sh_serial_write, |
368 | 2f062c72 | ths | &sh_serial_write, |
369 | 2f062c72 | ths | }; |
370 | 2f062c72 | ths | |
371 | 2f062c72 | ths | void sh_serial_init (target_phys_addr_t base, int feat, |
372 | bf5b7423 | aurel32 | uint32_t freq, CharDriverState *chr, |
373 | bf5b7423 | aurel32 | struct intc_source *eri_source,
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374 | bf5b7423 | aurel32 | struct intc_source *rxi_source,
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375 | bf5b7423 | aurel32 | struct intc_source *txi_source,
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376 | bf5b7423 | aurel32 | struct intc_source *tei_source,
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377 | bf5b7423 | aurel32 | struct intc_source *bri_source)
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378 | 2f062c72 | ths | { |
379 | 2f062c72 | ths | sh_serial_state *s; |
380 | 2f062c72 | ths | int s_io_memory;
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381 | 2f062c72 | ths | |
382 | 2f062c72 | ths | s = qemu_mallocz(sizeof(sh_serial_state));
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383 | 2f062c72 | ths | if (!s)
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384 | 2f062c72 | ths | return;
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385 | 2f062c72 | ths | |
386 | 2f062c72 | ths | s->base = base; |
387 | 2f062c72 | ths | s->feat = feat; |
388 | 2f062c72 | ths | s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE; |
389 | 63242a00 | aurel32 | s->rtrg = 1;
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390 | 2f062c72 | ths | |
391 | 2f062c72 | ths | s->smr = 0;
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392 | 2f062c72 | ths | s->brr = 0xff;
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393 | b7d35e65 | balrog | s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */ |
394 | 2f062c72 | ths | s->sptr = 0;
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395 | 2f062c72 | ths | |
396 | 2f062c72 | ths | if (feat & SH_SERIAL_FEAT_SCIF) {
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397 | 2f062c72 | ths | s->fcr = 0;
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398 | 2f062c72 | ths | } |
399 | 2f062c72 | ths | else {
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400 | 2f062c72 | ths | s->dr = 0xff;
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401 | 2f062c72 | ths | } |
402 | 2f062c72 | ths | |
403 | 63242a00 | aurel32 | sh_serial_clear_fifo(s); |
404 | 2f062c72 | ths | |
405 | 2f062c72 | ths | s_io_memory = cpu_register_io_memory(0, sh_serial_readfn,
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406 | 2f062c72 | ths | sh_serial_writefn, s); |
407 | 2f062c72 | ths | cpu_register_physical_memory(base, 0x28, s_io_memory);
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408 | 2f062c72 | ths | |
409 | 2f062c72 | ths | s->chr = chr; |
410 | 2f062c72 | ths | |
411 | 2f062c72 | ths | if (chr)
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412 | 2f062c72 | ths | qemu_chr_add_handlers(chr, sh_serial_can_receive1, sh_serial_receive1, |
413 | 2f062c72 | ths | sh_serial_event, s); |
414 | bf5b7423 | aurel32 | |
415 | bf5b7423 | aurel32 | s->eri = eri_source; |
416 | bf5b7423 | aurel32 | s->rxi = rxi_source; |
417 | bf5b7423 | aurel32 | s->txi = txi_source; |
418 | bf5b7423 | aurel32 | s->tei = tei_source; |
419 | bf5b7423 | aurel32 | s->bri = bri_source; |
420 | 2f062c72 | ths | } |