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Revision 6327c221

ID6327c221fff955ee979559ec85c148963e06d78f

Added by Peter Crosthwaite almost 11 years ago

intc/xilinx_intc: Don't clear level sens. IRQs without ACK

For level sensitive interrupts, ISR bits are cleared when the input pin
is lowered. This is incorrect. Only software can clear ISR bits (via
IAR or direct write to ISR with !MER).

Signed-off-by: Peter Crosthwaite <>
Signed-off-by: Edgar E. Iglesias <>

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