Revision 633aa0ac
| b/hw/acpi_piix4.c | ||
|---|---|---|
| 107 | 107 |
(ACPI_BITMASK_RT_CLOCK_ENABLE | |
| 108 | 108 |
ACPI_BITMASK_POWER_BUTTON_ENABLE | |
| 109 | 109 |
ACPI_BITMASK_GLOBAL_LOCK_ENABLE | |
| 110 |
ACPI_BITMASK_TIMER_ENABLE)) != 0); |
|
| 110 |
ACPI_BITMASK_TIMER_ENABLE)) != 0) || |
|
| 111 |
(((s->gpe.sts & s->gpe.en) & PIIX4_PCI_HOTPLUG_STATUS) != 0); |
|
| 112 |
|
|
| 111 | 113 |
qemu_set_irq(s->irq, sci_level); |
| 112 | 114 |
/* schedule a timer interruption if needed */ |
| 113 | 115 |
if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) && |
| ... | ... | |
| 462 | 464 |
static uint32_t gpe_readb(void *opaque, uint32_t addr) |
| 463 | 465 |
{
|
| 464 | 466 |
uint32_t val = 0; |
| 465 |
struct gpe_regs *g = opaque; |
|
| 467 |
PIIX4PMState *s = opaque; |
|
| 468 |
struct gpe_regs *g = &s->gpe; |
|
| 469 |
|
|
| 466 | 470 |
switch (addr) {
|
| 467 | 471 |
case GPE_BASE: |
| 468 | 472 |
case GPE_BASE + 1: |
| ... | ... | |
| 502 | 506 |
|
| 503 | 507 |
static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) |
| 504 | 508 |
{
|
| 505 |
struct gpe_regs *g = opaque; |
|
| 509 |
PIIX4PMState *s = opaque; |
|
| 510 |
struct gpe_regs *g = &s->gpe; |
|
| 511 |
|
|
| 506 | 512 |
switch (addr) {
|
| 507 | 513 |
case GPE_BASE: |
| 508 | 514 |
case GPE_BASE + 1: |
| ... | ... | |
| 514 | 520 |
break; |
| 515 | 521 |
default: |
| 516 | 522 |
break; |
| 517 |
} |
|
| 523 |
} |
|
| 524 |
|
|
| 525 |
pm_update_sci(s); |
|
| 518 | 526 |
|
| 519 | 527 |
PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
|
| 520 | 528 |
} |
| ... | ... | |
| 581 | 589 |
|
| 582 | 590 |
static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) |
| 583 | 591 |
{
|
| 584 |
struct gpe_regs *gpe = &s->gpe; |
|
| 585 | 592 |
struct pci_status *pci0_status = &s->pci0_status; |
| 586 | 593 |
|
| 587 |
register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, gpe);
|
|
| 588 |
register_ioport_read(GPE_BASE, 4, 1, gpe_readb, gpe);
|
|
| 594 |
register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, s);
|
|
| 595 |
register_ioport_read(GPE_BASE, 4, 1, gpe_readb, s);
|
|
| 589 | 596 |
|
| 590 | 597 |
register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status); |
| 591 | 598 |
register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, pci0_status); |
| ... | ... | |
| 621 | 628 |
} else {
|
| 622 | 629 |
disable_device(s, slot); |
| 623 | 630 |
} |
| 624 |
if (s->gpe.en & 2) {
|
|
| 625 |
qemu_set_irq(s->irq, 1); |
|
| 626 |
qemu_set_irq(s->irq, 0); |
|
| 627 |
} |
|
| 631 |
|
|
| 632 |
pm_update_sci(s); |
|
| 633 |
|
|
| 628 | 634 |
return 0; |
| 629 | 635 |
} |
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