Revision 636aa200
b/hw/ppc.c | ||
---|---|---|
393 | 393 |
void *opaque; |
394 | 394 |
}; |
395 | 395 |
|
396 |
static always_inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env, uint64_t vmclk,
|
|
397 |
int64_t tb_offset)
|
|
396 |
static inline uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk,
|
|
397 |
int64_t tb_offset) |
|
398 | 398 |
{ |
399 | 399 |
/* TB time in tb periods */ |
400 | 400 |
return muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec) + tb_offset; |
... | ... | |
411 | 411 |
return tb & 0xFFFFFFFF; |
412 | 412 |
} |
413 | 413 |
|
414 |
static always_inline uint32_t _cpu_ppc_load_tbu (CPUState *env)
|
|
414 |
static inline uint32_t _cpu_ppc_load_tbu(CPUState *env)
|
|
415 | 415 |
{ |
416 | 416 |
ppc_tb_t *tb_env = env->tb_env; |
417 | 417 |
uint64_t tb; |
... | ... | |
427 | 427 |
return _cpu_ppc_load_tbu(env); |
428 | 428 |
} |
429 | 429 |
|
430 |
static always_inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t vmclk, |
|
431 |
int64_t *tb_offsetp, |
|
432 |
uint64_t value) |
|
430 |
static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, |
|
431 |
int64_t *tb_offsetp, uint64_t value) |
|
433 | 432 |
{ |
434 | 433 |
*tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec); |
435 | 434 |
LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", |
... | ... | |
447 | 446 |
&tb_env->tb_offset, tb | (uint64_t)value); |
448 | 447 |
} |
449 | 448 |
|
450 |
static always_inline void _cpu_ppc_store_tbu (CPUState *env, uint32_t value)
|
|
449 |
static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value)
|
|
451 | 450 |
{ |
452 | 451 |
ppc_tb_t *tb_env = env->tb_env; |
453 | 452 |
uint64_t tb; |
... | ... | |
550 | 549 |
} |
551 | 550 |
} |
552 | 551 |
|
553 |
static always_inline uint32_t _cpu_ppc_load_decr (CPUState *env, |
|
554 |
uint64_t next) |
|
552 |
static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next) |
|
555 | 553 |
{ |
556 | 554 |
ppc_tb_t *tb_env = env->tb_env; |
557 | 555 |
uint32_t decr; |
... | ... | |
594 | 592 |
/* When decrementer expires, |
595 | 593 |
* all we need to do is generate or queue a CPU exception |
596 | 594 |
*/ |
597 |
static always_inline void cpu_ppc_decr_excp (CPUState *env)
|
|
595 |
static inline void cpu_ppc_decr_excp(CPUState *env)
|
|
598 | 596 |
{ |
599 | 597 |
/* Raise it */ |
600 | 598 |
LOG_TB("raise decrementer exception\n"); |
601 | 599 |
ppc_set_irq(env, PPC_INTERRUPT_DECR, 1); |
602 | 600 |
} |
603 | 601 |
|
604 |
static always_inline void cpu_ppc_hdecr_excp (CPUState *env)
|
|
602 |
static inline void cpu_ppc_hdecr_excp(CPUState *env)
|
|
605 | 603 |
{ |
606 | 604 |
/* Raise it */ |
607 | 605 |
LOG_TB("raise decrementer exception\n"); |
... | ... | |
635 | 633 |
(*raise_excp)(env); |
636 | 634 |
} |
637 | 635 |
|
638 |
static always_inline void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,
|
|
639 |
uint32_t value, int is_excp)
|
|
636 |
static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr,
|
|
637 |
uint32_t value, int is_excp) |
|
640 | 638 |
{ |
641 | 639 |
ppc_tb_t *tb_env = env->tb_env; |
642 | 640 |
|
... | ... | |
654 | 652 |
_cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1); |
655 | 653 |
} |
656 | 654 |
|
657 |
static always_inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr,
|
|
658 |
uint32_t value, int is_excp)
|
|
655 |
static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr,
|
|
656 |
uint32_t value, int is_excp) |
|
659 | 657 |
{ |
660 | 658 |
ppc_tb_t *tb_env = env->tb_env; |
661 | 659 |
|
b/hw/ppc4xx_devs.c | ||
---|---|---|
377 | 377 |
return bcr; |
378 | 378 |
} |
379 | 379 |
|
380 |
static always_inline target_phys_addr_t sdram_base (uint32_t bcr)
|
|
380 |
static inline target_phys_addr_t sdram_base(uint32_t bcr)
|
|
381 | 381 |
{ |
382 | 382 |
return bcr & 0xFF800000; |
383 | 383 |
} |
b/hw/ppc_prep.c | ||
---|---|---|
115 | 115 |
// printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value); |
116 | 116 |
} |
117 | 117 |
|
118 |
static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
|
|
118 |
static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
|
|
119 | 119 |
{ |
120 | 120 |
uint32_t retval = 0; |
121 | 121 |
|
... | ... | |
426 | 426 |
return retval; |
427 | 427 |
} |
428 | 428 |
|
429 |
static always_inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl, |
|
430 |
target_phys_addr_t |
|
431 |
addr) |
|
429 |
static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl, |
|
430 |
target_phys_addr_t addr) |
|
432 | 431 |
{ |
433 | 432 |
if (sysctrl->contiguous_map == 0) { |
434 | 433 |
/* 64 KB contiguous space for IOs */ |
b/osdep.h | ||
---|---|---|
48 | 48 |
#endif |
49 | 49 |
|
50 | 50 |
#ifndef always_inline |
51 |
#if (__GNUC__ < 3) || defined(__APPLE__) |
|
52 |
#define always_inline inline |
|
53 |
#else |
|
54 |
#define always_inline __attribute__ (( always_inline )) __inline__ |
|
51 |
#if !((__GNUC__ < 3) || defined(__APPLE__)) |
|
55 | 52 |
#ifdef __OPTIMIZE__ |
56 |
#define inline always_inline
|
|
53 |
#define inline __attribute__ (( always_inline )) __inline__
|
|
57 | 54 |
#endif |
58 | 55 |
#endif |
59 | 56 |
#else |
b/target-alpha/exec.h | ||
---|---|---|
39 | 39 |
#include "softmmu_exec.h" |
40 | 40 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
41 | 41 |
|
42 |
static always_inline void env_to_regs(void)
|
|
42 |
static inline void env_to_regs(void) |
|
43 | 43 |
{ |
44 | 44 |
} |
45 | 45 |
|
46 |
static always_inline void regs_to_env(void)
|
|
46 |
static inline void regs_to_env(void) |
|
47 | 47 |
{ |
48 | 48 |
} |
49 | 49 |
|
50 |
static always_inline int cpu_has_work(CPUState *env)
|
|
50 |
static inline int cpu_has_work(CPUState *env) |
|
51 | 51 |
{ |
52 | 52 |
return (env->interrupt_request & CPU_INTERRUPT_HARD); |
53 | 53 |
} |
54 | 54 |
|
55 |
static always_inline int cpu_halted(CPUState *env) { |
|
55 |
static inline int cpu_halted(CPUState *env) |
|
56 |
{ |
|
56 | 57 |
if (!env->halted) |
57 | 58 |
return 0; |
58 | 59 |
if (cpu_has_work(env)) { |
b/target-alpha/op_helper.c | ||
---|---|---|
200 | 200 |
return ctz64(arg); |
201 | 201 |
} |
202 | 202 |
|
203 |
static always_inline uint64_t byte_zap (uint64_t op, uint8_t mskb)
|
|
203 |
static inline uint64_t byte_zap(uint64_t op, uint8_t mskb)
|
|
204 | 204 |
{ |
205 | 205 |
uint64_t mask; |
206 | 206 |
|
... | ... | |
322 | 322 |
/* Floating point helpers */ |
323 | 323 |
|
324 | 324 |
/* F floating (VAX) */ |
325 |
static always_inline uint64_t float32_to_f (float32 fa)
|
|
325 |
static inline uint64_t float32_to_f(float32 fa)
|
|
326 | 326 |
{ |
327 | 327 |
uint64_t r, exp, mant, sig; |
328 | 328 |
CPU_FloatU a; |
... | ... | |
355 | 355 |
return r; |
356 | 356 |
} |
357 | 357 |
|
358 |
static always_inline float32 f_to_float32 (uint64_t a)
|
|
358 |
static inline float32 f_to_float32(uint64_t a)
|
|
359 | 359 |
{ |
360 | 360 |
uint32_t exp, mant_sig; |
361 | 361 |
CPU_FloatU r; |
... | ... | |
449 | 449 |
|
450 | 450 |
|
451 | 451 |
/* G floating (VAX) */ |
452 |
static always_inline uint64_t float64_to_g (float64 fa)
|
|
452 |
static inline uint64_t float64_to_g(float64 fa)
|
|
453 | 453 |
{ |
454 | 454 |
uint64_t r, exp, mant, sig; |
455 | 455 |
CPU_DoubleU a; |
... | ... | |
482 | 482 |
return r; |
483 | 483 |
} |
484 | 484 |
|
485 |
static always_inline float64 g_to_float64 (uint64_t a)
|
|
485 |
static inline float64 g_to_float64(uint64_t a)
|
|
486 | 486 |
{ |
487 | 487 |
uint64_t exp, mant_sig; |
488 | 488 |
CPU_DoubleU r; |
... | ... | |
576 | 576 |
|
577 | 577 |
|
578 | 578 |
/* S floating (single) */ |
579 |
static always_inline uint64_t float32_to_s (float32 fa)
|
|
579 |
static inline uint64_t float32_to_s(float32 fa)
|
|
580 | 580 |
{ |
581 | 581 |
CPU_FloatU a; |
582 | 582 |
uint64_t r; |
... | ... | |
589 | 589 |
return r; |
590 | 590 |
} |
591 | 591 |
|
592 |
static always_inline float32 s_to_float32 (uint64_t a)
|
|
592 |
static inline float32 s_to_float32(uint64_t a)
|
|
593 | 593 |
{ |
594 | 594 |
CPU_FloatU r; |
595 | 595 |
r.l = ((a >> 32) & 0xc0000000) | ((a >> 29) & 0x3fffffff); |
... | ... | |
660 | 660 |
|
661 | 661 |
|
662 | 662 |
/* T floating (double) */ |
663 |
static always_inline float64 t_to_float64 (uint64_t a)
|
|
663 |
static inline float64 t_to_float64(uint64_t a)
|
|
664 | 664 |
{ |
665 | 665 |
/* Memory format is the same as float64 */ |
666 | 666 |
CPU_DoubleU r; |
... | ... | |
668 | 668 |
return r.d; |
669 | 669 |
} |
670 | 670 |
|
671 |
static always_inline uint64_t float64_to_t (float64 fa)
|
|
671 |
static inline uint64_t float64_to_t(float64 fa)
|
|
672 | 672 |
{ |
673 | 673 |
/* Memory format is the same as float64 */ |
674 | 674 |
CPU_DoubleU r; |
... | ... | |
939 | 939 |
return (int64_t)((int32_t)((a >> 32) | ((a >> 29) & 0x3FFFFFFF))); |
940 | 940 |
} |
941 | 941 |
|
942 |
static always_inline uint64_t __helper_cvtql (uint64_t a, int s, int v)
|
|
942 |
static inline uint64_t __helper_cvtql(uint64_t a, int s, int v)
|
|
943 | 943 |
{ |
944 | 944 |
uint64_t r; |
945 | 945 |
|
b/target-alpha/translate.c | ||
---|---|---|
103 | 103 |
done_init = 1; |
104 | 104 |
} |
105 | 105 |
|
106 |
static always_inline void gen_excp (DisasContext *ctx, |
|
107 |
int exception, int error_code) |
|
106 |
static inline void gen_excp(DisasContext *ctx, int exception, int error_code) |
|
108 | 107 |
{ |
109 | 108 |
TCGv_i32 tmp1, tmp2; |
110 | 109 |
|
... | ... | |
116 | 115 |
tcg_temp_free_i32(tmp1); |
117 | 116 |
} |
118 | 117 |
|
119 |
static always_inline void gen_invalid (DisasContext *ctx)
|
|
118 |
static inline void gen_invalid(DisasContext *ctx)
|
|
120 | 119 |
{ |
121 | 120 |
gen_excp(ctx, EXCP_OPCDEC, 0); |
122 | 121 |
} |
123 | 122 |
|
124 |
static always_inline void gen_qemu_ldf (TCGv t0, TCGv t1, int flags)
|
|
123 |
static inline void gen_qemu_ldf(TCGv t0, TCGv t1, int flags)
|
|
125 | 124 |
{ |
126 | 125 |
TCGv tmp = tcg_temp_new(); |
127 | 126 |
TCGv_i32 tmp32 = tcg_temp_new_i32(); |
... | ... | |
132 | 131 |
tcg_temp_free(tmp); |
133 | 132 |
} |
134 | 133 |
|
135 |
static always_inline void gen_qemu_ldg (TCGv t0, TCGv t1, int flags)
|
|
134 |
static inline void gen_qemu_ldg(TCGv t0, TCGv t1, int flags)
|
|
136 | 135 |
{ |
137 | 136 |
TCGv tmp = tcg_temp_new(); |
138 | 137 |
tcg_gen_qemu_ld64(tmp, t1, flags); |
... | ... | |
140 | 139 |
tcg_temp_free(tmp); |
141 | 140 |
} |
142 | 141 |
|
143 |
static always_inline void gen_qemu_lds (TCGv t0, TCGv t1, int flags)
|
|
142 |
static inline void gen_qemu_lds(TCGv t0, TCGv t1, int flags)
|
|
144 | 143 |
{ |
145 | 144 |
TCGv tmp = tcg_temp_new(); |
146 | 145 |
TCGv_i32 tmp32 = tcg_temp_new_i32(); |
... | ... | |
151 | 150 |
tcg_temp_free(tmp); |
152 | 151 |
} |
153 | 152 |
|
154 |
static always_inline void gen_qemu_ldl_l (TCGv t0, TCGv t1, int flags)
|
|
153 |
static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags)
|
|
155 | 154 |
{ |
156 | 155 |
tcg_gen_mov_i64(cpu_lock, t1); |
157 | 156 |
tcg_gen_qemu_ld32s(t0, t1, flags); |
158 | 157 |
} |
159 | 158 |
|
160 |
static always_inline void gen_qemu_ldq_l (TCGv t0, TCGv t1, int flags)
|
|
159 |
static inline void gen_qemu_ldq_l(TCGv t0, TCGv t1, int flags)
|
|
161 | 160 |
{ |
162 | 161 |
tcg_gen_mov_i64(cpu_lock, t1); |
163 | 162 |
tcg_gen_qemu_ld64(t0, t1, flags); |
164 | 163 |
} |
165 | 164 |
|
166 |
static always_inline void gen_load_mem (DisasContext *ctx, |
|
167 |
void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1, int flags), |
|
168 |
int ra, int rb, int32_t disp16, |
|
169 |
int fp, int clear) |
|
165 |
static inline void gen_load_mem(DisasContext *ctx, |
|
166 |
void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1, |
|
167 |
int flags), |
|
168 |
int ra, int rb, int32_t disp16, int fp, |
|
169 |
int clear) |
|
170 | 170 |
{ |
171 | 171 |
TCGv addr; |
172 | 172 |
|
... | ... | |
190 | 190 |
tcg_temp_free(addr); |
191 | 191 |
} |
192 | 192 |
|
193 |
static always_inline void gen_qemu_stf (TCGv t0, TCGv t1, int flags)
|
|
193 |
static inline void gen_qemu_stf(TCGv t0, TCGv t1, int flags)
|
|
194 | 194 |
{ |
195 | 195 |
TCGv_i32 tmp32 = tcg_temp_new_i32(); |
196 | 196 |
TCGv tmp = tcg_temp_new(); |
... | ... | |
201 | 201 |
tcg_temp_free_i32(tmp32); |
202 | 202 |
} |
203 | 203 |
|
204 |
static always_inline void gen_qemu_stg (TCGv t0, TCGv t1, int flags)
|
|
204 |
static inline void gen_qemu_stg(TCGv t0, TCGv t1, int flags)
|
|
205 | 205 |
{ |
206 | 206 |
TCGv tmp = tcg_temp_new(); |
207 | 207 |
gen_helper_g_to_memory(tmp, t0); |
... | ... | |
209 | 209 |
tcg_temp_free(tmp); |
210 | 210 |
} |
211 | 211 |
|
212 |
static always_inline void gen_qemu_sts (TCGv t0, TCGv t1, int flags)
|
|
212 |
static inline void gen_qemu_sts(TCGv t0, TCGv t1, int flags)
|
|
213 | 213 |
{ |
214 | 214 |
TCGv_i32 tmp32 = tcg_temp_new_i32(); |
215 | 215 |
TCGv tmp = tcg_temp_new(); |
... | ... | |
220 | 220 |
tcg_temp_free_i32(tmp32); |
221 | 221 |
} |
222 | 222 |
|
223 |
static always_inline void gen_qemu_stl_c (TCGv t0, TCGv t1, int flags)
|
|
223 |
static inline void gen_qemu_stl_c(TCGv t0, TCGv t1, int flags)
|
|
224 | 224 |
{ |
225 | 225 |
int l1, l2; |
226 | 226 |
|
... | ... | |
236 | 236 |
tcg_gen_movi_i64(cpu_lock, -1); |
237 | 237 |
} |
238 | 238 |
|
239 |
static always_inline void gen_qemu_stq_c (TCGv t0, TCGv t1, int flags)
|
|
239 |
static inline void gen_qemu_stq_c(TCGv t0, TCGv t1, int flags)
|
|
240 | 240 |
{ |
241 | 241 |
int l1, l2; |
242 | 242 |
|
... | ... | |
252 | 252 |
tcg_gen_movi_i64(cpu_lock, -1); |
253 | 253 |
} |
254 | 254 |
|
255 |
static always_inline void gen_store_mem (DisasContext *ctx, |
|
256 |
void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, int flags), |
|
257 |
int ra, int rb, int32_t disp16, |
|
258 |
int fp, int clear, int local) |
|
255 |
static inline void gen_store_mem(DisasContext *ctx, |
|
256 |
void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, |
|
257 |
int flags), |
|
258 |
int ra, int rb, int32_t disp16, int fp, |
|
259 |
int clear, int local) |
|
259 | 260 |
{ |
260 | 261 |
TCGv addr; |
261 | 262 |
if (local) |
... | ... | |
288 | 289 |
tcg_temp_free(addr); |
289 | 290 |
} |
290 | 291 |
|
291 |
static always_inline void gen_bcond (DisasContext *ctx, |
|
292 |
TCGCond cond, |
|
293 |
int ra, int32_t disp, int mask) |
|
292 |
static inline void gen_bcond(DisasContext *ctx, TCGCond cond, int ra, |
|
293 |
int32_t disp, int mask) |
|
294 | 294 |
{ |
295 | 295 |
int l1, l2; |
296 | 296 |
|
... | ... | |
317 | 317 |
gen_set_label(l2); |
318 | 318 |
} |
319 | 319 |
|
320 |
static always_inline void gen_fbcond (DisasContext *ctx, int opc,
|
|
321 |
int ra, int32_t disp16)
|
|
320 |
static inline void gen_fbcond(DisasContext *ctx, int opc, int ra,
|
|
321 |
int32_t disp16) |
|
322 | 322 |
{ |
323 | 323 |
int l1, l2; |
324 | 324 |
TCGv tmp; |
... | ... | |
363 | 363 |
gen_set_label(l2); |
364 | 364 |
} |
365 | 365 |
|
366 |
static always_inline void gen_cmov (TCGCond inv_cond, |
|
367 |
int ra, int rb, int rc, |
|
368 |
int islit, uint8_t lit, int mask) |
|
366 |
static inline void gen_cmov(TCGCond inv_cond, int ra, int rb, int rc, |
|
367 |
int islit, uint8_t lit, int mask) |
|
369 | 368 |
{ |
370 | 369 |
int l1; |
371 | 370 |
|
... | ... | |
397 | 396 |
} |
398 | 397 |
|
399 | 398 |
#define FARITH2(name) \ |
400 |
static always_inline void glue(gen_f, name)(int rb, int rc) \
|
|
399 |
static inline void glue(gen_f, name)(int rb, int rc) \
|
|
401 | 400 |
{ \ |
402 | 401 |
if (unlikely(rc == 31)) \ |
403 | 402 |
return; \ |
... | ... | |
429 | 428 |
FARITH2(cvtqlsv) |
430 | 429 |
|
431 | 430 |
#define FARITH3(name) \ |
432 |
static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \
|
|
431 |
static inline void glue(gen_f, name)(int ra, int rb, int rc) \
|
|
433 | 432 |
{ \ |
434 | 433 |
if (unlikely(rc == 31)) \ |
435 | 434 |
return; \ |
... | ... | |
480 | 479 |
FARITH3(cpyse) |
481 | 480 |
|
482 | 481 |
#define FCMOV(name) \ |
483 |
static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \
|
|
482 |
static inline void glue(gen_f, name)(int ra, int rb, int rc) \
|
|
484 | 483 |
{ \ |
485 | 484 |
int l1; \ |
486 | 485 |
TCGv tmp; \ |
... | ... | |
512 | 511 |
FCMOV(cmpfgt) |
513 | 512 |
|
514 | 513 |
/* EXTWH, EXTWH, EXTLH, EXTQH */ |
515 |
static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), |
|
516 |
int ra, int rb, int rc, |
|
517 |
int islit, uint8_t lit) |
|
514 |
static inline void gen_ext_h(void(*tcg_gen_ext_i64)(TCGv t0, TCGv t1), |
|
515 |
int ra, int rb, int rc, int islit, uint8_t lit) |
|
518 | 516 |
{ |
519 | 517 |
if (unlikely(rc == 31)) |
520 | 518 |
return; |
... | ... | |
543 | 541 |
} |
544 | 542 |
|
545 | 543 |
/* EXTBL, EXTWL, EXTWL, EXTLL, EXTQL */ |
546 |
static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), |
|
547 |
int ra, int rb, int rc, |
|
548 |
int islit, uint8_t lit) |
|
544 |
static inline void gen_ext_l(void(*tcg_gen_ext_i64)(TCGv t0, TCGv t1), |
|
545 |
int ra, int rb, int rc, int islit, uint8_t lit) |
|
549 | 546 |
{ |
550 | 547 |
if (unlikely(rc == 31)) |
551 | 548 |
return; |
... | ... | |
568 | 565 |
|
569 | 566 |
/* Code to call arith3 helpers */ |
570 | 567 |
#define ARITH3(name) \ |
571 |
static always_inline void glue(gen_, name) (int ra, int rb, int rc, \
|
|
572 |
int islit, uint8_t lit) \
|
|
568 |
static inline void glue(gen_, name)(int ra, int rb, int rc, int islit,\
|
|
569 |
uint8_t lit) \
|
|
573 | 570 |
{ \ |
574 | 571 |
if (unlikely(rc == 31)) \ |
575 | 572 |
return; \ |
... | ... | |
617 | 614 |
ARITH3(mullv) |
618 | 615 |
ARITH3(mulqv) |
619 | 616 |
|
620 |
static always_inline void gen_cmp(TCGCond cond, |
|
621 |
int ra, int rb, int rc, |
|
622 |
int islit, uint8_t lit) |
|
617 |
static inline void gen_cmp(TCGCond cond, int ra, int rb, int rc, int islit, |
|
618 |
uint8_t lit) |
|
623 | 619 |
{ |
624 | 620 |
int l1, l2; |
625 | 621 |
TCGv tmp; |
... | ... | |
647 | 643 |
gen_set_label(l2); |
648 | 644 |
} |
649 | 645 |
|
650 |
static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
|
|
646 |
static inline int translate_one(DisasContext *ctx, uint32_t insn)
|
|
651 | 647 |
{ |
652 | 648 |
uint32_t palcode; |
653 | 649 |
int32_t disp21, disp16, disp12; |
... | ... | |
2336 | 2332 |
return ret; |
2337 | 2333 |
} |
2338 | 2334 |
|
2339 |
static always_inline void gen_intermediate_code_internal (CPUState *env,
|
|
2340 |
TranslationBlock *tb,
|
|
2341 |
int search_pc)
|
|
2335 |
static inline void gen_intermediate_code_internal(CPUState *env,
|
|
2336 |
TranslationBlock *tb, |
|
2337 |
int search_pc) |
|
2342 | 2338 |
{ |
2343 | 2339 |
#if defined ALPHA_DEBUG_DISAS |
2344 | 2340 |
static int insn_count; |
b/target-ppc/cpu.h | ||
---|---|---|
781 | 781 |
#endif |
782 | 782 |
#endif |
783 | 783 |
|
784 |
static always_inline uint64_t ppc_dump_gpr (CPUPPCState *env, int gprn)
|
|
784 |
static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
|
|
785 | 785 |
{ |
786 | 786 |
uint64_t gprv; |
787 | 787 |
|
b/target-ppc/exec.h | ||
---|---|---|
35 | 35 |
#include "softmmu_exec.h" |
36 | 36 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
37 | 37 |
|
38 |
static always_inline void env_to_regs (void)
|
|
38 |
static inline void env_to_regs(void)
|
|
39 | 39 |
{ |
40 | 40 |
} |
41 | 41 |
|
42 |
static always_inline void regs_to_env (void)
|
|
42 |
static inline void regs_to_env(void)
|
|
43 | 43 |
{ |
44 | 44 |
} |
45 | 45 |
|
46 |
static always_inline int cpu_has_work(CPUState *env)
|
|
46 |
static inline int cpu_has_work(CPUState *env) |
|
47 | 47 |
{ |
48 | 48 |
return (msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD)); |
49 | 49 |
} |
50 | 50 |
|
51 | 51 |
|
52 |
static always_inline int cpu_halted (CPUState *env)
|
|
52 |
static inline int cpu_halted(CPUState *env)
|
|
53 | 53 |
{ |
54 | 54 |
if (!env->halted) |
55 | 55 |
return 0; |
b/target-ppc/helper.c | ||
---|---|---|
104 | 104 |
|
105 | 105 |
#else |
106 | 106 |
/* Common routines used by software and hardware TLBs emulation */ |
107 |
static always_inline int pte_is_valid (target_ulong pte0)
|
|
107 |
static inline int pte_is_valid(target_ulong pte0)
|
|
108 | 108 |
{ |
109 | 109 |
return pte0 & 0x80000000 ? 1 : 0; |
110 | 110 |
} |
111 | 111 |
|
112 |
static always_inline void pte_invalidate (target_ulong *pte0)
|
|
112 |
static inline void pte_invalidate(target_ulong *pte0)
|
|
113 | 113 |
{ |
114 | 114 |
*pte0 &= ~0x80000000; |
115 | 115 |
} |
116 | 116 |
|
117 | 117 |
#if defined(TARGET_PPC64) |
118 |
static always_inline int pte64_is_valid (target_ulong pte0)
|
|
118 |
static inline int pte64_is_valid(target_ulong pte0)
|
|
119 | 119 |
{ |
120 | 120 |
return pte0 & 0x0000000000000001ULL ? 1 : 0; |
121 | 121 |
} |
122 | 122 |
|
123 |
static always_inline void pte64_invalidate (target_ulong *pte0)
|
|
123 |
static inline void pte64_invalidate(target_ulong *pte0)
|
|
124 | 124 |
{ |
125 | 125 |
*pte0 &= ~0x0000000000000001ULL; |
126 | 126 |
} |
... | ... | |
133 | 133 |
#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F) |
134 | 134 |
#endif |
135 | 135 |
|
136 |
static always_inline int pp_check (int key, int pp, int nx)
|
|
136 |
static inline int pp_check(int key, int pp, int nx)
|
|
137 | 137 |
{ |
138 | 138 |
int access; |
139 | 139 |
|
... | ... | |
173 | 173 |
return access; |
174 | 174 |
} |
175 | 175 |
|
176 |
static always_inline int check_prot (int prot, int rw, int access_type)
|
|
176 |
static inline int check_prot(int prot, int rw, int access_type)
|
|
177 | 177 |
{ |
178 | 178 |
int ret; |
179 | 179 |
|
... | ... | |
197 | 197 |
return ret; |
198 | 198 |
} |
199 | 199 |
|
200 |
static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b, |
|
201 |
target_ulong pte0, target_ulong pte1, |
|
202 |
int h, int rw, int type) |
|
200 |
static inline int _pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0, |
|
201 |
target_ulong pte1, int h, int rw, int type) |
|
203 | 202 |
{ |
204 | 203 |
target_ulong ptem, mmask; |
205 | 204 |
int access, ret, pteh, ptev, pp; |
... | ... | |
260 | 259 |
return ret; |
261 | 260 |
} |
262 | 261 |
|
263 |
static always_inline int pte32_check (mmu_ctx_t *ctx, |
|
264 |
target_ulong pte0, target_ulong pte1, |
|
265 |
int h, int rw, int type) |
|
262 |
static inline int pte32_check(mmu_ctx_t *ctx, target_ulong pte0, |
|
263 |
target_ulong pte1, int h, int rw, int type) |
|
266 | 264 |
{ |
267 | 265 |
return _pte_check(ctx, 0, pte0, pte1, h, rw, type); |
268 | 266 |
} |
269 | 267 |
|
270 | 268 |
#if defined(TARGET_PPC64) |
271 |
static always_inline int pte64_check (mmu_ctx_t *ctx, |
|
272 |
target_ulong pte0, target_ulong pte1, |
|
273 |
int h, int rw, int type) |
|
269 |
static inline int pte64_check(mmu_ctx_t *ctx, target_ulong pte0, |
|
270 |
target_ulong pte1, int h, int rw, int type) |
|
274 | 271 |
{ |
275 | 272 |
return _pte_check(ctx, 1, pte0, pte1, h, rw, type); |
276 | 273 |
} |
277 | 274 |
#endif |
278 | 275 |
|
279 |
static always_inline int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
|
|
280 |
int ret, int rw)
|
|
276 |
static inline int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p,
|
|
277 |
int ret, int rw) |
|
281 | 278 |
{ |
282 | 279 |
int store = 0; |
283 | 280 |
|
... | ... | |
302 | 299 |
} |
303 | 300 |
|
304 | 301 |
/* Software driven TLB helpers */ |
305 |
static always_inline int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
|
|
306 |
int way, int is_code)
|
|
302 |
static inline int ppc6xx_tlb_getnum(CPUState *env, target_ulong eaddr, int way,
|
|
303 |
int is_code) |
|
307 | 304 |
{ |
308 | 305 |
int nr; |
309 | 306 |
|
... | ... | |
318 | 315 |
return nr; |
319 | 316 |
} |
320 | 317 |
|
321 |
static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env)
|
|
318 |
static inline void ppc6xx_tlb_invalidate_all(CPUState *env)
|
|
322 | 319 |
{ |
323 | 320 |
ppc6xx_tlb_t *tlb; |
324 | 321 |
int nr, max; |
... | ... | |
335 | 332 |
tlb_flush(env, 1); |
336 | 333 |
} |
337 | 334 |
|
338 |
static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env, |
|
339 |
target_ulong eaddr, |
|
340 |
int is_code, |
|
341 |
int match_epn) |
|
335 |
static inline void __ppc6xx_tlb_invalidate_virt(CPUState *env, |
|
336 |
target_ulong eaddr, |
|
337 |
int is_code, int match_epn) |
|
342 | 338 |
{ |
343 | 339 |
#if !defined(FLUSH_ALL_TLBS) |
344 | 340 |
ppc6xx_tlb_t *tlb; |
... | ... | |
361 | 357 |
#endif |
362 | 358 |
} |
363 | 359 |
|
364 |
static always_inline void ppc6xx_tlb_invalidate_virt (CPUState *env, |
|
365 |
target_ulong eaddr, |
|
366 |
int is_code) |
|
360 |
static inline void ppc6xx_tlb_invalidate_virt(CPUState *env, |
|
361 |
target_ulong eaddr, int is_code) |
|
367 | 362 |
{ |
368 | 363 |
__ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0); |
369 | 364 |
} |
... | ... | |
387 | 382 |
env->last_way = way; |
388 | 383 |
} |
389 | 384 |
|
390 |
static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx, |
|
391 |
target_ulong eaddr, int rw, |
|
392 |
int access_type) |
|
385 |
static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx, |
|
386 |
target_ulong eaddr, int rw, int access_type) |
|
393 | 387 |
{ |
394 | 388 |
ppc6xx_tlb_t *tlb; |
395 | 389 |
int nr, best, way; |
... | ... | |
452 | 446 |
} |
453 | 447 |
|
454 | 448 |
/* Perform BAT hit & translation */ |
455 |
static always_inline void bat_size_prot (CPUState *env, target_ulong *blp,
|
|
456 |
int *validp, int *protp,
|
|
457 |
target_ulong *BATu, target_ulong *BATl)
|
|
449 |
static inline void bat_size_prot(CPUState *env, target_ulong *blp, int *validp,
|
|
450 |
int *protp, target_ulong *BATu,
|
|
451 |
target_ulong *BATl) |
|
458 | 452 |
{ |
459 | 453 |
target_ulong bl; |
460 | 454 |
int pp, valid, prot; |
... | ... | |
477 | 471 |
*protp = prot; |
478 | 472 |
} |
479 | 473 |
|
480 |
static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp, |
|
481 |
int *validp, int *protp, |
|
482 |
target_ulong *BATu, |
|
483 |
target_ulong *BATl) |
|
474 |
static inline void bat_601_size_prot(CPUState *env, target_ulong *blp, |
|
475 |
int *validp, int *protp, |
|
476 |
target_ulong *BATu, target_ulong *BATl) |
|
484 | 477 |
{ |
485 | 478 |
target_ulong bl; |
486 | 479 |
int key, pp, valid, prot; |
... | ... | |
503 | 496 |
*protp = prot; |
504 | 497 |
} |
505 | 498 |
|
506 |
static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
|
|
507 |
target_ulong virtual, int rw, int type)
|
|
499 |
static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual,
|
|
500 |
int rw, int type) |
|
508 | 501 |
{ |
509 | 502 |
target_ulong *BATlt, *BATut, *BATu, *BATl; |
510 | 503 |
target_ulong base, BEPIl, BEPIu, bl; |
... | ... | |
579 | 572 |
} |
580 | 573 |
|
581 | 574 |
/* PTE table lookup */ |
582 |
static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, |
|
583 |
int rw, int type, |
|
584 |
int target_page_bits) |
|
575 |
static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw, |
|
576 |
int type, int target_page_bits) |
|
585 | 577 |
{ |
586 | 578 |
target_ulong base, pte0, pte1; |
587 | 579 |
int i, good = -1; |
... | ... | |
664 | 656 |
return ret; |
665 | 657 |
} |
666 | 658 |
|
667 |
static always_inline int find_pte32 (mmu_ctx_t *ctx, int h, int rw,
|
|
668 |
int type, int target_page_bits)
|
|
659 |
static inline int find_pte32(mmu_ctx_t *ctx, int h, int rw, int type,
|
|
660 |
int target_page_bits) |
|
669 | 661 |
{ |
670 | 662 |
return _find_pte(ctx, 0, h, rw, type, target_page_bits); |
671 | 663 |
} |
672 | 664 |
|
673 | 665 |
#if defined(TARGET_PPC64) |
674 |
static always_inline int find_pte64 (mmu_ctx_t *ctx, int h, int rw,
|
|
675 |
int type, int target_page_bits)
|
|
666 |
static inline int find_pte64(mmu_ctx_t *ctx, int h, int rw, int type,
|
|
667 |
int target_page_bits) |
|
676 | 668 |
{ |
677 | 669 |
return _find_pte(ctx, 1, h, rw, type, target_page_bits); |
678 | 670 |
} |
679 | 671 |
#endif |
680 | 672 |
|
681 |
static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx, |
|
682 |
int h, int rw, int type, |
|
683 |
int target_page_bits) |
|
673 |
static inline int find_pte(CPUState *env, mmu_ctx_t *ctx, int h, int rw, |
|
674 |
int type, int target_page_bits) |
|
684 | 675 |
{ |
685 | 676 |
#if defined(TARGET_PPC64) |
686 | 677 |
if (env->mmu_model & POWERPC_MMU_64) |
... | ... | |
721 | 712 |
entry->tmp = slb->tmp; |
722 | 713 |
} |
723 | 714 |
|
724 |
static always_inline int slb_is_valid (ppc_slb_t *slb)
|
|
715 |
static inline int slb_is_valid(ppc_slb_t *slb)
|
|
725 | 716 |
{ |
726 | 717 |
return (int)(slb->tmp64 & 0x0000000008000000ULL); |
727 | 718 |
} |
728 | 719 |
|
729 |
static always_inline void slb_invalidate (ppc_slb_t *slb)
|
|
720 |
static inline void slb_invalidate(ppc_slb_t *slb)
|
|
730 | 721 |
{ |
731 | 722 |
slb->tmp64 &= ~0x0000000008000000ULL; |
732 | 723 |
} |
733 | 724 |
|
734 |
static always_inline int slb_lookup (CPUPPCState *env, target_ulong eaddr, |
|
735 |
target_ulong *vsid, |
|
736 |
target_ulong *page_mask, int *attr, |
|
737 |
int *target_page_bits) |
|
725 |
static inline int slb_lookup(CPUPPCState *env, target_ulong eaddr, |
|
726 |
target_ulong *vsid, target_ulong *page_mask, |
|
727 |
int *attr, int *target_page_bits) |
|
738 | 728 |
{ |
739 | 729 |
target_ulong mask; |
740 | 730 |
int n, ret; |
... | ... | |
868 | 858 |
#endif /* defined(TARGET_PPC64) */ |
869 | 859 |
|
870 | 860 |
/* Perform segment based translation */ |
871 |
static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
|
|
872 |
int sdr_sh,
|
|
873 |
target_phys_addr_t hash,
|
|
874 |
target_phys_addr_t mask)
|
|
861 |
static inline target_phys_addr_t get_pgaddr(target_phys_addr_t sdr1,
|
|
862 |
int sdr_sh, |
|
863 |
target_phys_addr_t hash, |
|
864 |
target_phys_addr_t mask) |
|
875 | 865 |
{ |
876 | 866 |
return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask); |
877 | 867 |
} |
878 | 868 |
|
879 |
static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
|
|
880 |
target_ulong eaddr, int rw, int type)
|
|
869 |
static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
|
|
870 |
target_ulong eaddr, int rw, int type) |
|
881 | 871 |
{ |
882 | 872 |
target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask; |
883 | 873 |
target_ulong sr, vsid, vsid_mask, pgidx, page_mask; |
... | ... | |
1063 | 1053 |
} |
1064 | 1054 |
|
1065 | 1055 |
/* Generic TLB check function for embedded PowerPC implementations */ |
1066 |
static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
|
|
1067 |
target_phys_addr_t *raddrp,
|
|
1068 |
target_ulong address,
|
|
1069 |
uint32_t pid, int ext, int i)
|
|
1056 |
static inline int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
|
|
1057 |
target_phys_addr_t *raddrp, |
|
1058 |
target_ulong address, uint32_t pid, int ext,
|
|
1059 |
int i) |
|
1070 | 1060 |
{ |
1071 | 1061 |
target_ulong mask; |
1072 | 1062 |
|
... | ... | |
1117 | 1107 |
} |
1118 | 1108 |
|
1119 | 1109 |
/* Helpers specific to PowerPC 40x implementations */ |
1120 |
static always_inline void ppc4xx_tlb_invalidate_all (CPUState *env)
|
|
1110 |
static inline void ppc4xx_tlb_invalidate_all(CPUState *env)
|
|
1121 | 1111 |
{ |
1122 | 1112 |
ppcemb_tlb_t *tlb; |
1123 | 1113 |
int i; |
... | ... | |
1129 | 1119 |
tlb_flush(env, 1); |
1130 | 1120 |
} |
1131 | 1121 |
|
1132 |
static always_inline void ppc4xx_tlb_invalidate_virt (CPUState *env, |
|
1133 |
target_ulong eaddr, |
|
1134 |
uint32_t pid) |
|
1122 |
static inline void ppc4xx_tlb_invalidate_virt(CPUState *env, |
|
1123 |
target_ulong eaddr, uint32_t pid) |
|
1135 | 1124 |
{ |
1136 | 1125 |
#if !defined(FLUSH_ALL_TLBS) |
1137 | 1126 |
ppcemb_tlb_t *tlb; |
... | ... | |
1270 | 1259 |
return ret; |
1271 | 1260 |
} |
1272 | 1261 |
|
1273 |
static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx,
|
|
1274 |
target_ulong eaddr, int rw)
|
|
1262 |
static inline int check_physical(CPUState *env, mmu_ctx_t *ctx,
|
|
1263 |
target_ulong eaddr, int rw) |
|
1275 | 1264 |
{ |
1276 | 1265 |
int in_plb, ret; |
1277 | 1266 |
|
... | ... | |
1674 | 1663 |
/*****************************************************************************/ |
1675 | 1664 |
/* BATs management */ |
1676 | 1665 |
#if !defined(FLUSH_ALL_TLBS) |
1677 |
static always_inline void do_invalidate_BAT (CPUPPCState *env, |
|
1678 |
target_ulong BATu, |
|
1679 |
target_ulong mask) |
|
1666 |
static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu, |
|
1667 |
target_ulong mask) |
|
1680 | 1668 |
{ |
1681 | 1669 |
target_ulong base, end, page; |
1682 | 1670 |
|
... | ... | |
1690 | 1678 |
} |
1691 | 1679 |
#endif |
1692 | 1680 |
|
1693 |
static always_inline void dump_store_bat (CPUPPCState *env, char ID,
|
|
1694 |
int ul, int nr, target_ulong value)
|
|
1681 |
static inline void dump_store_bat(CPUPPCState *env, char ID, int ul, int nr,
|
|
1682 |
target_ulong value) |
|
1695 | 1683 |
{ |
1696 | 1684 |
LOG_BATS("Set %cBAT%d%c to " ADDRX " (" ADDRX ")\n", |
1697 | 1685 |
ID, nr, ul == 0 ? 'u' : 'l', value, env->nip); |
... | ... | |
2046 | 2034 |
env->error_code = 0; |
2047 | 2035 |
} |
2048 | 2036 |
#else /* defined (CONFIG_USER_ONLY) */ |
2049 |
static always_inline void dump_syscall (CPUState *env)
|
|
2037 |
static inline void dump_syscall(CPUState *env)
|
|
2050 | 2038 |
{ |
2051 | 2039 |
qemu_log_mask(CPU_LOG_INT, "syscall r0=" REGX " r3=" REGX " r4=" REGX |
2052 | 2040 |
" r5=" REGX " r6=" REGX " nip=" ADDRX "\n", |
... | ... | |
2057 | 2045 |
/* Note that this function should be greatly optimized |
2058 | 2046 |
* when called with a constant excp, from ppc_hw_interrupt |
2059 | 2047 |
*/ |
2060 |
static always_inline void powerpc_excp (CPUState *env, |
|
2061 |
int excp_model, int excp) |
|
2048 |
static inline void powerpc_excp(CPUState *env, int excp_model, int excp) |
|
2062 | 2049 |
{ |
2063 | 2050 |
target_ulong msr, new_msr, vector; |
2064 | 2051 |
int srr0, srr1, asrr0, asrr1; |
b/target-ppc/helper_regs.h | ||
---|---|---|
21 | 21 |
#define __HELPER_REGS_H__ |
22 | 22 |
|
23 | 23 |
/* Swap temporary saved registers with GPRs */ |
24 |
static always_inline void hreg_swap_gpr_tgpr (CPUPPCState *env)
|
|
24 |
static inline void hreg_swap_gpr_tgpr(CPUPPCState *env)
|
|
25 | 25 |
{ |
26 | 26 |
target_ulong tmp; |
27 | 27 |
|
... | ... | |
39 | 39 |
env->tgpr[3] = tmp; |
40 | 40 |
} |
41 | 41 |
|
42 |
static always_inline void hreg_compute_mem_idx (CPUPPCState *env)
|
|
42 |
static inline void hreg_compute_mem_idx(CPUPPCState *env)
|
|
43 | 43 |
{ |
44 | 44 |
/* Precompute MMU index */ |
45 | 45 |
if (msr_pr == 0 && msr_hv != 0) { |
... | ... | |
49 | 49 |
} |
50 | 50 |
} |
51 | 51 |
|
52 |
static always_inline void hreg_compute_hflags (CPUPPCState *env)
|
|
52 |
static inline void hreg_compute_hflags(CPUPPCState *env)
|
|
53 | 53 |
{ |
54 | 54 |
target_ulong hflags_mask; |
55 | 55 |
|
... | ... | |
64 | 64 |
env->hflags |= env->hflags_nmsr; |
65 | 65 |
} |
66 | 66 |
|
67 |
static always_inline int hreg_store_msr (CPUPPCState *env, target_ulong value,
|
|
68 |
int alter_hv)
|
|
67 |
static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
|
|
68 |
int alter_hv) |
|
69 | 69 |
{ |
70 | 70 |
int excp; |
71 | 71 |
|
b/target-ppc/op_helper.c | ||
---|---|---|
239 | 239 |
/*****************************************************************************/ |
240 | 240 |
/* Memory load and stores */ |
241 | 241 |
|
242 |
static always_inline target_ulong addr_add(target_ulong addr, target_long arg)
|
|
242 |
static inline target_ulong addr_add(target_ulong addr, target_long arg) |
|
243 | 243 |
{ |
244 | 244 |
#if defined(TARGET_PPC64) |
245 | 245 |
if (!msr_sf) |
... | ... | |
532 | 532 |
return f.l; |
533 | 533 |
} |
534 | 534 |
|
535 |
static always_inline int isden (float64 d)
|
|
535 |
static inline int isden(float64 d)
|
|
536 | 536 |
{ |
537 | 537 |
CPU_DoubleU u; |
538 | 538 |
|
... | ... | |
594 | 594 |
} |
595 | 595 |
|
596 | 596 |
/* Floating-point invalid operations exception */ |
597 |
static always_inline uint64_t fload_invalid_op_excp (int op)
|
|
597 |
static inline uint64_t fload_invalid_op_excp(int op)
|
|
598 | 598 |
{ |
599 | 599 |
uint64_t ret = 0; |
600 | 600 |
int ve; |
... | ... | |
675 | 675 |
return ret; |
676 | 676 |
} |
677 | 677 |
|
678 |
static always_inline void float_zero_divide_excp (void)
|
|
678 |
static inline void float_zero_divide_excp(void)
|
|
679 | 679 |
{ |
680 | 680 |
env->fpscr |= 1 << FPSCR_ZX; |
681 | 681 |
env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); |
... | ... | |
691 | 691 |
} |
692 | 692 |
} |
693 | 693 |
|
694 |
static always_inline void float_overflow_excp (void)
|
|
694 |
static inline void float_overflow_excp(void)
|
|
695 | 695 |
{ |
696 | 696 |
env->fpscr |= 1 << FPSCR_OX; |
697 | 697 |
/* Update the floating-point exception summary */ |
... | ... | |
709 | 709 |
} |
710 | 710 |
} |
711 | 711 |
|
712 |
static always_inline void float_underflow_excp (void)
|
|
712 |
static inline void float_underflow_excp(void)
|
|
713 | 713 |
{ |
714 | 714 |
env->fpscr |= 1 << FPSCR_UX; |
715 | 715 |
/* Update the floating-point exception summary */ |
... | ... | |
724 | 724 |
} |
725 | 725 |
} |
726 | 726 |
|
727 |
static always_inline void float_inexact_excp (void)
|
|
727 |
static inline void float_inexact_excp(void)
|
|
728 | 728 |
{ |
729 | 729 |
env->fpscr |= 1 << FPSCR_XX; |
730 | 730 |
/* Update the floating-point exception summary */ |
... | ... | |
738 | 738 |
} |
739 | 739 |
} |
740 | 740 |
|
741 |
static always_inline void fpscr_set_rounding_mode (void)
|
|
741 |
static inline void fpscr_set_rounding_mode(void)
|
|
742 | 742 |
{ |
743 | 743 |
int rnd_type; |
744 | 744 |
|
... | ... | |
1199 | 1199 |
|
1200 | 1200 |
#endif |
1201 | 1201 |
|
1202 |
static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
|
|
1202 |
static inline uint64_t do_fri(uint64_t arg, int rounding_mode)
|
|
1203 | 1203 |
{ |
1204 | 1204 |
CPU_DoubleU farg; |
1205 | 1205 |
farg.ll = arg; |
... | ... | |
1614 | 1614 |
} |
1615 | 1615 |
} |
1616 | 1616 |
|
1617 |
static always_inline void do_rfi (target_ulong nip, target_ulong msr,
|
|
1618 |
target_ulong msrm, int keep_msrh)
|
|
1617 |
static inline void do_rfi(target_ulong nip, target_ulong msr,
|
|
1618 |
target_ulong msrm, int keep_msrh) |
|
1619 | 1619 |
{ |
1620 | 1620 |
#if defined(TARGET_PPC64) |
1621 | 1621 |
if (msr & (1ULL << MSR_SF)) { |
... | ... | |
1956 | 1956 |
|
1957 | 1957 |
/* Saturating arithmetic helpers. */ |
1958 | 1958 |
#define SATCVT(from, to, from_type, to_type, min, max, use_min, use_max) \ |
1959 |
static always_inline to_type cvt##from##to (from_type x, int *sat) \
|
|
1959 |
static inline to_type cvt##from##to(from_type x, int *sat) \
|
|
1960 | 1960 |
{ \ |
1961 | 1961 |
to_type r; \ |
1962 | 1962 |
if (use_min && x < min) { \ |
... | ... | |
1975 | 1975 |
SATCVT(sd, sw, int64_t, int32_t, INT32_MIN, INT32_MAX, 1, 1) |
1976 | 1976 |
|
1977 | 1977 |
/* Work around gcc problems with the macro version */ |
1978 |
static always_inline uint8_t cvtuhub(uint16_t x, int *sat)
|
|
1978 |
static inline uint8_t cvtuhub(uint16_t x, int *sat) |
|
1979 | 1979 |
{ |
1980 | 1980 |
uint8_t r; |
1981 | 1981 |
|
... | ... | |
2243 | 2243 |
#undef VCMPFP_DO |
2244 | 2244 |
#undef VCMPFP |
2245 | 2245 |
|
2246 |
static always_inline void vcmpbfp_internal (ppc_avr_t *r, ppc_avr_t *a,
|
|
2247 |
ppc_avr_t *b, int record)
|
|
2246 |
static inline void vcmpbfp_internal(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
|
|
2247 |
int record) |
|
2248 | 2248 |
{ |
2249 | 2249 |
int i; |
2250 | 2250 |
int all_in = 0; |
... | ... | |
3063 | 3063 |
0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF, |
3064 | 3064 |
}; |
3065 | 3065 |
|
3066 |
static always_inline uint8_t byte_reverse (uint8_t val)
|
|
3066 |
static inline uint8_t byte_reverse(uint8_t val)
|
|
3067 | 3067 |
{ |
3068 | 3068 |
return hbrev[val >> 4] | (hbrev[val & 0xF] << 4); |
3069 | 3069 |
} |
3070 | 3070 |
|
3071 |
static always_inline uint32_t word_reverse (uint32_t val)
|
|
3071 |
static inline uint32_t word_reverse(uint32_t val)
|
|
3072 | 3072 |
{ |
3073 | 3073 |
return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) | |
3074 | 3074 |
(byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24); |
... | ... | |
3100 | 3100 |
} |
3101 | 3101 |
|
3102 | 3102 |
/* Single-precision floating-point conversions */ |
3103 |
static always_inline uint32_t efscfsi (uint32_t val)
|
|
3103 |
static inline uint32_t efscfsi(uint32_t val)
|
|
3104 | 3104 |
{ |
3105 | 3105 |
CPU_FloatU u; |
3106 | 3106 |
|
... | ... | |
3109 | 3109 |
return u.l; |
3110 | 3110 |
} |
3111 | 3111 |
|
3112 |
static always_inline uint32_t efscfui (uint32_t val)
|
|
3112 |
static inline uint32_t efscfui(uint32_t val)
|
|
3113 | 3113 |
{ |
3114 | 3114 |
CPU_FloatU u; |
3115 | 3115 |
|
... | ... | |
3118 | 3118 |
return u.l; |
3119 | 3119 |
} |
3120 | 3120 |
|
3121 |
static always_inline int32_t efsctsi (uint32_t val)
|
|
3121 |
static inline int32_t efsctsi(uint32_t val)
|
|
3122 | 3122 |
{ |
3123 | 3123 |
CPU_FloatU u; |
3124 | 3124 |
|
... | ... | |
3130 | 3130 |
return float32_to_int32(u.f, &env->vec_status); |
3131 | 3131 |
} |
3132 | 3132 |
|
3133 |
static always_inline uint32_t efsctui (uint32_t val)
|
|
3133 |
static inline uint32_t efsctui(uint32_t val)
|
|
3134 | 3134 |
{ |
3135 | 3135 |
CPU_FloatU u; |
3136 | 3136 |
|
... | ... | |
3142 | 3142 |
return float32_to_uint32(u.f, &env->vec_status); |
3143 | 3143 |
} |
3144 | 3144 |
|
3145 |
static always_inline uint32_t efsctsiz (uint32_t val)
|
|
3145 |
static inline uint32_t efsctsiz(uint32_t val)
|
|
3146 | 3146 |
{ |
3147 | 3147 |
CPU_FloatU u; |
3148 | 3148 |
|
... | ... | |
3154 | 3154 |
return float32_to_int32_round_to_zero(u.f, &env->vec_status); |
3155 | 3155 |
} |
3156 | 3156 |
|
3157 |
static always_inline uint32_t efsctuiz (uint32_t val)
|
|
3157 |
static inline uint32_t efsctuiz(uint32_t val)
|
|
3158 | 3158 |
{ |
3159 | 3159 |
CPU_FloatU u; |
3160 | 3160 |
|
... | ... | |
3166 | 3166 |
return float32_to_uint32_round_to_zero(u.f, &env->vec_status); |
3167 | 3167 |
} |
3168 | 3168 |
|
3169 |
static always_inline uint32_t efscfsf (uint32_t val)
|
|
3169 |
static inline uint32_t efscfsf(uint32_t val)
|
|
3170 | 3170 |
{ |
3171 | 3171 |
CPU_FloatU u; |
3172 | 3172 |
float32 tmp; |
... | ... | |
3178 | 3178 |
return u.l; |
3179 | 3179 |
} |
3180 | 3180 |
|
3181 |
static always_inline uint32_t efscfuf (uint32_t val)
|
|
3181 |
static inline uint32_t efscfuf(uint32_t val)
|
|
3182 | 3182 |
{ |
3183 | 3183 |
CPU_FloatU u; |
3184 | 3184 |
float32 tmp; |
... | ... | |
3190 | 3190 |
return u.l; |
3191 | 3191 |
} |
3192 | 3192 |
|
3193 |
static always_inline uint32_t efsctsf (uint32_t val)
|
|
3193 |
static inline uint32_t efsctsf(uint32_t val)
|
|
3194 | 3194 |
{ |
3195 | 3195 |
CPU_FloatU u; |
3196 | 3196 |
float32 tmp; |
... | ... | |
3205 | 3205 |
return float32_to_int32(u.f, &env->vec_status); |
3206 | 3206 |
} |
3207 | 3207 |
|
3208 |
static always_inline uint32_t efsctuf (uint32_t val)
|
|
3208 |
static inline uint32_t efsctuf(uint32_t val)
|
|
3209 | 3209 |
{ |
3210 | 3210 |
CPU_FloatU u; |
3211 | 3211 |
float32 tmp; |
... | ... | |
3274 | 3274 |
HELPER_SPE_VECTOR_CONV(fsctuf); |
3275 | 3275 |
|
3276 | 3276 |
/* Single-precision floating-point arithmetic */ |
3277 |
static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
|
|
3277 |
static inline uint32_t efsadd(uint32_t op1, uint32_t op2)
|
|
3278 | 3278 |
{ |
3279 | 3279 |
CPU_FloatU u1, u2; |
3280 | 3280 |
u1.l = op1; |
... | ... | |
3283 | 3283 |
return u1.l; |
3284 | 3284 |
} |
3285 | 3285 |
|
3286 |
static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
|
|
3286 |
static inline uint32_t efssub(uint32_t op1, uint32_t op2)
|
|
3287 | 3287 |
{ |
3288 | 3288 |
CPU_FloatU u1, u2; |
3289 | 3289 |
u1.l = op1; |
... | ... | |
3292 | 3292 |
return u1.l; |
3293 | 3293 |
} |
3294 | 3294 |
|
3295 |
static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
|
|
3295 |
static inline uint32_t efsmul(uint32_t op1, uint32_t op2)
|
|
3296 | 3296 |
{ |
3297 | 3297 |
CPU_FloatU u1, u2; |
3298 | 3298 |
u1.l = op1; |
... | ... | |
3301 | 3301 |
return u1.l; |
3302 | 3302 |
} |
3303 | 3303 |
|
3304 |
static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
|
|
3304 |
static inline uint32_t efsdiv(uint32_t op1, uint32_t op2)
|
|
3305 | 3305 |
{ |
3306 | 3306 |
CPU_FloatU u1, u2; |
3307 | 3307 |
u1.l = op1; |
... | ... | |
3340 | 3340 |
HELPER_SPE_VECTOR_ARITH(fsdiv); |
3341 | 3341 |
|
3342 | 3342 |
/* Single-precision floating-point comparisons */ |
3343 |
static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
|
|
3343 |
static inline uint32_t efststlt(uint32_t op1, uint32_t op2)
|
|
3344 | 3344 |
{ |
3345 | 3345 |
CPU_FloatU u1, u2; |
3346 | 3346 |
u1.l = op1; |
... | ... | |
3348 | 3348 |
return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0; |
3349 | 3349 |
} |
3350 | 3350 |
|
3351 |
static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
|
|
3351 |
static inline uint32_t efststgt(uint32_t op1, uint32_t op2)
|
|
3352 | 3352 |
{ |
3353 | 3353 |
CPU_FloatU u1, u2; |
3354 | 3354 |
u1.l = op1; |
... | ... | |
3356 | 3356 |
return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4; |
3357 | 3357 |
} |
3358 | 3358 |
|
3359 |
static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
|
|
3359 |
static inline uint32_t efststeq(uint32_t op1, uint32_t op2)
|
|
3360 | 3360 |
{ |
3361 | 3361 |
CPU_FloatU u1, u2; |
3362 | 3362 |
u1.l = op1; |
... | ... | |
3364 | 3364 |
return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0; |
3365 | 3365 |
} |
3366 | 3366 |
|
3367 |
static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
|
|
3367 |
static inline uint32_t efscmplt(uint32_t op1, uint32_t op2)
|
|
3368 | 3368 |
{ |
3369 | 3369 |
/* XXX: TODO: test special values (NaN, infinites, ...) */ |
3370 | 3370 |
return efststlt(op1, op2); |
3371 | 3371 |
} |
3372 | 3372 |
|
3373 |
static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
|
|
3373 |
static inline uint32_t efscmpgt(uint32_t op1, uint32_t op2)
|
|
3374 | 3374 |
{ |
3375 | 3375 |
/* XXX: TODO: test special values (NaN, infinites, ...) */ |
3376 | 3376 |
return efststgt(op1, op2); |
3377 | 3377 |
} |
3378 | 3378 |
|
3379 |
static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
|
|
3379 |
static inline uint32_t efscmpeq(uint32_t op1, uint32_t op2)
|
|
3380 | 3380 |
{ |
3381 | 3381 |
/* XXX: TODO: test special values (NaN, infinites, ...) */ |
3382 | 3382 |
return efststeq(op1, op2); |
... | ... | |
3400 | 3400 |
/* efscmpeq */ |
3401 | 3401 |
HELPER_SINGLE_SPE_CMP(fscmpeq); |
3402 | 3402 |
|
3403 |
static always_inline uint32_t evcmp_merge (int t0, int t1)
|
|
3403 |
static inline uint32_t evcmp_merge(int t0, int t1)
|
|
3404 | 3404 |
{ |
3405 | 3405 |
return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1); |
3406 | 3406 |
} |
... | ... | |
3850 | 3850 |
do_74xx_tlb(EPN, 1); |
3851 | 3851 |
} |
3852 | 3852 |
|
3853 |
static always_inline target_ulong booke_tlb_to_page_size (int size)
|
|
3853 |
static inline target_ulong booke_tlb_to_page_size(int size)
|
|
3854 | 3854 |
{ |
3855 | 3855 |
return 1024 << (2 * size); |
3856 | 3856 |
} |
3857 | 3857 |
|
3858 |
static always_inline int booke_page_size_to_tlb (target_ulong page_size)
|
|
3858 |
static inline int booke_page_size_to_tlb(target_ulong page_size)
|
|
3859 | 3859 |
{ |
3860 | 3860 |
int size; |
3861 | 3861 |
|
b/target-ppc/translate.c | ||
---|---|---|
210 | 210 |
#endif |
211 | 211 |
}; |
212 | 212 |
|
213 |
static always_inline void gen_reset_fpstatus (void)
|
|
213 |
static inline void gen_reset_fpstatus(void)
|
|
214 | 214 |
{ |
215 | 215 |
#ifdef CONFIG_SOFTFLOAT |
216 | 216 |
gen_helper_reset_fpstatus(); |
217 | 217 |
#endif |
218 | 218 |
} |
219 | 219 |
|
220 |
static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
|
|
220 |
static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
|
|
221 | 221 |
{ |
222 | 222 |
TCGv_i32 t0 = tcg_temp_new_i32(); |
223 | 223 |
|
... | ... | |
239 | 239 |
tcg_temp_free_i32(t0); |
240 | 240 |
} |
241 | 241 |
|
242 |
static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
|
|
242 |
static inline void gen_set_access_type(DisasContext *ctx, int access_type)
|
|
243 | 243 |
{ |
244 | 244 |
if (ctx->access_type != access_type) { |
245 | 245 |
tcg_gen_movi_i32(cpu_access_type, access_type); |
... | ... | |
247 | 247 |
} |
248 | 248 |
} |
249 | 249 |
|
250 |
static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
|
|
250 |
static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
|
|
251 | 251 |
{ |
252 | 252 |
#if defined(TARGET_PPC64) |
253 | 253 |
if (ctx->sf_mode) |
... | ... | |
257 | 257 |
tcg_gen_movi_tl(cpu_nip, (uint32_t)nip); |
258 | 258 |
} |
259 | 259 |
|
260 |
static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
|
|
260 |
static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
|
|
261 | 261 |
{ |
262 | 262 |
TCGv_i32 t0, t1; |
263 | 263 |
if (ctx->exception == POWERPC_EXCP_NONE) { |
... | ... | |
271 | 271 |
ctx->exception = (excp); |
272 | 272 |
} |
273 | 273 |
|
274 |
static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
|
|
274 |
static inline void gen_exception(DisasContext *ctx, uint32_t excp)
|
|
275 | 275 |
{ |
276 | 276 |
TCGv_i32 t0; |
277 | 277 |
if (ctx->exception == POWERPC_EXCP_NONE) { |
... | ... | |
283 | 283 |
ctx->exception = (excp); |
284 | 284 |
} |
285 | 285 |
|
286 |
static always_inline void gen_debug_exception (DisasContext *ctx)
|
|
286 |
static inline void gen_debug_exception(DisasContext *ctx)
|
|
287 | 287 |
{ |
288 | 288 |
TCGv_i32 t0; |
289 | 289 |
|
... | ... | |
294 | 294 |
tcg_temp_free_i32(t0); |
295 | 295 |
} |
296 | 296 |
|
297 |
static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
|
|
297 |
static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
|
|
298 | 298 |
{ |
299 | 299 |
gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error); |
300 | 300 |
} |
301 | 301 |
|
302 | 302 |
/* Stop translation */ |
303 |
static always_inline void gen_stop_exception (DisasContext *ctx)
|
|
303 |
static inline void gen_stop_exception(DisasContext *ctx)
|
|
304 | 304 |
{ |
305 | 305 |
gen_update_nip(ctx, ctx->nip); |
306 | 306 |
ctx->exception = POWERPC_EXCP_STOP; |
307 | 307 |
} |
308 | 308 |
|
309 | 309 |
/* No need to update nip here, as execution flow will change */ |
310 |
static always_inline void gen_sync_exception (DisasContext *ctx)
|
|
310 |
static inline void gen_sync_exception(DisasContext *ctx)
|
|
311 | 311 |
{ |
312 | 312 |
ctx->exception = POWERPC_EXCP_SYNC; |
313 | 313 |
} |
... | ... | |
332 | 332 |
/*****************************************************************************/ |
333 | 333 |
/*** Instruction decoding ***/ |
334 | 334 |
#define EXTRACT_HELPER(name, shift, nb) \ |
335 |
static always_inline uint32_t name (uint32_t opcode) \
|
|
335 |
static inline uint32_t name(uint32_t opcode) \
|
|
336 | 336 |
{ \ |
337 | 337 |
return (opcode >> (shift)) & ((1 << (nb)) - 1); \ |
338 | 338 |
} |
339 | 339 |
|
340 | 340 |
#define EXTRACT_SHELPER(name, shift, nb) \ |
341 |
static always_inline int32_t name (uint32_t opcode) \
|
|
341 |
static inline int32_t name(uint32_t opcode) \
|
|
342 | 342 |
{ \ |
343 | 343 |
return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
344 | 344 |
} |
... | ... | |
369 | 369 |
EXTRACT_HELPER(crbB, 11, 5); |
370 | 370 |
/* SPR / TBL */ |
371 | 371 |
EXTRACT_HELPER(_SPR, 11, 10); |
372 |
static always_inline uint32_t SPR (uint32_t opcode)
|
|
372 |
static inline uint32_t SPR(uint32_t opcode)
|
|
373 | 373 |
{ |
374 | 374 |
uint32_t sprn = _SPR(opcode); |
375 | 375 |
|
... | ... | |
407 | 407 |
/* Displacement */ |
408 | 408 |
EXTRACT_SHELPER(d, 0, 16); |
409 | 409 |
/* Immediate address */ |
410 |
static always_inline target_ulong LI (uint32_t opcode)
|
|
410 |
static inline target_ulong LI(uint32_t opcode)
|
|
411 | 411 |
{ |
412 | 412 |
return (opcode >> 0) & 0x03FFFFFC; |
413 | 413 |
} |
414 | 414 |
|
415 |
static always_inline uint32_t BD (uint32_t opcode)
|
|
415 |
static inline uint32_t BD(uint32_t opcode)
|
|
416 | 416 |
{ |
417 | 417 |
return (opcode >> 0) & 0xFFFC; |
418 | 418 |
} |
... | ... | |
425 | 425 |
EXTRACT_HELPER(LK, 0, 1); |
426 | 426 |
|
427 | 427 |
/* Create a mask between <start> and <end> bits */ |
428 |
static always_inline target_ulong MASK (uint32_t start, uint32_t end)
|
|
428 |
static inline target_ulong MASK(uint32_t start, uint32_t end)
|
|
429 | 429 |
{ |
430 | 430 |
target_ulong ret; |
431 | 431 |
|
... | ... | |
514 | 514 |
#endif |
515 | 515 |
|
516 | 516 |
/* SPR load/store helpers */ |
517 |
static always_inline void gen_load_spr(TCGv t, int reg)
|
|
517 |
static inline void gen_load_spr(TCGv t, int reg) |
|
518 | 518 |
{ |
519 | 519 |
tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg])); |
520 | 520 |
} |
521 | 521 |
|
522 |
static always_inline void gen_store_spr(int reg, TCGv t)
|
|
522 |
static inline void gen_store_spr(int reg, TCGv t) |
|
523 | 523 |
{ |
524 | 524 |
tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg])); |
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