Revision 636aa200 target-alpha/translate.c
| b/target-alpha/translate.c | ||
|---|---|---|
| 103 | 103 |
done_init = 1; |
| 104 | 104 |
} |
| 105 | 105 |
|
| 106 |
static always_inline void gen_excp (DisasContext *ctx, |
|
| 107 |
int exception, int error_code) |
|
| 106 |
static inline void gen_excp(DisasContext *ctx, int exception, int error_code) |
|
| 108 | 107 |
{
|
| 109 | 108 |
TCGv_i32 tmp1, tmp2; |
| 110 | 109 |
|
| ... | ... | |
| 116 | 115 |
tcg_temp_free_i32(tmp1); |
| 117 | 116 |
} |
| 118 | 117 |
|
| 119 |
static always_inline void gen_invalid (DisasContext *ctx)
|
|
| 118 |
static inline void gen_invalid(DisasContext *ctx)
|
|
| 120 | 119 |
{
|
| 121 | 120 |
gen_excp(ctx, EXCP_OPCDEC, 0); |
| 122 | 121 |
} |
| 123 | 122 |
|
| 124 |
static always_inline void gen_qemu_ldf (TCGv t0, TCGv t1, int flags)
|
|
| 123 |
static inline void gen_qemu_ldf(TCGv t0, TCGv t1, int flags)
|
|
| 125 | 124 |
{
|
| 126 | 125 |
TCGv tmp = tcg_temp_new(); |
| 127 | 126 |
TCGv_i32 tmp32 = tcg_temp_new_i32(); |
| ... | ... | |
| 132 | 131 |
tcg_temp_free(tmp); |
| 133 | 132 |
} |
| 134 | 133 |
|
| 135 |
static always_inline void gen_qemu_ldg (TCGv t0, TCGv t1, int flags)
|
|
| 134 |
static inline void gen_qemu_ldg(TCGv t0, TCGv t1, int flags)
|
|
| 136 | 135 |
{
|
| 137 | 136 |
TCGv tmp = tcg_temp_new(); |
| 138 | 137 |
tcg_gen_qemu_ld64(tmp, t1, flags); |
| ... | ... | |
| 140 | 139 |
tcg_temp_free(tmp); |
| 141 | 140 |
} |
| 142 | 141 |
|
| 143 |
static always_inline void gen_qemu_lds (TCGv t0, TCGv t1, int flags)
|
|
| 142 |
static inline void gen_qemu_lds(TCGv t0, TCGv t1, int flags)
|
|
| 144 | 143 |
{
|
| 145 | 144 |
TCGv tmp = tcg_temp_new(); |
| 146 | 145 |
TCGv_i32 tmp32 = tcg_temp_new_i32(); |
| ... | ... | |
| 151 | 150 |
tcg_temp_free(tmp); |
| 152 | 151 |
} |
| 153 | 152 |
|
| 154 |
static always_inline void gen_qemu_ldl_l (TCGv t0, TCGv t1, int flags)
|
|
| 153 |
static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags)
|
|
| 155 | 154 |
{
|
| 156 | 155 |
tcg_gen_mov_i64(cpu_lock, t1); |
| 157 | 156 |
tcg_gen_qemu_ld32s(t0, t1, flags); |
| 158 | 157 |
} |
| 159 | 158 |
|
| 160 |
static always_inline void gen_qemu_ldq_l (TCGv t0, TCGv t1, int flags)
|
|
| 159 |
static inline void gen_qemu_ldq_l(TCGv t0, TCGv t1, int flags)
|
|
| 161 | 160 |
{
|
| 162 | 161 |
tcg_gen_mov_i64(cpu_lock, t1); |
| 163 | 162 |
tcg_gen_qemu_ld64(t0, t1, flags); |
| 164 | 163 |
} |
| 165 | 164 |
|
| 166 |
static always_inline void gen_load_mem (DisasContext *ctx, |
|
| 167 |
void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1, int flags), |
|
| 168 |
int ra, int rb, int32_t disp16, |
|
| 169 |
int fp, int clear) |
|
| 165 |
static inline void gen_load_mem(DisasContext *ctx, |
|
| 166 |
void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1, |
|
| 167 |
int flags), |
|
| 168 |
int ra, int rb, int32_t disp16, int fp, |
|
| 169 |
int clear) |
|
| 170 | 170 |
{
|
| 171 | 171 |
TCGv addr; |
| 172 | 172 |
|
| ... | ... | |
| 190 | 190 |
tcg_temp_free(addr); |
| 191 | 191 |
} |
| 192 | 192 |
|
| 193 |
static always_inline void gen_qemu_stf (TCGv t0, TCGv t1, int flags)
|
|
| 193 |
static inline void gen_qemu_stf(TCGv t0, TCGv t1, int flags)
|
|
| 194 | 194 |
{
|
| 195 | 195 |
TCGv_i32 tmp32 = tcg_temp_new_i32(); |
| 196 | 196 |
TCGv tmp = tcg_temp_new(); |
| ... | ... | |
| 201 | 201 |
tcg_temp_free_i32(tmp32); |
| 202 | 202 |
} |
| 203 | 203 |
|
| 204 |
static always_inline void gen_qemu_stg (TCGv t0, TCGv t1, int flags)
|
|
| 204 |
static inline void gen_qemu_stg(TCGv t0, TCGv t1, int flags)
|
|
| 205 | 205 |
{
|
| 206 | 206 |
TCGv tmp = tcg_temp_new(); |
| 207 | 207 |
gen_helper_g_to_memory(tmp, t0); |
| ... | ... | |
| 209 | 209 |
tcg_temp_free(tmp); |
| 210 | 210 |
} |
| 211 | 211 |
|
| 212 |
static always_inline void gen_qemu_sts (TCGv t0, TCGv t1, int flags)
|
|
| 212 |
static inline void gen_qemu_sts(TCGv t0, TCGv t1, int flags)
|
|
| 213 | 213 |
{
|
| 214 | 214 |
TCGv_i32 tmp32 = tcg_temp_new_i32(); |
| 215 | 215 |
TCGv tmp = tcg_temp_new(); |
| ... | ... | |
| 220 | 220 |
tcg_temp_free_i32(tmp32); |
| 221 | 221 |
} |
| 222 | 222 |
|
| 223 |
static always_inline void gen_qemu_stl_c (TCGv t0, TCGv t1, int flags)
|
|
| 223 |
static inline void gen_qemu_stl_c(TCGv t0, TCGv t1, int flags)
|
|
| 224 | 224 |
{
|
| 225 | 225 |
int l1, l2; |
| 226 | 226 |
|
| ... | ... | |
| 236 | 236 |
tcg_gen_movi_i64(cpu_lock, -1); |
| 237 | 237 |
} |
| 238 | 238 |
|
| 239 |
static always_inline void gen_qemu_stq_c (TCGv t0, TCGv t1, int flags)
|
|
| 239 |
static inline void gen_qemu_stq_c(TCGv t0, TCGv t1, int flags)
|
|
| 240 | 240 |
{
|
| 241 | 241 |
int l1, l2; |
| 242 | 242 |
|
| ... | ... | |
| 252 | 252 |
tcg_gen_movi_i64(cpu_lock, -1); |
| 253 | 253 |
} |
| 254 | 254 |
|
| 255 |
static always_inline void gen_store_mem (DisasContext *ctx, |
|
| 256 |
void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, int flags), |
|
| 257 |
int ra, int rb, int32_t disp16, |
|
| 258 |
int fp, int clear, int local) |
|
| 255 |
static inline void gen_store_mem(DisasContext *ctx, |
|
| 256 |
void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, |
|
| 257 |
int flags), |
|
| 258 |
int ra, int rb, int32_t disp16, int fp, |
|
| 259 |
int clear, int local) |
|
| 259 | 260 |
{
|
| 260 | 261 |
TCGv addr; |
| 261 | 262 |
if (local) |
| ... | ... | |
| 288 | 289 |
tcg_temp_free(addr); |
| 289 | 290 |
} |
| 290 | 291 |
|
| 291 |
static always_inline void gen_bcond (DisasContext *ctx, |
|
| 292 |
TCGCond cond, |
|
| 293 |
int ra, int32_t disp, int mask) |
|
| 292 |
static inline void gen_bcond(DisasContext *ctx, TCGCond cond, int ra, |
|
| 293 |
int32_t disp, int mask) |
|
| 294 | 294 |
{
|
| 295 | 295 |
int l1, l2; |
| 296 | 296 |
|
| ... | ... | |
| 317 | 317 |
gen_set_label(l2); |
| 318 | 318 |
} |
| 319 | 319 |
|
| 320 |
static always_inline void gen_fbcond (DisasContext *ctx, int opc,
|
|
| 321 |
int ra, int32_t disp16)
|
|
| 320 |
static inline void gen_fbcond(DisasContext *ctx, int opc, int ra,
|
|
| 321 |
int32_t disp16) |
|
| 322 | 322 |
{
|
| 323 | 323 |
int l1, l2; |
| 324 | 324 |
TCGv tmp; |
| ... | ... | |
| 363 | 363 |
gen_set_label(l2); |
| 364 | 364 |
} |
| 365 | 365 |
|
| 366 |
static always_inline void gen_cmov (TCGCond inv_cond, |
|
| 367 |
int ra, int rb, int rc, |
|
| 368 |
int islit, uint8_t lit, int mask) |
|
| 366 |
static inline void gen_cmov(TCGCond inv_cond, int ra, int rb, int rc, |
|
| 367 |
int islit, uint8_t lit, int mask) |
|
| 369 | 368 |
{
|
| 370 | 369 |
int l1; |
| 371 | 370 |
|
| ... | ... | |
| 397 | 396 |
} |
| 398 | 397 |
|
| 399 | 398 |
#define FARITH2(name) \ |
| 400 |
static always_inline void glue(gen_f, name)(int rb, int rc) \
|
|
| 399 |
static inline void glue(gen_f, name)(int rb, int rc) \
|
|
| 401 | 400 |
{ \
|
| 402 | 401 |
if (unlikely(rc == 31)) \ |
| 403 | 402 |
return; \ |
| ... | ... | |
| 429 | 428 |
FARITH2(cvtqlsv) |
| 430 | 429 |
|
| 431 | 430 |
#define FARITH3(name) \ |
| 432 |
static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \
|
|
| 431 |
static inline void glue(gen_f, name)(int ra, int rb, int rc) \
|
|
| 433 | 432 |
{ \
|
| 434 | 433 |
if (unlikely(rc == 31)) \ |
| 435 | 434 |
return; \ |
| ... | ... | |
| 480 | 479 |
FARITH3(cpyse) |
| 481 | 480 |
|
| 482 | 481 |
#define FCMOV(name) \ |
| 483 |
static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \
|
|
| 482 |
static inline void glue(gen_f, name)(int ra, int rb, int rc) \
|
|
| 484 | 483 |
{ \
|
| 485 | 484 |
int l1; \ |
| 486 | 485 |
TCGv tmp; \ |
| ... | ... | |
| 512 | 511 |
FCMOV(cmpfgt) |
| 513 | 512 |
|
| 514 | 513 |
/* EXTWH, EXTWH, EXTLH, EXTQH */ |
| 515 |
static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), |
|
| 516 |
int ra, int rb, int rc, |
|
| 517 |
int islit, uint8_t lit) |
|
| 514 |
static inline void gen_ext_h(void(*tcg_gen_ext_i64)(TCGv t0, TCGv t1), |
|
| 515 |
int ra, int rb, int rc, int islit, uint8_t lit) |
|
| 518 | 516 |
{
|
| 519 | 517 |
if (unlikely(rc == 31)) |
| 520 | 518 |
return; |
| ... | ... | |
| 543 | 541 |
} |
| 544 | 542 |
|
| 545 | 543 |
/* EXTBL, EXTWL, EXTWL, EXTLL, EXTQL */ |
| 546 |
static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), |
|
| 547 |
int ra, int rb, int rc, |
|
| 548 |
int islit, uint8_t lit) |
|
| 544 |
static inline void gen_ext_l(void(*tcg_gen_ext_i64)(TCGv t0, TCGv t1), |
|
| 545 |
int ra, int rb, int rc, int islit, uint8_t lit) |
|
| 549 | 546 |
{
|
| 550 | 547 |
if (unlikely(rc == 31)) |
| 551 | 548 |
return; |
| ... | ... | |
| 568 | 565 |
|
| 569 | 566 |
/* Code to call arith3 helpers */ |
| 570 | 567 |
#define ARITH3(name) \ |
| 571 |
static always_inline void glue(gen_, name) (int ra, int rb, int rc, \
|
|
| 572 |
int islit, uint8_t lit) \
|
|
| 568 |
static inline void glue(gen_, name)(int ra, int rb, int rc, int islit,\
|
|
| 569 |
uint8_t lit) \
|
|
| 573 | 570 |
{ \
|
| 574 | 571 |
if (unlikely(rc == 31)) \ |
| 575 | 572 |
return; \ |
| ... | ... | |
| 617 | 614 |
ARITH3(mullv) |
| 618 | 615 |
ARITH3(mulqv) |
| 619 | 616 |
|
| 620 |
static always_inline void gen_cmp(TCGCond cond, |
|
| 621 |
int ra, int rb, int rc, |
|
| 622 |
int islit, uint8_t lit) |
|
| 617 |
static inline void gen_cmp(TCGCond cond, int ra, int rb, int rc, int islit, |
|
| 618 |
uint8_t lit) |
|
| 623 | 619 |
{
|
| 624 | 620 |
int l1, l2; |
| 625 | 621 |
TCGv tmp; |
| ... | ... | |
| 647 | 643 |
gen_set_label(l2); |
| 648 | 644 |
} |
| 649 | 645 |
|
| 650 |
static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
|
|
| 646 |
static inline int translate_one(DisasContext *ctx, uint32_t insn)
|
|
| 651 | 647 |
{
|
| 652 | 648 |
uint32_t palcode; |
| 653 | 649 |
int32_t disp21, disp16, disp12; |
| ... | ... | |
| 2336 | 2332 |
return ret; |
| 2337 | 2333 |
} |
| 2338 | 2334 |
|
| 2339 |
static always_inline void gen_intermediate_code_internal (CPUState *env,
|
|
| 2340 |
TranslationBlock *tb,
|
|
| 2341 |
int search_pc)
|
|
| 2335 |
static inline void gen_intermediate_code_internal(CPUState *env,
|
|
| 2336 |
TranslationBlock *tb, |
|
| 2337 |
int search_pc) |
|
| 2342 | 2338 |
{
|
| 2343 | 2339 |
#if defined ALPHA_DEBUG_DISAS |
| 2344 | 2340 |
static int insn_count; |
Also available in: Unified diff