Revision 636aa200 target-ppc/translate.c
b/target-ppc/translate.c | ||
---|---|---|
210 | 210 |
#endif |
211 | 211 |
}; |
212 | 212 |
|
213 |
static always_inline void gen_reset_fpstatus (void)
|
|
213 |
static inline void gen_reset_fpstatus(void)
|
|
214 | 214 |
{ |
215 | 215 |
#ifdef CONFIG_SOFTFLOAT |
216 | 216 |
gen_helper_reset_fpstatus(); |
217 | 217 |
#endif |
218 | 218 |
} |
219 | 219 |
|
220 |
static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
|
|
220 |
static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
|
|
221 | 221 |
{ |
222 | 222 |
TCGv_i32 t0 = tcg_temp_new_i32(); |
223 | 223 |
|
... | ... | |
239 | 239 |
tcg_temp_free_i32(t0); |
240 | 240 |
} |
241 | 241 |
|
242 |
static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
|
|
242 |
static inline void gen_set_access_type(DisasContext *ctx, int access_type)
|
|
243 | 243 |
{ |
244 | 244 |
if (ctx->access_type != access_type) { |
245 | 245 |
tcg_gen_movi_i32(cpu_access_type, access_type); |
... | ... | |
247 | 247 |
} |
248 | 248 |
} |
249 | 249 |
|
250 |
static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
|
|
250 |
static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
|
|
251 | 251 |
{ |
252 | 252 |
#if defined(TARGET_PPC64) |
253 | 253 |
if (ctx->sf_mode) |
... | ... | |
257 | 257 |
tcg_gen_movi_tl(cpu_nip, (uint32_t)nip); |
258 | 258 |
} |
259 | 259 |
|
260 |
static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
|
|
260 |
static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
|
|
261 | 261 |
{ |
262 | 262 |
TCGv_i32 t0, t1; |
263 | 263 |
if (ctx->exception == POWERPC_EXCP_NONE) { |
... | ... | |
271 | 271 |
ctx->exception = (excp); |
272 | 272 |
} |
273 | 273 |
|
274 |
static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
|
|
274 |
static inline void gen_exception(DisasContext *ctx, uint32_t excp)
|
|
275 | 275 |
{ |
276 | 276 |
TCGv_i32 t0; |
277 | 277 |
if (ctx->exception == POWERPC_EXCP_NONE) { |
... | ... | |
283 | 283 |
ctx->exception = (excp); |
284 | 284 |
} |
285 | 285 |
|
286 |
static always_inline void gen_debug_exception (DisasContext *ctx)
|
|
286 |
static inline void gen_debug_exception(DisasContext *ctx)
|
|
287 | 287 |
{ |
288 | 288 |
TCGv_i32 t0; |
289 | 289 |
|
... | ... | |
294 | 294 |
tcg_temp_free_i32(t0); |
295 | 295 |
} |
296 | 296 |
|
297 |
static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
|
|
297 |
static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
|
|
298 | 298 |
{ |
299 | 299 |
gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error); |
300 | 300 |
} |
301 | 301 |
|
302 | 302 |
/* Stop translation */ |
303 |
static always_inline void gen_stop_exception (DisasContext *ctx)
|
|
303 |
static inline void gen_stop_exception(DisasContext *ctx)
|
|
304 | 304 |
{ |
305 | 305 |
gen_update_nip(ctx, ctx->nip); |
306 | 306 |
ctx->exception = POWERPC_EXCP_STOP; |
307 | 307 |
} |
308 | 308 |
|
309 | 309 |
/* No need to update nip here, as execution flow will change */ |
310 |
static always_inline void gen_sync_exception (DisasContext *ctx)
|
|
310 |
static inline void gen_sync_exception(DisasContext *ctx)
|
|
311 | 311 |
{ |
312 | 312 |
ctx->exception = POWERPC_EXCP_SYNC; |
313 | 313 |
} |
... | ... | |
332 | 332 |
/*****************************************************************************/ |
333 | 333 |
/*** Instruction decoding ***/ |
334 | 334 |
#define EXTRACT_HELPER(name, shift, nb) \ |
335 |
static always_inline uint32_t name (uint32_t opcode) \
|
|
335 |
static inline uint32_t name(uint32_t opcode) \
|
|
336 | 336 |
{ \ |
337 | 337 |
return (opcode >> (shift)) & ((1 << (nb)) - 1); \ |
338 | 338 |
} |
339 | 339 |
|
340 | 340 |
#define EXTRACT_SHELPER(name, shift, nb) \ |
341 |
static always_inline int32_t name (uint32_t opcode) \
|
|
341 |
static inline int32_t name(uint32_t opcode) \
|
|
342 | 342 |
{ \ |
343 | 343 |
return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
344 | 344 |
} |
... | ... | |
369 | 369 |
EXTRACT_HELPER(crbB, 11, 5); |
370 | 370 |
/* SPR / TBL */ |
371 | 371 |
EXTRACT_HELPER(_SPR, 11, 10); |
372 |
static always_inline uint32_t SPR (uint32_t opcode)
|
|
372 |
static inline uint32_t SPR(uint32_t opcode)
|
|
373 | 373 |
{ |
374 | 374 |
uint32_t sprn = _SPR(opcode); |
375 | 375 |
|
... | ... | |
407 | 407 |
/* Displacement */ |
408 | 408 |
EXTRACT_SHELPER(d, 0, 16); |
409 | 409 |
/* Immediate address */ |
410 |
static always_inline target_ulong LI (uint32_t opcode)
|
|
410 |
static inline target_ulong LI(uint32_t opcode)
|
|
411 | 411 |
{ |
412 | 412 |
return (opcode >> 0) & 0x03FFFFFC; |
413 | 413 |
} |
414 | 414 |
|
415 |
static always_inline uint32_t BD (uint32_t opcode)
|
|
415 |
static inline uint32_t BD(uint32_t opcode)
|
|
416 | 416 |
{ |
417 | 417 |
return (opcode >> 0) & 0xFFFC; |
418 | 418 |
} |
... | ... | |
425 | 425 |
EXTRACT_HELPER(LK, 0, 1); |
426 | 426 |
|
427 | 427 |
/* Create a mask between <start> and <end> bits */ |
428 |
static always_inline target_ulong MASK (uint32_t start, uint32_t end)
|
|
428 |
static inline target_ulong MASK(uint32_t start, uint32_t end)
|
|
429 | 429 |
{ |
430 | 430 |
target_ulong ret; |
431 | 431 |
|
... | ... | |
514 | 514 |
#endif |
515 | 515 |
|
516 | 516 |
/* SPR load/store helpers */ |
517 |
static always_inline void gen_load_spr(TCGv t, int reg)
|
|
517 |
static inline void gen_load_spr(TCGv t, int reg) |
|
518 | 518 |
{ |
519 | 519 |
tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg])); |
520 | 520 |
} |
521 | 521 |
|
522 |
static always_inline void gen_store_spr(int reg, TCGv t)
|
|
522 |
static inline void gen_store_spr(int reg, TCGv t) |
|
523 | 523 |
{ |
524 | 524 |
tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg])); |
525 | 525 |
} |
... | ... | |
538 | 538 |
|
539 | 539 |
/*** Integer comparison ***/ |
540 | 540 |
|
541 |
static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
|
|
541 |
static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
|
542 | 542 |
{ |
543 | 543 |
int l1, l2, l3; |
544 | 544 |
|
... | ... | |
566 | 566 |
gen_set_label(l3); |
567 | 567 |
} |
568 | 568 |
|
569 |
static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
|
|
569 |
static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
|
570 | 570 |
{ |
571 | 571 |
TCGv t0 = tcg_const_local_tl(arg1); |
572 | 572 |
gen_op_cmp(arg0, t0, s, crf); |
... | ... | |
574 | 574 |
} |
575 | 575 |
|
576 | 576 |
#if defined(TARGET_PPC64) |
577 |
static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
|
|
577 |
static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
|
578 | 578 |
{ |
579 | 579 |
TCGv t0, t1; |
580 | 580 |
t0 = tcg_temp_local_new(); |
... | ... | |
591 | 591 |
tcg_temp_free(t0); |
592 | 592 |
} |
593 | 593 |
|
594 |
static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
|
|
594 |
static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
|
595 | 595 |
{ |
596 | 596 |
TCGv t0 = tcg_const_local_tl(arg1); |
597 | 597 |
gen_op_cmp32(arg0, t0, s, crf); |
... | ... | |
599 | 599 |
} |
600 | 600 |
#endif |
601 | 601 |
|
602 |
static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
|
|
602 |
static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
|
|
603 | 603 |
{ |
604 | 604 |
#if defined(TARGET_PPC64) |
605 | 605 |
if (!(ctx->sf_mode)) |
... | ... | |
689 | 689 |
|
690 | 690 |
/*** Integer arithmetic ***/ |
691 | 691 |
|
692 |
static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub) |
|
692 |
static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
|
693 |
TCGv arg1, TCGv arg2, int sub) |
|
693 | 694 |
{ |
694 | 695 |
int l1; |
695 | 696 |
TCGv t0; |
... | ... | |
721 | 722 |
tcg_temp_free(t0); |
722 | 723 |
} |
723 | 724 |
|
724 |
static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub) |
|
725 |
static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, |
|
726 |
TCGv arg2, int sub) |
|
725 | 727 |
{ |
726 | 728 |
int l1 = gen_new_label(); |
727 | 729 |
|
... | ... | |
756 | 758 |
} |
757 | 759 |
|
758 | 760 |
/* Common add function */ |
759 |
static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, |
|
760 |
int add_ca, int compute_ca, int compute_ov) |
|
761 |
static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
|
762 |
TCGv arg2, int add_ca, int compute_ca, |
|
763 |
int compute_ov) |
|
761 | 764 |
{ |
762 | 765 |
TCGv t0, t1; |
763 | 766 |
|
... | ... | |
857 | 860 |
} |
858 | 861 |
} |
859 | 862 |
/* addic addic.*/ |
860 |
static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
|
|
861 |
int compute_Rc0)
|
|
863 |
static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1,
|
|
864 |
int compute_Rc0) |
|
862 | 865 |
{ |
863 | 866 |
target_long simm = SIMM(ctx->opcode); |
864 | 867 |
|
... | ... | |
902 | 905 |
} |
903 | 906 |
} |
904 | 907 |
|
905 |
static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
|
|
906 |
int sign, int compute_ov)
|
|
908 |
static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
|
|
909 |
TCGv arg2, int sign, int compute_ov)
|
|
907 | 910 |
{ |
908 | 911 |
int l1 = gen_new_label(); |
909 | 912 |
int l2 = gen_new_label(); |
... | ... | |
957 | 960 |
GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); |
958 | 961 |
GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); |
959 | 962 |
#if defined(TARGET_PPC64) |
960 |
static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
|
|
961 |
int sign, int compute_ov)
|
|
963 |
static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
|
|
964 |
TCGv arg2, int sign, int compute_ov)
|
|
962 | 965 |
{ |
963 | 966 |
int l1 = gen_new_label(); |
964 | 967 |
int l2 = gen_new_label(); |
... | ... | |
1133 | 1136 |
#endif |
1134 | 1137 |
|
1135 | 1138 |
/* neg neg. nego nego. */ |
1136 |
static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check) |
|
1139 |
static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1, |
|
1140 |
int ov_check) |
|
1137 | 1141 |
{ |
1138 | 1142 |
int l1 = gen_new_label(); |
1139 | 1143 |
int l2 = gen_new_label(); |
... | ... | |
1175 | 1179 |
} |
1176 | 1180 |
|
1177 | 1181 |
/* Common subf function */ |
1178 |
static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, |
|
1179 |
int add_ca, int compute_ca, int compute_ov) |
|
1182 |
static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
|
1183 |
TCGv arg2, int add_ca, int compute_ca, |
|
1184 |
int compute_ov) |
|
1180 | 1185 |
{ |
1181 | 1186 |
TCGv t0, t1; |
1182 | 1187 |
|
... | ... | |
1658 | 1663 |
gen_##name(ctx, 1, 1); \ |
1659 | 1664 |
} |
1660 | 1665 |
|
1661 |
static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
|
|
1662 |
uint32_t me, uint32_t sh)
|
|
1666 |
static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
|
|
1667 |
uint32_t sh) |
|
1663 | 1668 |
{ |
1664 | 1669 |
if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { |
1665 | 1670 |
tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
... | ... | |
1679 | 1684 |
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1680 | 1685 |
} |
1681 | 1686 |
/* rldicl - rldicl. */ |
1682 |
static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
|
|
1687 |
static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
|
|
1683 | 1688 |
{ |
1684 | 1689 |
uint32_t sh, mb; |
1685 | 1690 |
|
... | ... | |
1689 | 1694 |
} |
1690 | 1695 |
GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
1691 | 1696 |
/* rldicr - rldicr. */ |
1692 |
static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
|
|
1697 |
static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
|
|
1693 | 1698 |
{ |
1694 | 1699 |
uint32_t sh, me; |
1695 | 1700 |
|
... | ... | |
1699 | 1704 |
} |
1700 | 1705 |
GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
1701 | 1706 |
/* rldic - rldic. */ |
1702 |
static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
|
|
1707 |
static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
|
|
1703 | 1708 |
{ |
1704 | 1709 |
uint32_t sh, mb; |
1705 | 1710 |
|
... | ... | |
1709 | 1714 |
} |
1710 | 1715 |
GEN_PPC64_R4(rldic, 0x1E, 0x04); |
1711 | 1716 |
|
1712 |
static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb, |
|
1713 |
uint32_t me) |
|
1717 |
static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me) |
|
1714 | 1718 |
{ |
1715 | 1719 |
TCGv t0; |
1716 | 1720 |
|
... | ... | |
1730 | 1734 |
} |
1731 | 1735 |
|
1732 | 1736 |
/* rldcl - rldcl. */ |
1733 |
static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
|
|
1737 |
static inline void gen_rldcl(DisasContext *ctx, int mbn)
|
|
1734 | 1738 |
{ |
1735 | 1739 |
uint32_t mb; |
1736 | 1740 |
|
... | ... | |
1739 | 1743 |
} |
1740 | 1744 |
GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
1741 | 1745 |
/* rldcr - rldcr. */ |
1742 |
static always_inline void gen_rldcr (DisasContext *ctx, int men)
|
|
1746 |
static inline void gen_rldcr(DisasContext *ctx, int men)
|
|
1743 | 1747 |
{ |
1744 | 1748 |
uint32_t me; |
1745 | 1749 |
|
... | ... | |
1748 | 1752 |
} |
1749 | 1753 |
GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
1750 | 1754 |
/* rldimi - rldimi. */ |
1751 |
static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
|
|
1755 |
static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
|
|
1752 | 1756 |
{ |
1753 | 1757 |
uint32_t sh, mb, me; |
1754 | 1758 |
|
... | ... | |
1895 | 1899 |
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1896 | 1900 |
} |
1897 | 1901 |
/* sradi & sradi. */ |
1898 |
static always_inline void gen_sradi (DisasContext *ctx, int n)
|
|
1902 |
static inline void gen_sradi(DisasContext *ctx, int n)
|
|
1899 | 1903 |
{ |
1900 | 1904 |
int sh = SH(ctx->opcode) + (n << 5); |
1901 | 1905 |
if (sh != 0) { |
... | ... | |
2348 | 2352 |
|
2349 | 2353 |
/*** Addressing modes ***/ |
2350 | 2354 |
/* Register indirect with immediate index : EA = (rA|0) + SIMM */ |
2351 |
static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl) |
|
2355 |
static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
|
2356 |
target_long maskl) |
|
2352 | 2357 |
{ |
2353 | 2358 |
target_long simm = SIMM(ctx->opcode); |
2354 | 2359 |
|
... | ... | |
2377 | 2382 |
} |
2378 | 2383 |
} |
2379 | 2384 |
|
2380 |
static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
|
|
2385 |
static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
|
|
2381 | 2386 |
{ |
2382 | 2387 |
if (rA(ctx->opcode) == 0) { |
2383 | 2388 |
#if defined(TARGET_PPC64) |
... | ... | |
2396 | 2401 |
} |
2397 | 2402 |
} |
2398 | 2403 |
|
2399 |
static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
|
|
2404 |
static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
|
|
2400 | 2405 |
{ |
2401 | 2406 |
if (rA(ctx->opcode) == 0) { |
2402 | 2407 |
tcg_gen_movi_tl(EA, 0); |
... | ... | |
2410 | 2415 |
} |
2411 | 2416 |
} |
2412 | 2417 |
|
2413 |
static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val) |
|
2418 |
static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
|
2419 |
target_long val) |
|
2414 | 2420 |
{ |
2415 | 2421 |
tcg_gen_addi_tl(ret, arg1, val); |
2416 | 2422 |
#if defined(TARGET_PPC64) |
... | ... | |
2420 | 2426 |
#endif |
2421 | 2427 |
} |
2422 | 2428 |
|
2423 |
static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
|
|
2429 |
static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
|
|
2424 | 2430 |
{ |
2425 | 2431 |
int l1 = gen_new_label(); |
2426 | 2432 |
TCGv t0 = tcg_temp_new(); |
... | ... | |
2439 | 2445 |
} |
2440 | 2446 |
|
2441 | 2447 |
/*** Integer load ***/ |
2442 |
static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
|
|
2448 |
static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
|
2443 | 2449 |
{ |
2444 | 2450 |
tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx); |
2445 | 2451 |
} |
2446 | 2452 |
|
2447 |
static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
|
|
2453 |
static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
|
2448 | 2454 |
{ |
2449 | 2455 |
tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx); |
2450 | 2456 |
} |
2451 | 2457 |
|
2452 |
static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
|
|
2458 |
static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
|
2453 | 2459 |
{ |
2454 | 2460 |
tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2455 | 2461 |
if (unlikely(ctx->le_mode)) { |
... | ... | |
2457 | 2463 |
} |
2458 | 2464 |
} |
2459 | 2465 |
|
2460 |
static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
|
|
2466 |
static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
|
2461 | 2467 |
{ |
2462 | 2468 |
if (unlikely(ctx->le_mode)) { |
2463 | 2469 |
tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
... | ... | |
2468 | 2474 |
} |
2469 | 2475 |
} |
2470 | 2476 |
|
2471 |
static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
|
|
2477 |
static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
|
2472 | 2478 |
{ |
2473 | 2479 |
tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2474 | 2480 |
if (unlikely(ctx->le_mode)) { |
... | ... | |
2477 | 2483 |
} |
2478 | 2484 |
|
2479 | 2485 |
#if defined(TARGET_PPC64) |
2480 |
static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
|
|
2486 |
static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
|
2481 | 2487 |
{ |
2482 | 2488 |
if (unlikely(ctx->le_mode)) { |
2483 | 2489 |
tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
... | ... | |
2488 | 2494 |
} |
2489 | 2495 |
#endif |
2490 | 2496 |
|
2491 |
static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
|
|
2497 |
static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
|
2492 | 2498 |
{ |
2493 | 2499 |
tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); |
2494 | 2500 |
if (unlikely(ctx->le_mode)) { |
... | ... | |
2496 | 2502 |
} |
2497 | 2503 |
} |
2498 | 2504 |
|
2499 |
static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
|
|
2505 |
static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2) |
|
2500 | 2506 |
{ |
2501 | 2507 |
tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx); |
2502 | 2508 |
} |
2503 | 2509 |
|
2504 |
static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
|
|
2510 |
static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) |
|
2505 | 2511 |
{ |
2506 | 2512 |
if (unlikely(ctx->le_mode)) { |
2507 | 2513 |
TCGv t0 = tcg_temp_new(); |
... | ... | |
2514 | 2520 |
} |
2515 | 2521 |
} |
2516 | 2522 |
|
2517 |
static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
|
|
2523 |
static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) |
|
2518 | 2524 |
{ |
2519 | 2525 |
if (unlikely(ctx->le_mode)) { |
2520 | 2526 |
TCGv t0 = tcg_temp_new(); |
... | ... | |
2527 | 2533 |
} |
2528 | 2534 |
} |
2529 | 2535 |
|
2530 |
static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
|
|
2536 |
static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
|
2531 | 2537 |
{ |
2532 | 2538 |
if (unlikely(ctx->le_mode)) { |
2533 | 2539 |
TCGv_i64 t0 = tcg_temp_new_i64(); |
... | ... | |
2808 | 2814 |
#endif |
2809 | 2815 |
/*** Integer load and store with byte reverse ***/ |
2810 | 2816 |
/* lhbrx */ |
2811 |
static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
|
|
2817 |
static void inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
|
2812 | 2818 |
{ |
2813 | 2819 |
tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2814 | 2820 |
if (likely(!ctx->le_mode)) { |
... | ... | |
2818 | 2824 |
GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
2819 | 2825 |
|
2820 | 2826 |
/* lwbrx */ |
2821 |
static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
|
|
2827 |
static void inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
|
2822 | 2828 |
{ |
2823 | 2829 |
tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2824 | 2830 |
if (likely(!ctx->le_mode)) { |
... | ... | |
2828 | 2834 |
GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
2829 | 2835 |
|
2830 | 2836 |
/* sthbrx */ |
2831 |
static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
|
|
2837 |
static void inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
|
2832 | 2838 |
{ |
2833 | 2839 |
if (likely(!ctx->le_mode)) { |
2834 | 2840 |
TCGv t0 = tcg_temp_new(); |
... | ... | |
2843 | 2849 |
GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
2844 | 2850 |
|
2845 | 2851 |
/* stwbrx */ |
2846 |
static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
|
|
2852 |
static void inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
|
2847 | 2853 |
{ |
2848 | 2854 |
if (likely(!ctx->le_mode)) { |
2849 | 2855 |
TCGv t0 = tcg_temp_new(); |
... | ... | |
3200 | 3206 |
GEN_LDUXF(name, ldop, op | 0x01, type); \ |
3201 | 3207 |
GEN_LDXF(name, ldop, 0x17, op | 0x00, type) |
3202 | 3208 |
|
3203 |
static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
|
|
3209 |
static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
|
3204 | 3210 |
{ |
3205 | 3211 |
TCGv t0 = tcg_temp_new(); |
3206 | 3212 |
TCGv_i32 t1 = tcg_temp_new_i32(); |
... | ... | |
3293 | 3299 |
GEN_STUXF(name, stop, op | 0x01, type); \ |
3294 | 3300 |
GEN_STXF(name, stop, 0x17, op | 0x00, type) |
3295 | 3301 |
|
3296 |
static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
|
|
3302 |
static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
|
3297 | 3303 |
{ |
3298 | 3304 |
TCGv_i32 t0 = tcg_temp_new_i32(); |
3299 | 3305 |
TCGv t1 = tcg_temp_new(); |
... | ... | |
3310 | 3316 |
GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT); |
3311 | 3317 |
|
3312 | 3318 |
/* Optional: */ |
3313 |
static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
|
|
3319 |
static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
|
3314 | 3320 |
{ |
3315 | 3321 |
TCGv t0 = tcg_temp_new(); |
3316 | 3322 |
tcg_gen_trunc_i64_tl(t0, arg1), |
... | ... | |
3321 | 3327 |
GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); |
3322 | 3328 |
|
3323 | 3329 |
/*** Branch ***/ |
3324 |
static always_inline void gen_goto_tb (DisasContext *ctx, int n, |
|
3325 |
target_ulong dest) |
|
3330 |
static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
|
3326 | 3331 |
{ |
3327 | 3332 |
TranslationBlock *tb; |
3328 | 3333 |
tb = ctx->tb; |
... | ... | |
3354 | 3359 |
} |
3355 | 3360 |
} |
3356 | 3361 |
|
3357 |
static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
|
|
3362 |
static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
|
|
3358 | 3363 |
{ |
3359 | 3364 |
#if defined(TARGET_PPC64) |
3360 | 3365 |
if (ctx->sf_mode == 0) |
... | ... | |
3390 | 3395 |
#define BCOND_LR 1 |
3391 | 3396 |
#define BCOND_CTR 2 |
3392 | 3397 |
|
3393 |
static always_inline void gen_bcond (DisasContext *ctx, int type)
|
|
3398 |
static inline void gen_bcond(DisasContext *ctx, int type)
|
|
3394 | 3399 |
{ |
3395 | 3400 |
uint32_t bo = BO(ctx->opcode); |
3396 | 3401 |
int l1 = gen_new_label(); |
... | ... | |
3726 | 3731 |
#endif |
3727 | 3732 |
|
3728 | 3733 |
/* mfspr */ |
3729 |
static always_inline void gen_op_mfspr (DisasContext *ctx)
|
|
3734 |
static inline void gen_op_mfspr(DisasContext *ctx)
|
|
3730 | 3735 |
{ |
3731 | 3736 |
void (*read_cb)(void *opaque, int gprn, int sprn); |
3732 | 3737 |
uint32_t sprn = SPR(ctx->opcode); |
... | ... | |
5333 | 5338 |
} |
5334 | 5339 |
|
5335 | 5340 |
/* All 405 MAC instructions are translated here */ |
5336 |
static always_inline void gen_405_mulladd_insn (DisasContext *ctx, |
|
5337 |
int opc2, int opc3, |
|
5338 |
int ra, int rb, int rt, int Rc) |
|
5341 |
static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
|
5342 |
int ra, int rb, int rt, int Rc) |
|
5339 | 5343 |
{ |
5340 | 5344 |
TCGv t0, t1; |
5341 | 5345 |
|
... | ... | |
6015 | 6019 |
/*** Altivec vector extension ***/ |
6016 | 6020 |
/* Altivec registers moves */ |
6017 | 6021 |
|
6018 |
static always_inline TCGv_ptr gen_avr_ptr(int reg)
|
|
6022 |
static inline TCGv_ptr gen_avr_ptr(int reg) |
|
6019 | 6023 |
{ |
6020 | 6024 |
TCGv_ptr r = tcg_temp_new_ptr(); |
6021 | 6025 |
tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); |
... | ... | |
6499 | 6503 |
/*** SPE extension ***/ |
6500 | 6504 |
/* Register moves */ |
6501 | 6505 |
|
6502 |
static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) { |
|
6506 |
static inline void gen_load_gpr64(TCGv_i64 t, int reg) |
|
6507 |
{ |
|
6503 | 6508 |
#if defined(TARGET_PPC64) |
6504 | 6509 |
tcg_gen_mov_i64(t, cpu_gpr[reg]); |
6505 | 6510 |
#else |
... | ... | |
6507 | 6512 |
#endif |
6508 | 6513 |
} |
6509 | 6514 |
|
6510 |
static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) { |
|
6515 |
static inline void gen_store_gpr64(int reg, TCGv_i64 t) |
|
6516 |
{ |
|
6511 | 6517 |
#if defined(TARGET_PPC64) |
6512 | 6518 |
tcg_gen_mov_i64(cpu_gpr[reg], t); |
6513 | 6519 |
#else |
... | ... | |
6529 | 6535 |
} |
6530 | 6536 |
|
6531 | 6537 |
/* Handler for undefined SPE opcodes */ |
6532 |
static always_inline void gen_speundef (DisasContext *ctx)
|
|
6538 |
static inline void gen_speundef(DisasContext *ctx)
|
|
6533 | 6539 |
{ |
6534 | 6540 |
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
6535 | 6541 |
} |
... | ... | |
6537 | 6543 |
/* SPE logic */ |
6538 | 6544 |
#if defined(TARGET_PPC64) |
6539 | 6545 |
#define GEN_SPEOP_LOGIC2(name, tcg_op) \ |
6540 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
6546 |
static inline void gen_##name(DisasContext *ctx) \
|
|
6541 | 6547 |
{ \ |
6542 | 6548 |
if (unlikely(!ctx->spe_enabled)) { \ |
6543 | 6549 |
gen_exception(ctx, POWERPC_EXCP_APU); \ |
... | ... | |
6548 | 6554 |
} |
6549 | 6555 |
#else |
6550 | 6556 |
#define GEN_SPEOP_LOGIC2(name, tcg_op) \ |
6551 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
6557 |
static inline void gen_##name(DisasContext *ctx) \
|
|
6552 | 6558 |
{ \ |
6553 | 6559 |
if (unlikely(!ctx->spe_enabled)) { \ |
6554 | 6560 |
gen_exception(ctx, POWERPC_EXCP_APU); \ |
... | ... | |
6573 | 6579 |
/* SPE logic immediate */ |
6574 | 6580 |
#if defined(TARGET_PPC64) |
6575 | 6581 |
#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ |
6576 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
6582 |
static inline void gen_##name(DisasContext *ctx) \
|
|
6577 | 6583 |
{ \ |
6578 | 6584 |
if (unlikely(!ctx->spe_enabled)) { \ |
6579 | 6585 |
gen_exception(ctx, POWERPC_EXCP_APU); \ |
... | ... | |
6594 | 6600 |
} |
6595 | 6601 |
#else |
6596 | 6602 |
#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ |
6597 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
6603 |
static inline void gen_##name(DisasContext *ctx) \
|
|
6598 | 6604 |
{ \ |
6599 | 6605 |
if (unlikely(!ctx->spe_enabled)) { \ |
6600 | 6606 |
gen_exception(ctx, POWERPC_EXCP_APU); \ |
... | ... | |
6614 | 6620 |
/* SPE arithmetic */ |
6615 | 6621 |
#if defined(TARGET_PPC64) |
6616 | 6622 |
#define GEN_SPEOP_ARITH1(name, tcg_op) \ |
6617 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
6623 |
static inline void gen_##name(DisasContext *ctx) \
|
|
6618 | 6624 |
{ \ |
6619 | 6625 |
if (unlikely(!ctx->spe_enabled)) { \ |
6620 | 6626 |
gen_exception(ctx, POWERPC_EXCP_APU); \ |
... | ... | |
6635 | 6641 |
} |
6636 | 6642 |
#else |
6637 | 6643 |
#define GEN_SPEOP_ARITH1(name, tcg_op) \ |
6638 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
6644 |
static inline void gen_##name(DisasContext *ctx) \
|
|
6639 | 6645 |
{ \ |
6640 | 6646 |
if (unlikely(!ctx->spe_enabled)) { \ |
6641 | 6647 |
gen_exception(ctx, POWERPC_EXCP_APU); \ |
... | ... | |
6646 | 6652 |
} |
6647 | 6653 |
#endif |
6648 | 6654 |
|
6649 |
static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
|
|
6655 |
static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
|
|
6650 | 6656 |
{ |
6651 | 6657 |
int l1 = gen_new_label(); |
6652 | 6658 |
int l2 = gen_new_label(); |
... | ... | |
6662 | 6668 |
GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); |
6663 | 6669 |
GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); |
6664 | 6670 |
GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); |
6665 |
static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
|
|
6671 |
static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
|
|
6666 | 6672 |
{ |
6667 | 6673 |
tcg_gen_addi_i32(ret, arg1, 0x8000); |
6668 | 6674 |
tcg_gen_ext16u_i32(ret, ret); |
... | ... | |
6673 | 6679 |
|
6674 | 6680 |
#if defined(TARGET_PPC64) |
6675 | 6681 |
#define GEN_SPEOP_ARITH2(name, tcg_op) \ |
6676 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
6682 |
static inline void gen_##name(DisasContext *ctx) \
|
|
6677 | 6683 |
{ \ |
6678 | 6684 |
if (unlikely(!ctx->spe_enabled)) { \ |
6679 | 6685 |
gen_exception(ctx, POWERPC_EXCP_APU); \ |
... | ... | |
6699 | 6705 |
} |
6700 | 6706 |
#else |
6701 | 6707 |
#define GEN_SPEOP_ARITH2(name, tcg_op) \ |
6702 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
6708 |
static inline void gen_##name(DisasContext *ctx) \
|
|
6703 | 6709 |
{ \ |
6704 | 6710 |
if (unlikely(!ctx->spe_enabled)) { \ |
6705 | 6711 |
gen_exception(ctx, POWERPC_EXCP_APU); \ |
... | ... | |
6712 | 6718 |
} |
6713 | 6719 |
#endif |
6714 | 6720 |
|
6715 |
static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
|
|
6721 |
static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
|
|
6716 | 6722 |
{ |
6717 | 6723 |
TCGv_i32 t0; |
6718 | 6724 |
int l1, l2; |
... | ... | |
6731 | 6737 |
tcg_temp_free_i32(t0); |
6732 | 6738 |
} |
6733 | 6739 |
GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); |
6734 |
static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
|
|
6740 |
static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
|
|
6735 | 6741 |
{ |
6736 | 6742 |
TCGv_i32 t0; |
6737 | 6743 |
int l1, l2; |
... | ... | |
6750 | 6756 |
tcg_temp_free_i32(t0); |
6751 | 6757 |
} |
6752 | 6758 |
GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); |
6753 |
static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
|
|
6759 |
static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
|
|
6754 | 6760 |
{ |
6755 | 6761 |
TCGv_i32 t0; |
6756 | 6762 |
int l1, l2; |
... | ... | |
6769 | 6775 |
tcg_temp_free_i32(t0); |
6770 | 6776 |
} |
6771 | 6777 |
GEN_SPEOP_ARITH2(evslw, gen_op_evslw); |
6772 |
static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
|
|
6778 |
static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
|
|
6773 | 6779 |
{ |
6774 | 6780 |
TCGv_i32 t0 = tcg_temp_new_i32(); |
6775 | 6781 |
tcg_gen_andi_i32(t0, arg2, 0x1F); |
... | ... | |
6777 | 6783 |
tcg_temp_free_i32(t0); |
6778 | 6784 |
} |
6779 | 6785 |
GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); |
6780 |
static always_inline void gen_evmergehi (DisasContext *ctx)
|
|
6786 |
static inline void gen_evmergehi(DisasContext *ctx)
|
|
6781 | 6787 |
{ |
6782 | 6788 |
if (unlikely(!ctx->spe_enabled)) { |
6783 | 6789 |
gen_exception(ctx, POWERPC_EXCP_APU); |
... | ... | |
6797 | 6803 |
#endif |
6798 | 6804 |
} |
6799 | 6805 |
GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); |
6800 |
static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
|
|
6806 |
static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
|
|
6801 | 6807 |
{ |
6802 | 6808 |
tcg_gen_sub_i32(ret, arg2, arg1); |
6803 | 6809 |
} |
... | ... | |
6806 | 6812 |
/* SPE arithmetic immediate */ |
6807 | 6813 |
#if defined(TARGET_PPC64) |
6808 | 6814 |
#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ |
6809 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
6815 |
static inline void gen_##name(DisasContext *ctx) \
|
|
6810 | 6816 |
{ \ |
6811 | 6817 |
if (unlikely(!ctx->spe_enabled)) { \ |
6812 | 6818 |
gen_exception(ctx, POWERPC_EXCP_APU); \ |
... | ... | |
6827 | 6833 |
} |
6828 | 6834 |
#else |
6829 | 6835 |
#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ |
6830 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
6836 |
static inline void gen_##name(DisasContext *ctx) \
|
|
6831 | 6837 |
{ \ |
6832 | 6838 |
if (unlikely(!ctx->spe_enabled)) { \ |
6833 | 6839 |
gen_exception(ctx, POWERPC_EXCP_APU); \ |
... | ... | |
6845 | 6851 |
/* SPE comparison */ |
6846 | 6852 |
#if defined(TARGET_PPC64) |
6847 | 6853 |
#define GEN_SPEOP_COMP(name, tcg_cond) \ |
6848 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
6854 |
static inline void gen_##name(DisasContext *ctx) \
|
|
6849 | 6855 |
{ \ |
6850 | 6856 |
if (unlikely(!ctx->spe_enabled)) { \ |
6851 | 6857 |
gen_exception(ctx, POWERPC_EXCP_APU); \ |
... | ... | |
6885 | 6891 |
} |
6886 | 6892 |
#else |
6887 | 6893 |
#define GEN_SPEOP_COMP(name, tcg_cond) \ |
6888 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
6894 |
static inline void gen_##name(DisasContext *ctx) \
|
|
6889 | 6895 |
{ \ |
6890 | 6896 |
if (unlikely(!ctx->spe_enabled)) { \ |
6891 | 6897 |
gen_exception(ctx, POWERPC_EXCP_APU); \ |
... | ... | |
6922 | 6928 |
GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); |
6923 | 6929 |
|
6924 | 6930 |
/* SPE misc */ |
6925 |
static always_inline void gen_brinc (DisasContext *ctx)
|
|
6931 |
static inline void gen_brinc(DisasContext *ctx)
|
|
6926 | 6932 |
{ |
6927 | 6933 |
/* Note: brinc is usable even if SPE is disabled */ |
6928 | 6934 |
gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], |
6929 | 6935 |
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
6930 | 6936 |
} |
6931 |
static always_inline void gen_evmergelo (DisasContext *ctx)
|
|
6937 |
static inline void gen_evmergelo(DisasContext *ctx)
|
|
6932 | 6938 |
{ |
6933 | 6939 |
if (unlikely(!ctx->spe_enabled)) { |
6934 | 6940 |
gen_exception(ctx, POWERPC_EXCP_APU); |
... | ... | |
6947 | 6953 |
tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
6948 | 6954 |
#endif |
6949 | 6955 |
} |
6950 |
static always_inline void gen_evmergehilo (DisasContext *ctx)
|
|
6956 |
static inline void gen_evmergehilo(DisasContext *ctx)
|
|
6951 | 6957 |
{ |
6952 | 6958 |
if (unlikely(!ctx->spe_enabled)) { |
6953 | 6959 |
gen_exception(ctx, POWERPC_EXCP_APU); |
... | ... | |
6966 | 6972 |
tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
6967 | 6973 |
#endif |
6968 | 6974 |
} |
6969 |
static always_inline void gen_evmergelohi (DisasContext *ctx)
|
|
6975 |
static inline void gen_evmergelohi(DisasContext *ctx)
|
|
6970 | 6976 |
{ |
6971 | 6977 |
if (unlikely(!ctx->spe_enabled)) { |
6972 | 6978 |
gen_exception(ctx, POWERPC_EXCP_APU); |
... | ... | |
6993 | 6999 |
} |
6994 | 7000 |
#endif |
6995 | 7001 |
} |
6996 |
static always_inline void gen_evsplati (DisasContext *ctx)
|
|
7002 |
static inline void gen_evsplati(DisasContext *ctx)
|
|
6997 | 7003 |
{ |
6998 | 7004 |
uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27; |
6999 | 7005 |
|
... | ... | |
7004 | 7010 |
tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); |
7005 | 7011 |
#endif |
7006 | 7012 |
} |
7007 |
static always_inline void gen_evsplatfi (DisasContext *ctx)
|
|
7013 |
static inline void gen_evsplatfi(DisasContext *ctx)
|
|
7008 | 7014 |
{ |
7009 | 7015 |
uint64_t imm = rA(ctx->opcode) << 11; |
7010 | 7016 |
|
... | ... | |
7016 | 7022 |
#endif |
7017 | 7023 |
} |
7018 | 7024 |
|
7019 |
static always_inline void gen_evsel (DisasContext *ctx)
|
|
7025 |
static inline void gen_evsel(DisasContext *ctx)
|
|
7020 | 7026 |
{ |
7021 | 7027 |
int l1 = gen_new_label(); |
7022 | 7028 |
int l2 = gen_new_label(); |
... | ... | |
7112 | 7118 |
GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); //// |
7113 | 7119 |
|
7114 | 7120 |
/* SPE load and stores */ |
7115 |
static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
|
|
7121 |
static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
|
|
7116 | 7122 |
{ |
7117 | 7123 |
target_ulong uimm = rB(ctx->opcode); |
7118 | 7124 |
|
... | ... | |
7128 | 7134 |
} |
7129 | 7135 |
} |
7130 | 7136 |
|
7131 |
static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
|
|
7137 |
static inline void gen_op_evldd(DisasContext *ctx, TCGv addr) |
|
7132 | 7138 |
{ |
7133 | 7139 |
#if defined(TARGET_PPC64) |
7134 | 7140 |
gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
... | ... | |
7142 | 7148 |
#endif |
7143 | 7149 |
} |
7144 | 7150 |
|
7145 |
static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
|
|
7151 |
static inline void gen_op_evldw(DisasContext *ctx, TCGv addr) |
|
7146 | 7152 |
{ |
7147 | 7153 |
#if defined(TARGET_PPC64) |
7148 | 7154 |
TCGv t0 = tcg_temp_new(); |
... | ... | |
7159 | 7165 |
#endif |
7160 | 7166 |
} |
7161 | 7167 |
|
7162 |
static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
|
|
7168 |
static inline void gen_op_evldh(DisasContext *ctx, TCGv addr) |
|
7163 | 7169 |
{ |
7164 | 7170 |
TCGv t0 = tcg_temp_new(); |
7165 | 7171 |
#if defined(TARGET_PPC64) |
... | ... | |
7192 | 7198 |
tcg_temp_free(t0); |
7193 | 7199 |
} |
7194 | 7200 |
|
7195 |
static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
|
|
7201 |
static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) |
|
7196 | 7202 |
{ |
7197 | 7203 |
TCGv t0 = tcg_temp_new(); |
7198 | 7204 |
gen_qemu_ld16u(ctx, t0, addr); |
... | ... | |
7208 | 7214 |
tcg_temp_free(t0); |
7209 | 7215 |
} |
7210 | 7216 |
|
7211 |
static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
|
|
7217 |
static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) |
|
7212 | 7218 |
{ |
7213 | 7219 |
TCGv t0 = tcg_temp_new(); |
7214 | 7220 |
gen_qemu_ld16u(ctx, t0, addr); |
... | ... | |
7222 | 7228 |
tcg_temp_free(t0); |
7223 | 7229 |
} |
7224 | 7230 |
|
7225 |
static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
|
|
7231 |
static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) |
|
7226 | 7232 |
{ |
7227 | 7233 |
TCGv t0 = tcg_temp_new(); |
7228 | 7234 |
gen_qemu_ld16s(ctx, t0, addr); |
... | ... | |
7237 | 7243 |
tcg_temp_free(t0); |
7238 | 7244 |
} |
7239 | 7245 |
|
7240 |
static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
|
|
7246 |
static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) |
|
7241 | 7247 |
{ |
7242 | 7248 |
TCGv t0 = tcg_temp_new(); |
7243 | 7249 |
#if defined(TARGET_PPC64) |
... | ... | |
7257 | 7263 |
tcg_temp_free(t0); |
7258 | 7264 |
} |
7259 | 7265 |
|
7260 |
static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
|
|
7266 |
static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) |
|
7261 | 7267 |
{ |
7262 | 7268 |
#if defined(TARGET_PPC64) |
7263 | 7269 |
TCGv t0 = tcg_temp_new(); |
... | ... | |
7274 | 7280 |
#endif |
7275 | 7281 |
} |
7276 | 7282 |
|
7277 |
static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
|
|
7283 |
static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) |
|
7278 | 7284 |
{ |
7279 | 7285 |
#if defined(TARGET_PPC64) |
7280 | 7286 |
TCGv t0 = tcg_temp_new(); |
... | ... | |
7292 | 7298 |
#endif |
7293 | 7299 |
} |
7294 | 7300 |
|
7295 |
static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
|
|
7301 |
static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) |
|
7296 | 7302 |
{ |
7297 | 7303 |
TCGv t0 = tcg_temp_new(); |
7298 | 7304 |
gen_qemu_ld32u(ctx, t0, addr); |
... | ... | |
7306 | 7312 |
tcg_temp_free(t0); |
7307 | 7313 |
} |
7308 | 7314 |
|
7309 |
static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
|
|
7315 |
static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) |
|
7310 | 7316 |
{ |
7311 | 7317 |
TCGv t0 = tcg_temp_new(); |
7312 | 7318 |
#if defined(TARGET_PPC64) |
... | ... | |
7331 | 7337 |
tcg_temp_free(t0); |
7332 | 7338 |
} |
7333 | 7339 |
|
7334 |
static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
|
|
7340 |
static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) |
|
7335 | 7341 |
{ |
7336 | 7342 |
#if defined(TARGET_PPC64) |
7337 | 7343 |
gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
... | ... | |
7343 | 7349 |
#endif |
7344 | 7350 |
} |
7345 | 7351 |
|
7346 |
static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
|
|
7352 |
static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) |
|
7347 | 7353 |
{ |
7348 | 7354 |
#if defined(TARGET_PPC64) |
7349 | 7355 |
TCGv t0 = tcg_temp_new(); |
... | ... | |
7357 | 7363 |
gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
7358 | 7364 |
} |
7359 | 7365 |
|
7360 |
static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
|
|
7366 |
static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) |
|
7361 | 7367 |
{ |
7362 | 7368 |
TCGv t0 = tcg_temp_new(); |
7363 | 7369 |
#if defined(TARGET_PPC64) |
... | ... | |
7381 | 7387 |
gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
7382 | 7388 |
} |
7383 | 7389 |
|
7384 |
static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
|
|
7390 |
static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) |
|
7385 | 7391 |
{ |
7386 | 7392 |
TCGv t0 = tcg_temp_new(); |
7387 | 7393 |
#if defined(TARGET_PPC64) |
... | ... | |
7396 | 7402 |
tcg_temp_free(t0); |
7397 | 7403 |
} |
7398 | 7404 |
|
7399 |
static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
|
|
7405 |
static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) |
|
7400 | 7406 |
{ |
7401 | 7407 |
#if defined(TARGET_PPC64) |
7402 | 7408 |
TCGv t0 = tcg_temp_new(); |
... | ... | |
7410 | 7416 |
gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
7411 | 7417 |
} |
7412 | 7418 |
|
7413 |
static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
|
|
7419 |
static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) |
|
7414 | 7420 |
{ |
7415 | 7421 |
#if defined(TARGET_PPC64) |
7416 | 7422 |
TCGv t0 = tcg_temp_new(); |
... | ... | |
7422 | 7428 |
#endif |
7423 | 7429 |
} |
7424 | 7430 |
|
7425 |
static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
|
|
7431 |
static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) |
|
7426 | 7432 |
{ |
7427 | 7433 |
gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
7428 | 7434 |
} |
... | ... | |
7545 | 7551 |
/*** SPE floating-point extension ***/ |
7546 | 7552 |
#if defined(TARGET_PPC64) |
7547 | 7553 |
#define GEN_SPEFPUOP_CONV_32_32(name) \ |
7548 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
7554 |
static inline void gen_##name(DisasContext *ctx) \
|
|
7549 | 7555 |
{ \ |
7550 | 7556 |
TCGv_i32 t0; \ |
7551 | 7557 |
TCGv t1; \ |
... | ... | |
7561 | 7567 |
tcg_temp_free(t1); \ |
7562 | 7568 |
} |
7563 | 7569 |
#define GEN_SPEFPUOP_CONV_32_64(name) \ |
7564 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
7570 |
static inline void gen_##name(DisasContext *ctx) \
|
|
7565 | 7571 |
{ \ |
7566 | 7572 |
TCGv_i32 t0; \ |
7567 | 7573 |
TCGv t1; \ |
... | ... | |
7576 | 7582 |
tcg_temp_free(t1); \ |
7577 | 7583 |
} |
7578 | 7584 |
#define GEN_SPEFPUOP_CONV_64_32(name) \ |
7579 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
7585 |
static inline void gen_##name(DisasContext *ctx) \
|
|
7580 | 7586 |
{ \ |
7581 | 7587 |
TCGv_i32 t0 = tcg_temp_new_i32(); \ |
7582 | 7588 |
tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
... | ... | |
7584 | 7590 |
tcg_temp_free_i32(t0); \ |
7585 | 7591 |
} |
7586 | 7592 |
#define GEN_SPEFPUOP_CONV_64_64(name) \ |
7587 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
7593 |
static inline void gen_##name(DisasContext *ctx) \
|
|
7588 | 7594 |
{ \ |
7589 | 7595 |
gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
7590 | 7596 |
} |
7591 | 7597 |
#define GEN_SPEFPUOP_ARITH2_32_32(name) \ |
7592 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
7598 |
static inline void gen_##name(DisasContext *ctx) \
|
|
7593 | 7599 |
{ \ |
7594 | 7600 |
TCGv_i32 t0, t1; \ |
7595 | 7601 |
TCGv_i64 t2; \ |
... | ... | |
7612 | 7618 |
tcg_temp_free(t2); \ |
7613 | 7619 |
} |
7614 | 7620 |
#define GEN_SPEFPUOP_ARITH2_64_64(name) \ |
7615 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
7621 |
static inline void gen_##name(DisasContext *ctx) \
|
|
7616 | 7622 |
{ \ |
7617 | 7623 |
if (unlikely(!ctx->spe_enabled)) { \ |
7618 | 7624 |
gen_exception(ctx, POWERPC_EXCP_APU); \ |
... | ... | |
7622 | 7628 |
cpu_gpr[rB(ctx->opcode)]); \ |
7623 | 7629 |
} |
7624 | 7630 |
#define GEN_SPEFPUOP_COMP_32(name) \ |
7625 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
7631 |
static inline void gen_##name(DisasContext *ctx) \
|
|
7626 | 7632 |
{ \ |
7627 | 7633 |
TCGv_i32 t0, t1; \ |
7628 | 7634 |
if (unlikely(!ctx->spe_enabled)) { \ |
... | ... | |
7638 | 7644 |
tcg_temp_free_i32(t1); \ |
7639 | 7645 |
} |
7640 | 7646 |
#define GEN_SPEFPUOP_COMP_64(name) \ |
7641 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
7647 |
static inline void gen_##name(DisasContext *ctx) \
|
|
7642 | 7648 |
{ \ |
7643 | 7649 |
if (unlikely(!ctx->spe_enabled)) { \ |
7644 | 7650 |
gen_exception(ctx, POWERPC_EXCP_APU); \ |
... | ... | |
7649 | 7655 |
} |
7650 | 7656 |
#else |
7651 | 7657 |
#define GEN_SPEFPUOP_CONV_32_32(name) \ |
7652 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
7658 |
static inline void gen_##name(DisasContext *ctx) \
|
|
7653 | 7659 |
{ \ |
7654 | 7660 |
gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
7655 | 7661 |
} |
7656 | 7662 |
#define GEN_SPEFPUOP_CONV_32_64(name) \ |
7657 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
7663 |
static inline void gen_##name(DisasContext *ctx) \
|
|
7658 | 7664 |
{ \ |
7659 | 7665 |
TCGv_i64 t0 = tcg_temp_new_i64(); \ |
7660 | 7666 |
gen_load_gpr64(t0, rB(ctx->opcode)); \ |
... | ... | |
7662 | 7668 |
tcg_temp_free_i64(t0); \ |
7663 | 7669 |
} |
7664 | 7670 |
#define GEN_SPEFPUOP_CONV_64_32(name) \ |
7665 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
7671 |
static inline void gen_##name(DisasContext *ctx) \
|
|
7666 | 7672 |
{ \ |
7667 | 7673 |
TCGv_i64 t0 = tcg_temp_new_i64(); \ |
7668 | 7674 |
gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \ |
... | ... | |
7670 | 7676 |
tcg_temp_free_i64(t0); \ |
7671 | 7677 |
} |
7672 | 7678 |
#define GEN_SPEFPUOP_CONV_64_64(name) \ |
7673 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
7679 |
static inline void gen_##name(DisasContext *ctx) \
|
|
7674 | 7680 |
{ \ |
7675 | 7681 |
TCGv_i64 t0 = tcg_temp_new_i64(); \ |
7676 | 7682 |
gen_load_gpr64(t0, rB(ctx->opcode)); \ |
... | ... | |
7679 | 7685 |
tcg_temp_free_i64(t0); \ |
7680 | 7686 |
} |
7681 | 7687 |
#define GEN_SPEFPUOP_ARITH2_32_32(name) \ |
7682 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
7688 |
static inline void gen_##name(DisasContext *ctx) \
|
|
7683 | 7689 |
{ \ |
7684 | 7690 |
if (unlikely(!ctx->spe_enabled)) { \ |
7685 | 7691 |
gen_exception(ctx, POWERPC_EXCP_APU); \ |
... | ... | |
7689 | 7695 |
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
7690 | 7696 |
} |
7691 | 7697 |
#define GEN_SPEFPUOP_ARITH2_64_64(name) \ |
7692 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
7698 |
static inline void gen_##name(DisasContext *ctx) \
|
|
7693 | 7699 |
{ \ |
7694 | 7700 |
TCGv_i64 t0, t1; \ |
7695 | 7701 |
if (unlikely(!ctx->spe_enabled)) { \ |
... | ... | |
7706 | 7712 |
tcg_temp_free_i64(t1); \ |
7707 | 7713 |
} |
7708 | 7714 |
#define GEN_SPEFPUOP_COMP_32(name) \ |
7709 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
7715 |
static inline void gen_##name(DisasContext *ctx) \
|
|
7710 | 7716 |
{ \ |
7711 | 7717 |
if (unlikely(!ctx->spe_enabled)) { \ |
7712 | 7718 |
gen_exception(ctx, POWERPC_EXCP_APU); \ |
... | ... | |
7716 | 7722 |
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
7717 | 7723 |
} |
7718 | 7724 |
#define GEN_SPEFPUOP_COMP_64(name) \ |
7719 |
static always_inline void gen_##name (DisasContext *ctx) \
|
|
7725 |
static inline void gen_##name(DisasContext *ctx) \
|
|
7720 | 7726 |
{ \ |
7721 | 7727 |
TCGv_i64 t0, t1; \ |
7722 | 7728 |
if (unlikely(!ctx->spe_enabled)) { \ |
... | ... | |
7739 | 7745 |
GEN_SPEFPUOP_ARITH2_64_64(evfssub); |
7740 | 7746 |
GEN_SPEFPUOP_ARITH2_64_64(evfsmul); |
7741 | 7747 |
GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); |
7742 |
static always_inline void gen_evfsabs (DisasContext *ctx)
|
|
7748 |
static inline void gen_evfsabs(DisasContext *ctx)
|
|
7743 | 7749 |
{ |
7744 | 7750 |
if (unlikely(!ctx->spe_enabled)) { |
7745 | 7751 |
gen_exception(ctx, POWERPC_EXCP_APU); |
... | ... | |
7752 | 7758 |
tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); |
7753 | 7759 |
#endif |
7754 | 7760 |
} |
7755 |
static always_inline void gen_evfsnabs (DisasContext *ctx)
|
|
7761 |
static inline void gen_evfsnabs(DisasContext *ctx)
|
|
7756 | 7762 |
{ |
7757 | 7763 |
if (unlikely(!ctx->spe_enabled)) { |
7758 | 7764 |
gen_exception(ctx, POWERPC_EXCP_APU); |
... | ... | |
7765 | 7771 |
tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); |
7766 | 7772 |
#endif |
7767 | 7773 |
} |
7768 |
static always_inline void gen_evfsneg (DisasContext *ctx)
|
|
7774 |
static inline void gen_evfsneg(DisasContext *ctx)
|
|
7769 | 7775 |
{ |
7770 | 7776 |
if (unlikely(!ctx->spe_enabled)) { |
7771 | 7777 |
gen_exception(ctx, POWERPC_EXCP_APU); |
... | ... | |
7821 | 7827 |
GEN_SPEFPUOP_ARITH2_32_32(efssub); |
7822 | 7828 |
GEN_SPEFPUOP_ARITH2_32_32(efsmul); |
7823 | 7829 |
GEN_SPEFPUOP_ARITH2_32_32(efsdiv); |
7824 |
static always_inline void gen_efsabs (DisasContext *ctx)
|
|
7830 |
static inline void gen_efsabs(DisasContext *ctx)
|
|
7825 | 7831 |
{ |
7826 | 7832 |
if (unlikely(!ctx->spe_enabled)) { |
7827 | 7833 |
gen_exception(ctx, POWERPC_EXCP_APU); |
... | ... | |
7829 | 7835 |
} |
7830 | 7836 |
tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL); |
7831 | 7837 |
} |
7832 |
static always_inline void gen_efsnabs (DisasContext *ctx)
|
|
7838 |
static inline void gen_efsnabs(DisasContext *ctx)
|
|
7833 | 7839 |
{ |
7834 | 7840 |
if (unlikely(!ctx->spe_enabled)) { |
7835 | 7841 |
gen_exception(ctx, POWERPC_EXCP_APU); |
... | ... | |
7837 | 7843 |
} |
7838 | 7844 |
tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
7839 | 7845 |
} |
7840 |
static always_inline void gen_efsneg (DisasContext *ctx)
|
|
7846 |
static inline void gen_efsneg(DisasContext *ctx)
|
|
7841 | 7847 |
{ |
7842 | 7848 |
if (unlikely(!ctx->spe_enabled)) { |
7843 | 7849 |
gen_exception(ctx, POWERPC_EXCP_APU); |
... | ... | |
7889 | 7895 |
GEN_SPEFPUOP_ARITH2_64_64(efdsub); |
7890 | 7896 |
GEN_SPEFPUOP_ARITH2_64_64(efdmul); |
7891 | 7897 |
GEN_SPEFPUOP_ARITH2_64_64(efddiv); |
7892 |
static always_inline void gen_efdabs (DisasContext *ctx)
|
|
7898 |
static inline void gen_efdabs(DisasContext *ctx)
|
|
7893 | 7899 |
{ |
7894 | 7900 |
if (unlikely(!ctx->spe_enabled)) { |
7895 | 7901 |
gen_exception(ctx, POWERPC_EXCP_APU); |
... | ... | |
7901 | 7907 |
tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); |
7902 | 7908 |
#endif |
7903 | 7909 |
} |
7904 |
static always_inline void gen_efdnabs (DisasContext *ctx)
|
|
7910 |
static inline void gen_efdnabs(DisasContext *ctx)
|
|
7905 | 7911 |
{ |
7906 | 7912 |
if (unlikely(!ctx->spe_enabled)) { |
7907 | 7913 |
gen_exception(ctx, POWERPC_EXCP_APU); |
... | ... | |
7913 | 7919 |
tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); |
7914 | 7920 |
#endif |
7915 | 7921 |
} |
7916 |
static always_inline void gen_efdneg (DisasContext *ctx)
|
|
7922 |
static inline void gen_efdneg(DisasContext *ctx)
|
|
7917 | 7923 |
{ |
7918 | 7924 |
if (unlikely(!ctx->spe_enabled)) { |
7919 | 7925 |
gen_exception(ctx, POWERPC_EXCP_APU); |
... | ... | |
8936 | 8942 |
} |
8937 | 8943 |
|
8938 | 8944 |
/*****************************************************************************/ |
8939 |
static always_inline void gen_intermediate_code_internal (CPUState *env,
|
|
8940 |
TranslationBlock *tb,
|
|
8941 |
int search_pc)
|
|
8945 |
static inline void gen_intermediate_code_internal(CPUState *env,
|
|
8946 |
TranslationBlock *tb, |
|
8947 |
int search_pc) |
|
8942 | 8948 |
{ |
8943 | 8949 |
DisasContext ctx, *ctxp = &ctx; |
8944 | 8950 |
opc_handler_t **table, *handler; |
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