root / hw / ppc4xx_devs.c @ 636aa200
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/*
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* QEMU PowerPC 4xx embedded processors shared devices emulation
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "ppc.h" |
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#include "ppc4xx.h" |
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#include "sysemu.h" |
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#include "qemu-log.h" |
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//#define DEBUG_MMIO
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//#define DEBUG_UNASSIGNED
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#define DEBUG_UIC
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#ifdef DEBUG_UIC
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# define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) |
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#else
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# define LOG_UIC(...) do { } while (0) |
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#endif
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/*****************************************************************************/
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/* Generic PowerPC 4xx processor instanciation */
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CPUState *ppc4xx_init (const char *cpu_model, |
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clk_setup_t *cpu_clk, clk_setup_t *tb_clk, |
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uint32_t sysclk) |
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{
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CPUState *env; |
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|
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/* init CPUs */
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env = cpu_init(cpu_model); |
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if (!env) {
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fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
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cpu_model); |
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exit(1);
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} |
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cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */ |
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cpu_clk->opaque = env; |
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/* Set time-base frequency to sysclk */
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tb_clk->cb = ppc_emb_timers_init(env, sysclk); |
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tb_clk->opaque = env; |
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ppc_dcr_init(env, NULL, NULL); |
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/* Register qemu callbacks */
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qemu_register_reset(&cpu_ppc_reset, env); |
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return env;
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} |
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|
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/*****************************************************************************/
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/* "Universal" Interrupt controller */
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enum {
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DCR_UICSR = 0x000,
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DCR_UICSRS = 0x001,
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DCR_UICER = 0x002,
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DCR_UICCR = 0x003,
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DCR_UICPR = 0x004,
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DCR_UICTR = 0x005,
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DCR_UICMSR = 0x006,
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DCR_UICVR = 0x007,
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DCR_UICVCR = 0x008,
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DCR_UICMAX = 0x009,
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}; |
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#define UIC_MAX_IRQ 32 |
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typedef struct ppcuic_t ppcuic_t; |
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struct ppcuic_t {
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uint32_t dcr_base; |
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int use_vectors;
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uint32_t level; /* Remembers the state of level-triggered interrupts. */
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uint32_t uicsr; /* Status register */
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uint32_t uicer; /* Enable register */
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uint32_t uiccr; /* Critical register */
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uint32_t uicpr; /* Polarity register */
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uint32_t uictr; /* Triggering register */
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uint32_t uicvcr; /* Vector configuration register */
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uint32_t uicvr; |
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qemu_irq *irqs; |
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}; |
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|
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static void ppcuic_trigger_irq (ppcuic_t *uic) |
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{
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uint32_t ir, cr; |
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int start, end, inc, i;
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/* Trigger interrupt if any is pending */
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ir = uic->uicsr & uic->uicer & (~uic->uiccr); |
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cr = uic->uicsr & uic->uicer & uic->uiccr; |
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LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32 |
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" uiccr %08" PRIx32 "\n" |
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" %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n", |
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__func__, uic->uicsr, uic->uicer, uic->uiccr, |
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uic->uicsr & uic->uicer, ir, cr); |
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if (ir != 0x0000000) { |
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LOG_UIC("Raise UIC interrupt\n");
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qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]); |
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} else {
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LOG_UIC("Lower UIC interrupt\n");
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qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]); |
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} |
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/* Trigger critical interrupt if any is pending and update vector */
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if (cr != 0x0000000) { |
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qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]); |
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if (uic->use_vectors) {
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/* Compute critical IRQ vector */
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if (uic->uicvcr & 1) { |
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start = 31;
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end = 0;
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inc = -1;
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} else {
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start = 0;
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end = 31;
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inc = 1;
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} |
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uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
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for (i = start; i <= end; i += inc) {
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if (cr & (1 << i)) { |
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uic->uicvr += (i - start) * 512 * inc;
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break;
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} |
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} |
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} |
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LOG_UIC("Raise UIC critical interrupt - "
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"vector %08" PRIx32 "\n", uic->uicvr); |
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} else {
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LOG_UIC("Lower UIC critical interrupt\n");
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qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]); |
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uic->uicvr = 0x00000000;
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} |
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} |
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static void ppcuic_set_irq (void *opaque, int irq_num, int level) |
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{
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ppcuic_t *uic; |
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uint32_t mask, sr; |
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uic = opaque; |
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mask = 1 << (31-irq_num); |
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LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
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" mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n", |
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__func__, irq_num, level, |
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uic->uicsr, mask, uic->uicsr & mask, level << irq_num); |
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if (irq_num < 0 || irq_num > 31) |
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return;
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sr = uic->uicsr; |
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/* Update status register */
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if (uic->uictr & mask) {
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/* Edge sensitive interrupt */
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if (level == 1) |
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uic->uicsr |= mask; |
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} else {
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/* Level sensitive interrupt */
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if (level == 1) { |
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uic->uicsr |= mask; |
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uic->level |= mask; |
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} else {
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uic->uicsr &= ~mask; |
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uic->level &= ~mask; |
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} |
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} |
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LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => " |
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"%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr); |
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if (sr != uic->uicsr)
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ppcuic_trigger_irq(uic); |
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} |
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static target_ulong dcr_read_uic (void *opaque, int dcrn) |
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{
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ppcuic_t *uic; |
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target_ulong ret; |
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uic = opaque; |
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dcrn -= uic->dcr_base; |
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switch (dcrn) {
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case DCR_UICSR:
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case DCR_UICSRS:
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ret = uic->uicsr; |
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break;
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case DCR_UICER:
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ret = uic->uicer; |
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break;
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case DCR_UICCR:
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ret = uic->uiccr; |
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break;
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case DCR_UICPR:
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ret = uic->uicpr; |
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break;
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case DCR_UICTR:
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ret = uic->uictr; |
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break;
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case DCR_UICMSR:
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ret = uic->uicsr & uic->uicer; |
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break;
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case DCR_UICVR:
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if (!uic->use_vectors)
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goto no_read;
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ret = uic->uicvr; |
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break;
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case DCR_UICVCR:
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if (!uic->use_vectors)
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goto no_read;
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ret = uic->uicvcr; |
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break;
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default:
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no_read:
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ret = 0x00000000;
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break;
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} |
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return ret;
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} |
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|
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static void dcr_write_uic (void *opaque, int dcrn, target_ulong val) |
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{
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ppcuic_t *uic; |
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uic = opaque; |
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dcrn -= uic->dcr_base; |
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LOG_UIC("%s: dcr %d val " ADDRX "\n", __func__, dcrn, val); |
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switch (dcrn) {
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case DCR_UICSR:
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uic->uicsr &= ~val; |
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uic->uicsr |= uic->level; |
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ppcuic_trigger_irq(uic); |
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break;
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case DCR_UICSRS:
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uic->uicsr |= val; |
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ppcuic_trigger_irq(uic); |
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break;
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case DCR_UICER:
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uic->uicer = val; |
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ppcuic_trigger_irq(uic); |
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break;
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case DCR_UICCR:
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uic->uiccr = val; |
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ppcuic_trigger_irq(uic); |
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break;
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case DCR_UICPR:
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uic->uicpr = val; |
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break;
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case DCR_UICTR:
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uic->uictr = val; |
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ppcuic_trigger_irq(uic); |
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break;
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case DCR_UICMSR:
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break;
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case DCR_UICVR:
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break;
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case DCR_UICVCR:
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uic->uicvcr = val & 0xFFFFFFFD;
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ppcuic_trigger_irq(uic); |
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break;
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} |
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} |
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|
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static void ppcuic_reset (void *opaque) |
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{
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ppcuic_t *uic; |
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uic = opaque; |
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uic->uiccr = 0x00000000;
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uic->uicer = 0x00000000;
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uic->uicpr = 0x00000000;
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uic->uicsr = 0x00000000;
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uic->uictr = 0x00000000;
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if (uic->use_vectors) {
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uic->uicvcr = 0x00000000;
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uic->uicvr = 0x0000000;
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} |
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} |
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qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, |
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uint32_t dcr_base, int has_ssr, int has_vr) |
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{
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ppcuic_t *uic; |
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int i;
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uic = qemu_mallocz(sizeof(ppcuic_t));
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uic->dcr_base = dcr_base; |
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uic->irqs = irqs; |
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if (has_vr)
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uic->use_vectors = 1;
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for (i = 0; i < DCR_UICMAX; i++) { |
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ppc_dcr_register(env, dcr_base + i, uic, |
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&dcr_read_uic, &dcr_write_uic); |
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} |
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qemu_register_reset(ppcuic_reset, uic); |
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ppcuic_reset(uic); |
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return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
|
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} |
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|
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/*****************************************************************************/
|
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/* SDRAM controller */
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typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; |
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struct ppc4xx_sdram_t {
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uint32_t addr; |
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int nbanks;
|
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target_phys_addr_t ram_bases[4];
|
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target_phys_addr_t ram_sizes[4];
|
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uint32_t besr0; |
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uint32_t besr1; |
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uint32_t bear; |
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uint32_t cfg; |
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uint32_t status; |
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uint32_t rtr; |
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uint32_t pmit; |
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uint32_t bcr[4];
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uint32_t tr; |
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uint32_t ecccfg; |
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uint32_t eccesr; |
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qemu_irq irq; |
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}; |
| 333 |
|
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enum {
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SDRAM0_CFGADDR = 0x010,
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SDRAM0_CFGDATA = 0x011,
|
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}; |
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|
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/* XXX: TOFIX: some patches have made this code become inconsistent:
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* there are type inconsistencies, mixing target_phys_addr_t, target_ulong
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* and uint32_t
|
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*/
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static uint32_t sdram_bcr (target_phys_addr_t ram_base,
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target_phys_addr_t ram_size) |
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{
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uint32_t bcr; |
| 347 |
|
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switch (ram_size) {
|
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case (4 * 1024 * 1024): |
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bcr = 0x00000000;
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break;
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| 352 |
case (8 * 1024 * 1024): |
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bcr = 0x00020000;
|
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break;
|
| 355 |
case (16 * 1024 * 1024): |
| 356 |
bcr = 0x00040000;
|
| 357 |
break;
|
| 358 |
case (32 * 1024 * 1024): |
| 359 |
bcr = 0x00060000;
|
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break;
|
| 361 |
case (64 * 1024 * 1024): |
| 362 |
bcr = 0x00080000;
|
| 363 |
break;
|
| 364 |
case (128 * 1024 * 1024): |
| 365 |
bcr = 0x000A0000;
|
| 366 |
break;
|
| 367 |
case (256 * 1024 * 1024): |
| 368 |
bcr = 0x000C0000;
|
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break;
|
| 370 |
default:
|
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printf("%s: invalid RAM size " PADDRX "\n", __func__, ram_size); |
| 372 |
return 0x00000000; |
| 373 |
} |
| 374 |
bcr |= ram_base & 0xFF800000;
|
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bcr |= 1;
|
| 376 |
|
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return bcr;
|
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} |
| 379 |
|
| 380 |
static inline target_phys_addr_t sdram_base(uint32_t bcr) |
| 381 |
{
|
| 382 |
return bcr & 0xFF800000; |
| 383 |
} |
| 384 |
|
| 385 |
static target_ulong sdram_size (uint32_t bcr)
|
| 386 |
{
|
| 387 |
target_ulong size; |
| 388 |
int sh;
|
| 389 |
|
| 390 |
sh = (bcr >> 17) & 0x7; |
| 391 |
if (sh == 7) |
| 392 |
size = -1;
|
| 393 |
else
|
| 394 |
size = (4 * 1024 * 1024) << sh; |
| 395 |
|
| 396 |
return size;
|
| 397 |
} |
| 398 |
|
| 399 |
static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled) |
| 400 |
{
|
| 401 |
if (*bcrp & 0x00000001) { |
| 402 |
/* Unmap RAM */
|
| 403 |
#ifdef DEBUG_SDRAM
|
| 404 |
printf("%s: unmap RAM area " PADDRX " " ADDRX "\n", |
| 405 |
__func__, sdram_base(*bcrp), sdram_size(*bcrp)); |
| 406 |
#endif
|
| 407 |
cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp), |
| 408 |
IO_MEM_UNASSIGNED); |
| 409 |
} |
| 410 |
*bcrp = bcr & 0xFFDEE001;
|
| 411 |
if (enabled && (bcr & 0x00000001)) { |
| 412 |
#ifdef DEBUG_SDRAM
|
| 413 |
printf("%s: Map RAM area " PADDRX " " ADDRX "\n", |
| 414 |
__func__, sdram_base(bcr), sdram_size(bcr)); |
| 415 |
#endif
|
| 416 |
cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr), |
| 417 |
sdram_base(bcr) | IO_MEM_RAM); |
| 418 |
} |
| 419 |
} |
| 420 |
|
| 421 |
static void sdram_map_bcr (ppc4xx_sdram_t *sdram) |
| 422 |
{
|
| 423 |
int i;
|
| 424 |
|
| 425 |
for (i = 0; i < sdram->nbanks; i++) { |
| 426 |
if (sdram->ram_sizes[i] != 0) { |
| 427 |
sdram_set_bcr(&sdram->bcr[i], |
| 428 |
sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]), |
| 429 |
1);
|
| 430 |
} else {
|
| 431 |
sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0); |
| 432 |
} |
| 433 |
} |
| 434 |
} |
| 435 |
|
| 436 |
static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) |
| 437 |
{
|
| 438 |
int i;
|
| 439 |
|
| 440 |
for (i = 0; i < sdram->nbanks; i++) { |
| 441 |
#ifdef DEBUG_SDRAM
|
| 442 |
printf("%s: Unmap RAM area " PADDRX " " ADDRX "\n", |
| 443 |
__func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i])); |
| 444 |
#endif
|
| 445 |
cpu_register_physical_memory(sdram_base(sdram->bcr[i]), |
| 446 |
sdram_size(sdram->bcr[i]), |
| 447 |
IO_MEM_UNASSIGNED); |
| 448 |
} |
| 449 |
} |
| 450 |
|
| 451 |
static target_ulong dcr_read_sdram (void *opaque, int dcrn) |
| 452 |
{
|
| 453 |
ppc4xx_sdram_t *sdram; |
| 454 |
target_ulong ret; |
| 455 |
|
| 456 |
sdram = opaque; |
| 457 |
switch (dcrn) {
|
| 458 |
case SDRAM0_CFGADDR:
|
| 459 |
ret = sdram->addr; |
| 460 |
break;
|
| 461 |
case SDRAM0_CFGDATA:
|
| 462 |
switch (sdram->addr) {
|
| 463 |
case 0x00: /* SDRAM_BESR0 */ |
| 464 |
ret = sdram->besr0; |
| 465 |
break;
|
| 466 |
case 0x08: /* SDRAM_BESR1 */ |
| 467 |
ret = sdram->besr1; |
| 468 |
break;
|
| 469 |
case 0x10: /* SDRAM_BEAR */ |
| 470 |
ret = sdram->bear; |
| 471 |
break;
|
| 472 |
case 0x20: /* SDRAM_CFG */ |
| 473 |
ret = sdram->cfg; |
| 474 |
break;
|
| 475 |
case 0x24: /* SDRAM_STATUS */ |
| 476 |
ret = sdram->status; |
| 477 |
break;
|
| 478 |
case 0x30: /* SDRAM_RTR */ |
| 479 |
ret = sdram->rtr; |
| 480 |
break;
|
| 481 |
case 0x34: /* SDRAM_PMIT */ |
| 482 |
ret = sdram->pmit; |
| 483 |
break;
|
| 484 |
case 0x40: /* SDRAM_B0CR */ |
| 485 |
ret = sdram->bcr[0];
|
| 486 |
break;
|
| 487 |
case 0x44: /* SDRAM_B1CR */ |
| 488 |
ret = sdram->bcr[1];
|
| 489 |
break;
|
| 490 |
case 0x48: /* SDRAM_B2CR */ |
| 491 |
ret = sdram->bcr[2];
|
| 492 |
break;
|
| 493 |
case 0x4C: /* SDRAM_B3CR */ |
| 494 |
ret = sdram->bcr[3];
|
| 495 |
break;
|
| 496 |
case 0x80: /* SDRAM_TR */ |
| 497 |
ret = -1; /* ? */ |
| 498 |
break;
|
| 499 |
case 0x94: /* SDRAM_ECCCFG */ |
| 500 |
ret = sdram->ecccfg; |
| 501 |
break;
|
| 502 |
case 0x98: /* SDRAM_ECCESR */ |
| 503 |
ret = sdram->eccesr; |
| 504 |
break;
|
| 505 |
default: /* Error */ |
| 506 |
ret = -1;
|
| 507 |
break;
|
| 508 |
} |
| 509 |
break;
|
| 510 |
default:
|
| 511 |
/* Avoid gcc warning */
|
| 512 |
ret = 0x00000000;
|
| 513 |
break;
|
| 514 |
} |
| 515 |
|
| 516 |
return ret;
|
| 517 |
} |
| 518 |
|
| 519 |
static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val) |
| 520 |
{
|
| 521 |
ppc4xx_sdram_t *sdram; |
| 522 |
|
| 523 |
sdram = opaque; |
| 524 |
switch (dcrn) {
|
| 525 |
case SDRAM0_CFGADDR:
|
| 526 |
sdram->addr = val; |
| 527 |
break;
|
| 528 |
case SDRAM0_CFGDATA:
|
| 529 |
switch (sdram->addr) {
|
| 530 |
case 0x00: /* SDRAM_BESR0 */ |
| 531 |
sdram->besr0 &= ~val; |
| 532 |
break;
|
| 533 |
case 0x08: /* SDRAM_BESR1 */ |
| 534 |
sdram->besr1 &= ~val; |
| 535 |
break;
|
| 536 |
case 0x10: /* SDRAM_BEAR */ |
| 537 |
sdram->bear = val; |
| 538 |
break;
|
| 539 |
case 0x20: /* SDRAM_CFG */ |
| 540 |
val &= 0xFFE00000;
|
| 541 |
if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) { |
| 542 |
#ifdef DEBUG_SDRAM
|
| 543 |
printf("%s: enable SDRAM controller\n", __func__);
|
| 544 |
#endif
|
| 545 |
/* validate all RAM mappings */
|
| 546 |
sdram_map_bcr(sdram); |
| 547 |
sdram->status &= ~0x80000000;
|
| 548 |
} else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) { |
| 549 |
#ifdef DEBUG_SDRAM
|
| 550 |
printf("%s: disable SDRAM controller\n", __func__);
|
| 551 |
#endif
|
| 552 |
/* invalidate all RAM mappings */
|
| 553 |
sdram_unmap_bcr(sdram); |
| 554 |
sdram->status |= 0x80000000;
|
| 555 |
} |
| 556 |
if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) |
| 557 |
sdram->status |= 0x40000000;
|
| 558 |
else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) |
| 559 |
sdram->status &= ~0x40000000;
|
| 560 |
sdram->cfg = val; |
| 561 |
break;
|
| 562 |
case 0x24: /* SDRAM_STATUS */ |
| 563 |
/* Read-only register */
|
| 564 |
break;
|
| 565 |
case 0x30: /* SDRAM_RTR */ |
| 566 |
sdram->rtr = val & 0x3FF80000;
|
| 567 |
break;
|
| 568 |
case 0x34: /* SDRAM_PMIT */ |
| 569 |
sdram->pmit = (val & 0xF8000000) | 0x07C00000; |
| 570 |
break;
|
| 571 |
case 0x40: /* SDRAM_B0CR */ |
| 572 |
sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000); |
| 573 |
break;
|
| 574 |
case 0x44: /* SDRAM_B1CR */ |
| 575 |
sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000); |
| 576 |
break;
|
| 577 |
case 0x48: /* SDRAM_B2CR */ |
| 578 |
sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000); |
| 579 |
break;
|
| 580 |
case 0x4C: /* SDRAM_B3CR */ |
| 581 |
sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000); |
| 582 |
break;
|
| 583 |
case 0x80: /* SDRAM_TR */ |
| 584 |
sdram->tr = val & 0x018FC01F;
|
| 585 |
break;
|
| 586 |
case 0x94: /* SDRAM_ECCCFG */ |
| 587 |
sdram->ecccfg = val & 0x00F00000;
|
| 588 |
break;
|
| 589 |
case 0x98: /* SDRAM_ECCESR */ |
| 590 |
val &= 0xFFF0F000;
|
| 591 |
if (sdram->eccesr == 0 && val != 0) |
| 592 |
qemu_irq_raise(sdram->irq); |
| 593 |
else if (sdram->eccesr != 0 && val == 0) |
| 594 |
qemu_irq_lower(sdram->irq); |
| 595 |
sdram->eccesr = val; |
| 596 |
break;
|
| 597 |
default: /* Error */ |
| 598 |
break;
|
| 599 |
} |
| 600 |
break;
|
| 601 |
} |
| 602 |
} |
| 603 |
|
| 604 |
static void sdram_reset (void *opaque) |
| 605 |
{
|
| 606 |
ppc4xx_sdram_t *sdram; |
| 607 |
|
| 608 |
sdram = opaque; |
| 609 |
sdram->addr = 0x00000000;
|
| 610 |
sdram->bear = 0x00000000;
|
| 611 |
sdram->besr0 = 0x00000000; /* No error */ |
| 612 |
sdram->besr1 = 0x00000000; /* No error */ |
| 613 |
sdram->cfg = 0x00000000;
|
| 614 |
sdram->ecccfg = 0x00000000; /* No ECC */ |
| 615 |
sdram->eccesr = 0x00000000; /* No error */ |
| 616 |
sdram->pmit = 0x07C00000;
|
| 617 |
sdram->rtr = 0x05F00000;
|
| 618 |
sdram->tr = 0x00854009;
|
| 619 |
/* We pre-initialize RAM banks */
|
| 620 |
sdram->status = 0x00000000;
|
| 621 |
sdram->cfg = 0x00800000;
|
| 622 |
sdram_unmap_bcr(sdram); |
| 623 |
} |
| 624 |
|
| 625 |
void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, |
| 626 |
target_phys_addr_t *ram_bases, |
| 627 |
target_phys_addr_t *ram_sizes, |
| 628 |
int do_init)
|
| 629 |
{
|
| 630 |
ppc4xx_sdram_t *sdram; |
| 631 |
|
| 632 |
sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
|
| 633 |
sdram->irq = irq; |
| 634 |
sdram->nbanks = nbanks; |
| 635 |
memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t)); |
| 636 |
memcpy(sdram->ram_bases, ram_bases, |
| 637 |
nbanks * sizeof(target_phys_addr_t));
|
| 638 |
memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t)); |
| 639 |
memcpy(sdram->ram_sizes, ram_sizes, |
| 640 |
nbanks * sizeof(target_phys_addr_t));
|
| 641 |
sdram_reset(sdram); |
| 642 |
qemu_register_reset(&sdram_reset, sdram); |
| 643 |
ppc_dcr_register(env, SDRAM0_CFGADDR, |
| 644 |
sdram, &dcr_read_sdram, &dcr_write_sdram); |
| 645 |
ppc_dcr_register(env, SDRAM0_CFGDATA, |
| 646 |
sdram, &dcr_read_sdram, &dcr_write_sdram); |
| 647 |
if (do_init)
|
| 648 |
sdram_map_bcr(sdram); |
| 649 |
} |
| 650 |
|
| 651 |
/* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory.
|
| 652 |
*
|
| 653 |
* sdram_bank_sizes[] must be 0-terminated.
|
| 654 |
*
|
| 655 |
* The 4xx SDRAM controller supports a small number of banks, and each bank
|
| 656 |
* must be one of a small set of sizes. The number of banks and the supported
|
| 657 |
* sizes varies by SoC. */
|
| 658 |
ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
|
| 659 |
target_phys_addr_t ram_bases[], |
| 660 |
target_phys_addr_t ram_sizes[], |
| 661 |
const unsigned int sdram_bank_sizes[]) |
| 662 |
{
|
| 663 |
ram_addr_t size_left = ram_size; |
| 664 |
int i;
|
| 665 |
int j;
|
| 666 |
|
| 667 |
for (i = 0; i < nr_banks; i++) { |
| 668 |
for (j = 0; sdram_bank_sizes[j] != 0; j++) { |
| 669 |
unsigned int bank_size = sdram_bank_sizes[j]; |
| 670 |
|
| 671 |
if (bank_size <= size_left) {
|
| 672 |
ram_bases[i] = qemu_ram_alloc(bank_size); |
| 673 |
ram_sizes[i] = bank_size; |
| 674 |
size_left -= bank_size; |
| 675 |
break;
|
| 676 |
} |
| 677 |
} |
| 678 |
|
| 679 |
if (!size_left) {
|
| 680 |
/* No need to use the remaining banks. */
|
| 681 |
break;
|
| 682 |
} |
| 683 |
} |
| 684 |
|
| 685 |
ram_size -= size_left; |
| 686 |
if (ram_size)
|
| 687 |
printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n",
|
| 688 |
(int)(ram_size >> 20)); |
| 689 |
|
| 690 |
return ram_size;
|
| 691 |
} |