Revision 63e6f31d hw/apb_pci.c
b/hw/apb_pci.c | ||
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#include "sysbus.h" |
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#include "pci.h" |
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#include "pci_host.h" |
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#include "rwhandler.h" |
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#include "apb_pci.h" |
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/* debug APB */ |
... | ... | |
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typedef struct APBState { |
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SysBusDevice busdev; |
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PCIHostState host_state; |
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ReadWriteHandler pci_config_handler; |
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uint32_t iommu[4]; |
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uint32_t pci_control[16]; |
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uint32_t pci_irq_map[8]; |
... | ... | |
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&apb_config_readl, |
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}; |
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static void apb_pci_config_write(APBState *s, target_phys_addr_t addr,
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static void apb_pci_config_write(ReadWriteHandler *h, pcibus_t addr,
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uint32_t val, int size) |
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{ |
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APBState *s = container_of(h, APBState, pci_config_handler); |
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val = qemu_bswap_len(val, size); |
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val); |
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pci_data_write(s->host_state.bus, addr, val, size); |
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} |
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static uint32_t apb_pci_config_read(APBState *s, target_phys_addr_t addr,
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static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr,
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int size) |
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{ |
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uint32_t ret; |
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APBState *s = container_of(h, APBState, pci_config_handler); |
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ret = pci_data_read(s->host_state.bus, addr, size); |
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ret = qemu_bswap_len(ret, size); |
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret); |
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return ret; |
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} |
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static void apb_pci_config_writel(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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APBState *s = opaque; |
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apb_pci_config_write(s, addr, bswap32(val), 4); |
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} |
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static void apb_pci_config_writew(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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APBState *s = opaque; |
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apb_pci_config_write(s, addr, bswap16(val), 2); |
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} |
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static void apb_pci_config_writeb(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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APBState *s = opaque; |
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apb_pci_config_write(s, addr, val, 1); |
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} |
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static uint32_t apb_pci_config_readl(void *opaque, target_phys_addr_t addr) |
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{ |
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APBState *s = opaque; |
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return bswap32(apb_pci_config_read(s, addr, 4)); |
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} |
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static uint32_t apb_pci_config_readw(void *opaque, target_phys_addr_t addr) |
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{ |
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APBState *s = opaque; |
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return bswap16(apb_pci_config_read(s, addr, 2)); |
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} |
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static uint32_t apb_pci_config_readb(void *opaque, target_phys_addr_t addr) |
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{ |
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APBState *s = opaque; |
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return apb_pci_config_read(s, addr, 1); |
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} |
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static CPUWriteMemoryFunc * const apb_pci_config_writes[] = { |
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&apb_pci_config_writeb, |
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&apb_pci_config_writew, |
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&apb_pci_config_writel, |
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}; |
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static CPUReadMemoryFunc * const apb_pci_config_reads[] = { |
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&apb_pci_config_readb, |
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&apb_pci_config_readw, |
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&apb_pci_config_readl, |
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}; |
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static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
... | ... | |
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pci_apb_iowrite, s); |
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sysbus_init_mmio(dev, 0x10000ULL, pci_ioport); |
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/* pci_config */ |
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pci_config = cpu_register_io_memory(apb_pci_config_reads, |
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apb_pci_config_writes, s); |
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s->pci_config_handler.read = apb_pci_config_read; |
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s->pci_config_handler.write = apb_pci_config_write; |
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pci_config = cpu_register_io_memory_simple(&s->pci_config_handler); |
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assert(pci_config >= 0); |
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sysbus_init_mmio(dev, 0x1000000ULL, pci_config); |
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/* mem_data */ |
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pci_mem_data = pci_host_data_register_mmio(&s->host_state); |
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