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1 | d4e8164f | bellard | /*
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2 | d4e8164f | bellard | * internal execution defines for qemu
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3 | 5fafdf24 | ths | *
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4 | d4e8164f | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | d4e8164f | bellard | *
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6 | d4e8164f | bellard | * This library is free software; you can redistribute it and/or
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7 | d4e8164f | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | d4e8164f | bellard | * License as published by the Free Software Foundation; either
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9 | d4e8164f | bellard | * version 2 of the License, or (at your option) any later version.
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10 | d4e8164f | bellard | *
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11 | d4e8164f | bellard | * This library is distributed in the hope that it will be useful,
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12 | d4e8164f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | d4e8164f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | d4e8164f | bellard | * Lesser General Public License for more details.
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15 | d4e8164f | bellard | *
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16 | d4e8164f | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | d4e8164f | bellard | * License along with this library; if not, write to the Free Software
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18 | d4e8164f | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | d4e8164f | bellard | */
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20 | d4e8164f | bellard | |
21 | b346ff46 | bellard | /* allow to see translation results - the slowdown should be negligible, so we leave it */
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22 | b346ff46 | bellard | #define DEBUG_DISAS
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23 | b346ff46 | bellard | |
24 | 33417e70 | bellard | #ifndef glue
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25 | 33417e70 | bellard | #define xglue(x, y) x ## y |
26 | 33417e70 | bellard | #define glue(x, y) xglue(x, y)
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27 | 33417e70 | bellard | #define stringify(s) tostring(s)
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28 | 33417e70 | bellard | #define tostring(s) #s |
29 | 33417e70 | bellard | #endif
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30 | 33417e70 | bellard | |
31 | 2e03286b | balrog | #ifndef likely
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32 | c98baaac | bellard | #if __GNUC__ < 3 |
33 | 33417e70 | bellard | #define __builtin_expect(x, n) (x)
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34 | 33417e70 | bellard | #endif
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35 | 33417e70 | bellard | |
36 | cbecba26 | j_mayer | #define likely(x) __builtin_expect(!!(x), 1) |
37 | cbecba26 | j_mayer | #define unlikely(x) __builtin_expect(!!(x), 0) |
38 | 2e03286b | balrog | #endif
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39 | cbecba26 | j_mayer | |
40 | 29f640e2 | j_mayer | #ifndef always_inline
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41 | 8a84de23 | j_mayer | #if (__GNUC__ < 3) || defined(__APPLE__) |
42 | 29f640e2 | j_mayer | #define always_inline inline |
43 | 29f640e2 | j_mayer | #else
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44 | 29f640e2 | j_mayer | #define always_inline __attribute__ (( always_inline )) inline |
45 | 29f640e2 | j_mayer | #endif
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46 | 29f640e2 | j_mayer | #endif
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47 | 29f640e2 | j_mayer | |
48 | e2222c39 | bellard | #ifdef __i386__
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49 | e2222c39 | bellard | #define REGPARM(n) __attribute((regparm(n)))
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50 | e2222c39 | bellard | #else
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51 | e2222c39 | bellard | #define REGPARM(n)
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52 | e2222c39 | bellard | #endif
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53 | e2222c39 | bellard | |
54 | b346ff46 | bellard | /* is_jmp field values */
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55 | b346ff46 | bellard | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
56 | b346ff46 | bellard | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
57 | b346ff46 | bellard | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
58 | b346ff46 | bellard | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
59 | b346ff46 | bellard | |
60 | b346ff46 | bellard | struct TranslationBlock;
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61 | b346ff46 | bellard | |
62 | b346ff46 | bellard | /* XXX: make safe guess about sizes */
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63 | b346ff46 | bellard | #define MAX_OP_PER_INSTR 32 |
64 | b346ff46 | bellard | #define OPC_BUF_SIZE 512 |
65 | b346ff46 | bellard | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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66 | b346ff46 | bellard | |
67 | b346ff46 | bellard | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3) |
68 | b346ff46 | bellard | |
69 | b346ff46 | bellard | extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
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70 | b346ff46 | bellard | extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
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71 | c27004ec | bellard | extern long gen_labels[OPC_BUF_SIZE]; |
72 | c27004ec | bellard | extern int nb_gen_labels; |
73 | c27004ec | bellard | extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
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74 | c27004ec | bellard | extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
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75 | 66e85a21 | bellard | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
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76 | b346ff46 | bellard | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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77 | c3278b7b | bellard | extern target_ulong gen_opc_jump_pc[2]; |
78 | 30d6cb84 | bellard | extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
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79 | b346ff46 | bellard | |
80 | 9886cc16 | bellard | typedef void (GenOpFunc)(void); |
81 | 9886cc16 | bellard | typedef void (GenOpFunc1)(long); |
82 | 9886cc16 | bellard | typedef void (GenOpFunc2)(long, long); |
83 | 9886cc16 | bellard | typedef void (GenOpFunc3)(long, long, long); |
84 | 3b46e624 | ths | |
85 | b346ff46 | bellard | #if defined(TARGET_I386)
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86 | b346ff46 | bellard | |
87 | 33417e70 | bellard | void optimize_flags_init(void); |
88 | d4e8164f | bellard | |
89 | b346ff46 | bellard | #endif
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90 | b346ff46 | bellard | |
91 | b346ff46 | bellard | extern FILE *logfile;
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92 | b346ff46 | bellard | extern int loglevel; |
93 | b346ff46 | bellard | |
94 | 69d35728 | ths | void muls64(int64_t *phigh, int64_t *plow, int64_t a, int64_t b);
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95 | 69d35728 | ths | void mulu64(uint64_t *phigh, uint64_t *plow, uint64_t a, uint64_t b);
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96 | 69d35728 | ths | |
97 | 4c3a88a2 | bellard | int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
98 | 4c3a88a2 | bellard | int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
99 | b346ff46 | bellard | void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf); |
100 | 4c3a88a2 | bellard | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
101 | b346ff46 | bellard | int max_code_size, int *gen_code_size_ptr); |
102 | 5fafdf24 | ths | int cpu_restore_state(struct TranslationBlock *tb, |
103 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
104 | 58fe2f10 | bellard | void *puc);
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105 | 58fe2f10 | bellard | int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb, |
106 | 58fe2f10 | bellard | int max_code_size, int *gen_code_size_ptr); |
107 | 5fafdf24 | ths | int cpu_restore_state_copy(struct TranslationBlock *tb, |
108 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
109 | 58fe2f10 | bellard | void *puc);
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110 | 2e12669a | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc); |
111 | 6a00d601 | bellard | void cpu_exec_init(CPUState *env);
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112 | 53a5960a | pbrook | int page_unprotect(target_ulong address, unsigned long pc, void *puc); |
113 | 5fafdf24 | ths | void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
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114 | 2e12669a | bellard | int is_cpu_write_access);
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115 | 4390df51 | bellard | void tb_invalidate_page_range(target_ulong start, target_ulong end);
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116 | 2e12669a | bellard | void tlb_flush_page(CPUState *env, target_ulong addr);
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117 | ee8b7021 | bellard | void tlb_flush(CPUState *env, int flush_global); |
118 | 5fafdf24 | ths | int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
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119 | 5fafdf24 | ths | target_phys_addr_t paddr, int prot,
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120 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu); |
121 | 5fafdf24 | ths | static inline int tlb_set_page(CPUState *env, target_ulong vaddr, |
122 | 5fafdf24 | ths | target_phys_addr_t paddr, int prot,
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123 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
124 | 84b7b8e7 | bellard | { |
125 | 84b7b8e7 | bellard | if (prot & PAGE_READ)
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126 | 84b7b8e7 | bellard | prot |= PAGE_EXEC; |
127 | 6ebbf390 | j_mayer | return tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
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128 | 84b7b8e7 | bellard | } |
129 | d4e8164f | bellard | |
130 | d4e8164f | bellard | #define CODE_GEN_MAX_SIZE 65536 |
131 | d4e8164f | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
132 | d4e8164f | bellard | |
133 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_BITS 15 |
134 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
135 | 4390df51 | bellard | |
136 | d4e8164f | bellard | /* maximum total translate dcode allocated */
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137 | 4390df51 | bellard | |
138 | 4390df51 | bellard | /* NOTE: the translated code area cannot be too big because on some
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139 | c4c7e3e6 | bellard | archs the range of "fast" function calls is limited. Here is a
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140 | 4390df51 | bellard | summary of the ranges:
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141 | 4390df51 | bellard | |
142 | 4390df51 | bellard | i386 : signed 32 bits
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143 | 4390df51 | bellard | arm : signed 26 bits
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144 | 4390df51 | bellard | ppc : signed 24 bits
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145 | 4390df51 | bellard | sparc : signed 32 bits
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146 | 4390df51 | bellard | alpha : signed 23 bits
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147 | 4390df51 | bellard | */
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148 | 4390df51 | bellard | |
149 | 4390df51 | bellard | #if defined(__alpha__)
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150 | 4390df51 | bellard | #define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024) |
151 | b8076a74 | bellard | #elif defined(__ia64)
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152 | b8076a74 | bellard | #define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */ |
153 | 4390df51 | bellard | #elif defined(__powerpc__)
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154 | c4c7e3e6 | bellard | #define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024) |
155 | 4390df51 | bellard | #else
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156 | c98baaac | bellard | #define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024) |
157 | 4390df51 | bellard | #endif
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158 | 4390df51 | bellard | |
159 | d4e8164f | bellard | //#define CODE_GEN_BUFFER_SIZE (128 * 1024)
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160 | d4e8164f | bellard | |
161 | 4390df51 | bellard | /* estimated block size for TB allocation */
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162 | 4390df51 | bellard | /* XXX: use a per code average code fragment size and modulate it
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163 | 4390df51 | bellard | according to the host CPU */
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164 | 4390df51 | bellard | #if defined(CONFIG_SOFTMMU)
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165 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
166 | 4390df51 | bellard | #else
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167 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
168 | 4390df51 | bellard | #endif
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169 | 4390df51 | bellard | |
170 | 4390df51 | bellard | #define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
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171 | 4390df51 | bellard | |
172 | 5fafdf24 | ths | #if defined(__powerpc__)
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173 | 4390df51 | bellard | #define USE_DIRECT_JUMP
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174 | 4390df51 | bellard | #endif
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175 | 67b915a5 | bellard | #if defined(__i386__) && !defined(_WIN32)
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176 | d4e8164f | bellard | #define USE_DIRECT_JUMP
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177 | d4e8164f | bellard | #endif
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178 | d4e8164f | bellard | |
179 | d4e8164f | bellard | typedef struct TranslationBlock { |
180 | 2e12669a | bellard | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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181 | 2e12669a | bellard | target_ulong cs_base; /* CS base for this block */
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182 | c068688b | j_mayer | uint64_t flags; /* flags defining in which context the code was generated */
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183 | d4e8164f | bellard | uint16_t size; /* size of target code for this block (1 <=
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184 | d4e8164f | bellard | size <= TARGET_PAGE_SIZE) */
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185 | 58fe2f10 | bellard | uint16_t cflags; /* compile flags */
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186 | bf088061 | bellard | #define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */ |
187 | bf088061 | bellard | #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */ |
188 | bf088061 | bellard | #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */ |
189 | 2e12669a | bellard | #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */ |
190 | 58fe2f10 | bellard | |
191 | d4e8164f | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
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192 | 4390df51 | bellard | /* next matching tb for physical address. */
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193 | 5fafdf24 | ths | struct TranslationBlock *phys_hash_next;
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194 | 4390df51 | bellard | /* first and second physical page containing code. The lower bit
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195 | 4390df51 | bellard | of the pointer tells the index in page_next[] */
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196 | 5fafdf24 | ths | struct TranslationBlock *page_next[2]; |
197 | 5fafdf24 | ths | target_ulong page_addr[2];
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198 | 4390df51 | bellard | |
199 | d4e8164f | bellard | /* the following data are used to directly call another TB from
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200 | d4e8164f | bellard | the code of this one. */
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201 | d4e8164f | bellard | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
202 | d4e8164f | bellard | #ifdef USE_DIRECT_JUMP
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203 | 4cbb86e1 | bellard | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
204 | d4e8164f | bellard | #else
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205 | 95f7652d | bellard | uint32_t tb_next[2]; /* address of jump generated code */ |
206 | d4e8164f | bellard | #endif
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207 | d4e8164f | bellard | /* list of TBs jumping to this one. This is a circular list using
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208 | d4e8164f | bellard | the two least significant bits of the pointers to tell what is
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209 | d4e8164f | bellard | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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210 | d4e8164f | bellard | jmp_first */
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211 | 5fafdf24 | ths | struct TranslationBlock *jmp_next[2]; |
212 | d4e8164f | bellard | struct TranslationBlock *jmp_first;
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213 | d4e8164f | bellard | } TranslationBlock; |
214 | d4e8164f | bellard | |
215 | b362e5e0 | pbrook | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
216 | b362e5e0 | pbrook | { |
217 | b362e5e0 | pbrook | target_ulong tmp; |
218 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
219 | b362e5e0 | pbrook | return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
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220 | b362e5e0 | pbrook | } |
221 | b362e5e0 | pbrook | |
222 | 8a40a180 | bellard | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
223 | d4e8164f | bellard | { |
224 | b362e5e0 | pbrook | target_ulong tmp; |
225 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
226 | b362e5e0 | pbrook | return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) |
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227 | b362e5e0 | pbrook | (tmp & TB_JMP_ADDR_MASK)); |
228 | d4e8164f | bellard | } |
229 | d4e8164f | bellard | |
230 | 4390df51 | bellard | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
231 | 4390df51 | bellard | { |
232 | 4390df51 | bellard | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); |
233 | 4390df51 | bellard | } |
234 | 4390df51 | bellard | |
235 | c27004ec | bellard | TranslationBlock *tb_alloc(target_ulong pc); |
236 | 0124311e | bellard | void tb_flush(CPUState *env);
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237 | 5fafdf24 | ths | void tb_link_phys(TranslationBlock *tb,
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238 | 4390df51 | bellard | target_ulong phys_pc, target_ulong phys_page2); |
239 | d4e8164f | bellard | |
240 | 4390df51 | bellard | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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241 | d4e8164f | bellard | |
242 | d4e8164f | bellard | extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
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243 | d4e8164f | bellard | extern uint8_t *code_gen_ptr;
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244 | d4e8164f | bellard | |
245 | 4390df51 | bellard | #if defined(USE_DIRECT_JUMP)
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246 | 4390df51 | bellard | |
247 | 4390df51 | bellard | #if defined(__powerpc__)
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248 | 4cbb86e1 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
249 | d4e8164f | bellard | { |
250 | d4e8164f | bellard | uint32_t val, *ptr; |
251 | d4e8164f | bellard | |
252 | d4e8164f | bellard | /* patch the branch destination */
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253 | 4cbb86e1 | bellard | ptr = (uint32_t *)jmp_addr; |
254 | d4e8164f | bellard | val = *ptr; |
255 | 4cbb86e1 | bellard | val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc); |
256 | d4e8164f | bellard | *ptr = val; |
257 | d4e8164f | bellard | /* flush icache */
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258 | d4e8164f | bellard | asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory"); |
259 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
260 | d4e8164f | bellard | asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory"); |
261 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
262 | d4e8164f | bellard | asm volatile ("isync" : : : "memory"); |
263 | d4e8164f | bellard | } |
264 | 4390df51 | bellard | #elif defined(__i386__)
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265 | 4390df51 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
266 | 4390df51 | bellard | { |
267 | 4390df51 | bellard | /* patch the branch destination */
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268 | 4390df51 | bellard | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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269 | 4390df51 | bellard | /* no need to flush icache explicitely */
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270 | 4390df51 | bellard | } |
271 | 4390df51 | bellard | #endif
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272 | d4e8164f | bellard | |
273 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
274 | 4cbb86e1 | bellard | int n, unsigned long addr) |
275 | 4cbb86e1 | bellard | { |
276 | 4cbb86e1 | bellard | unsigned long offset; |
277 | 4cbb86e1 | bellard | |
278 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n]; |
279 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
280 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n + 2];
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281 | 4cbb86e1 | bellard | if (offset != 0xffff) |
282 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
283 | 4cbb86e1 | bellard | } |
284 | 4cbb86e1 | bellard | |
285 | d4e8164f | bellard | #else
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286 | d4e8164f | bellard | |
287 | d4e8164f | bellard | /* set the jump target */
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288 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
289 | d4e8164f | bellard | int n, unsigned long addr) |
290 | d4e8164f | bellard | { |
291 | 95f7652d | bellard | tb->tb_next[n] = addr; |
292 | d4e8164f | bellard | } |
293 | d4e8164f | bellard | |
294 | d4e8164f | bellard | #endif
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295 | d4e8164f | bellard | |
296 | 5fafdf24 | ths | static inline void tb_add_jump(TranslationBlock *tb, int n, |
297 | d4e8164f | bellard | TranslationBlock *tb_next) |
298 | d4e8164f | bellard | { |
299 | cf25629d | bellard | /* NOTE: this test is only needed for thread safety */
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300 | cf25629d | bellard | if (!tb->jmp_next[n]) {
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301 | cf25629d | bellard | /* patch the native jump address */
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302 | cf25629d | bellard | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
303 | 3b46e624 | ths | |
304 | cf25629d | bellard | /* add in TB jmp circular list */
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305 | cf25629d | bellard | tb->jmp_next[n] = tb_next->jmp_first; |
306 | cf25629d | bellard | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
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307 | cf25629d | bellard | } |
308 | d4e8164f | bellard | } |
309 | d4e8164f | bellard | |
310 | a513fe19 | bellard | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
311 | a513fe19 | bellard | |
312 | d4e8164f | bellard | #ifndef offsetof
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313 | d4e8164f | bellard | #define offsetof(type, field) ((size_t) &((type *)0)->field) |
314 | d4e8164f | bellard | #endif
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315 | d4e8164f | bellard | |
316 | d549f7d9 | bellard | #if defined(_WIN32)
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317 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
318 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".section .text\n" |
319 | d549f7d9 | bellard | #elif defined(__APPLE__)
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320 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".data\n" |
321 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".text\n" |
322 | d549f7d9 | bellard | #else
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323 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
324 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".previous\n" |
325 | d549f7d9 | bellard | #endif
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326 | d549f7d9 | bellard | |
327 | 75913b72 | bellard | #define ASM_OP_LABEL_NAME(n, opname) \
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328 | 75913b72 | bellard | ASM_NAME(__op_label) #n "." ASM_NAME(opname) |
329 | 75913b72 | bellard | |
330 | b346ff46 | bellard | #if defined(__powerpc__)
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331 | b346ff46 | bellard | |
332 | 4390df51 | bellard | /* we patch the jump instruction directly */
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333 | ae063a68 | bellard | #define GOTO_TB(opname, tbparam, n)\
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334 | b346ff46 | bellard | do {\
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335 | d549f7d9 | bellard | asm volatile (ASM_DATA_SECTION\ |
336 | 75913b72 | bellard | ASM_OP_LABEL_NAME(n, opname) ":\n"\
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337 | 9257a9e4 | bellard | ".long 1f\n"\
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338 | d549f7d9 | bellard | ASM_PREVIOUS_SECTION \ |
339 | d549f7d9 | bellard | "b " ASM_NAME(__op_jmp) #n "\n"\ |
340 | 9257a9e4 | bellard | "1:\n");\
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341 | 4390df51 | bellard | } while (0) |
342 | 4390df51 | bellard | |
343 | 4390df51 | bellard | #elif defined(__i386__) && defined(USE_DIRECT_JUMP)
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344 | 4390df51 | bellard | |
345 | 4390df51 | bellard | /* we patch the jump instruction directly */
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346 | ae063a68 | bellard | #define GOTO_TB(opname, tbparam, n)\
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347 | c27004ec | bellard | do {\
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348 | c27004ec | bellard | asm volatile (".section .data\n"\ |
349 | 75913b72 | bellard | ASM_OP_LABEL_NAME(n, opname) ":\n"\
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350 | c27004ec | bellard | ".long 1f\n"\
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351 | c27004ec | bellard | ASM_PREVIOUS_SECTION \ |
352 | c27004ec | bellard | "jmp " ASM_NAME(__op_jmp) #n "\n"\ |
353 | c27004ec | bellard | "1:\n");\
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354 | c27004ec | bellard | } while (0) |
355 | c27004ec | bellard | |
356 | 9bbc5cc8 | ths | #elif defined(__s390__)
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357 | 9bbc5cc8 | ths | /* GCC spills R13, so we have to restore it before branching away */
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358 | 9bbc5cc8 | ths | |
359 | 9bbc5cc8 | ths | #define GOTO_TB(opname, tbparam, n)\
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360 | 9bbc5cc8 | ths | do {\
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361 | 9bbc5cc8 | ths | static void __attribute__((used)) *dummy ## n = &&dummy_label ## n;\ |
362 | 9bbc5cc8 | ths | static void __attribute__((used)) *__op_label ## n \ |
363 | 9bbc5cc8 | ths | __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\ |
364 | 9bbc5cc8 | ths | __asm__ __volatile__ ( \ |
365 | 9bbc5cc8 | ths | "l %%r13,52(%%r15)\n" \
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366 | 9bbc5cc8 | ths | "br %0\n" \
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367 | 9bbc5cc8 | ths | : : "r" (((TranslationBlock*)tbparam)->tb_next[n]));\
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368 | 9bbc5cc8 | ths | \ |
369 | 9bbc5cc8 | ths | for(;*((int*)0);); /* just to keep GCC busy */ \ |
370 | 9bbc5cc8 | ths | label ## n: ;\ |
371 | 9bbc5cc8 | ths | dummy_label ## n: ;\ |
372 | 9bbc5cc8 | ths | } while(0) |
373 | 9bbc5cc8 | ths | |
374 | b346ff46 | bellard | #else
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375 | b346ff46 | bellard | |
376 | b346ff46 | bellard | /* jump to next block operations (more portable code, does not need
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377 | b346ff46 | bellard | cache flushing, but slower because of indirect jump) */
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378 | ae063a68 | bellard | #define GOTO_TB(opname, tbparam, n)\
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379 | b346ff46 | bellard | do {\
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380 | 6d8aa3bf | balrog | static void __attribute__((used)) *dummy ## n = &&dummy_label ## n;\ |
381 | 6d8aa3bf | balrog | static void __attribute__((used)) *__op_label ## n \ |
382 | 75913b72 | bellard | __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\ |
383 | b346ff46 | bellard | goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\ |
384 | ae063a68 | bellard | label ## n: ;\ |
385 | ae063a68 | bellard | dummy_label ## n: ;\ |
386 | b346ff46 | bellard | } while (0) |
387 | b346ff46 | bellard | |
388 | ae063a68 | bellard | #endif
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389 | ae063a68 | bellard | |
390 | 33417e70 | bellard | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
391 | 33417e70 | bellard | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
392 | a4193c8a | bellard | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
393 | 33417e70 | bellard | |
394 | 204a1b8d | ths | #if defined(__powerpc__)
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395 | d4e8164f | bellard | static inline int testandset (int *p) |
396 | d4e8164f | bellard | { |
397 | d4e8164f | bellard | int ret;
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398 | d4e8164f | bellard | __asm__ __volatile__ ( |
399 | 02e1ec9b | bellard | "0: lwarx %0,0,%1\n"
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400 | 02e1ec9b | bellard | " xor. %0,%3,%0\n"
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401 | 02e1ec9b | bellard | " bne 1f\n"
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402 | 02e1ec9b | bellard | " stwcx. %2,0,%1\n"
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403 | 02e1ec9b | bellard | " bne- 0b\n"
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404 | d4e8164f | bellard | "1: "
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405 | d4e8164f | bellard | : "=&r" (ret)
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406 | d4e8164f | bellard | : "r" (p), "r" (1), "r" (0) |
407 | d4e8164f | bellard | : "cr0", "memory"); |
408 | d4e8164f | bellard | return ret;
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409 | d4e8164f | bellard | } |
410 | 204a1b8d | ths | #elif defined(__i386__)
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411 | d4e8164f | bellard | static inline int testandset (int *p) |
412 | d4e8164f | bellard | { |
413 | 4955a2cd | bellard | long int readval = 0; |
414 | 3b46e624 | ths | |
415 | 4955a2cd | bellard | __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
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416 | 4955a2cd | bellard | : "+m" (*p), "+a" (readval) |
417 | 4955a2cd | bellard | : "r" (1) |
418 | 4955a2cd | bellard | : "cc");
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419 | 4955a2cd | bellard | return readval;
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420 | d4e8164f | bellard | } |
421 | 204a1b8d | ths | #elif defined(__x86_64__)
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422 | bc51c5c9 | bellard | static inline int testandset (int *p) |
423 | bc51c5c9 | bellard | { |
424 | 4955a2cd | bellard | long int readval = 0; |
425 | 3b46e624 | ths | |
426 | 4955a2cd | bellard | __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
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427 | 4955a2cd | bellard | : "+m" (*p), "+a" (readval) |
428 | 4955a2cd | bellard | : "r" (1) |
429 | 4955a2cd | bellard | : "cc");
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430 | 4955a2cd | bellard | return readval;
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431 | bc51c5c9 | bellard | } |
432 | 204a1b8d | ths | #elif defined(__s390__)
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433 | d4e8164f | bellard | static inline int testandset (int *p) |
434 | d4e8164f | bellard | { |
435 | d4e8164f | bellard | int ret;
|
436 | d4e8164f | bellard | |
437 | d4e8164f | bellard | __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
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438 | d4e8164f | bellard | " jl 0b"
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439 | d4e8164f | bellard | : "=&d" (ret)
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440 | 5fafdf24 | ths | : "r" (1), "a" (p), "0" (*p) |
441 | d4e8164f | bellard | : "cc", "memory" ); |
442 | d4e8164f | bellard | return ret;
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443 | d4e8164f | bellard | } |
444 | 204a1b8d | ths | #elif defined(__alpha__)
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445 | 2f87c607 | bellard | static inline int testandset (int *p) |
446 | d4e8164f | bellard | { |
447 | d4e8164f | bellard | int ret;
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448 | d4e8164f | bellard | unsigned long one; |
449 | d4e8164f | bellard | |
450 | d4e8164f | bellard | __asm__ __volatile__ ("0: mov 1,%2\n"
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451 | d4e8164f | bellard | " ldl_l %0,%1\n"
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452 | d4e8164f | bellard | " stl_c %2,%1\n"
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453 | d4e8164f | bellard | " beq %2,1f\n"
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454 | d4e8164f | bellard | ".subsection 2\n"
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455 | d4e8164f | bellard | "1: br 0b\n"
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456 | d4e8164f | bellard | ".previous"
|
457 | d4e8164f | bellard | : "=r" (ret), "=m" (*p), "=r" (one) |
458 | d4e8164f | bellard | : "m" (*p));
|
459 | d4e8164f | bellard | return ret;
|
460 | d4e8164f | bellard | } |
461 | 204a1b8d | ths | #elif defined(__sparc__)
|
462 | d4e8164f | bellard | static inline int testandset (int *p) |
463 | d4e8164f | bellard | { |
464 | d4e8164f | bellard | int ret;
|
465 | d4e8164f | bellard | |
466 | d4e8164f | bellard | __asm__ __volatile__("ldstub [%1], %0"
|
467 | d4e8164f | bellard | : "=r" (ret)
|
468 | d4e8164f | bellard | : "r" (p)
|
469 | d4e8164f | bellard | : "memory");
|
470 | d4e8164f | bellard | |
471 | d4e8164f | bellard | return (ret ? 1 : 0); |
472 | d4e8164f | bellard | } |
473 | 204a1b8d | ths | #elif defined(__arm__)
|
474 | a95c6790 | bellard | static inline int testandset (int *spinlock) |
475 | a95c6790 | bellard | { |
476 | a95c6790 | bellard | register unsigned int ret; |
477 | a95c6790 | bellard | __asm__ __volatile__("swp %0, %1, [%2]"
|
478 | a95c6790 | bellard | : "=r"(ret)
|
479 | a95c6790 | bellard | : "0"(1), "r"(spinlock)); |
480 | 3b46e624 | ths | |
481 | a95c6790 | bellard | return ret;
|
482 | a95c6790 | bellard | } |
483 | 204a1b8d | ths | #elif defined(__mc68000)
|
484 | 38e584a0 | bellard | static inline int testandset (int *p) |
485 | 38e584a0 | bellard | { |
486 | 38e584a0 | bellard | char ret;
|
487 | 38e584a0 | bellard | __asm__ __volatile__("tas %1; sne %0"
|
488 | 38e584a0 | bellard | : "=r" (ret)
|
489 | 38e584a0 | bellard | : "m" (p)
|
490 | 38e584a0 | bellard | : "cc","memory"); |
491 | 4955a2cd | bellard | return ret;
|
492 | 38e584a0 | bellard | } |
493 | 204a1b8d | ths | #elif defined(__ia64)
|
494 | 38e584a0 | bellard | |
495 | b8076a74 | bellard | #include <ia64intrin.h> |
496 | b8076a74 | bellard | |
497 | b8076a74 | bellard | static inline int testandset (int *p) |
498 | b8076a74 | bellard | { |
499 | b8076a74 | bellard | return __sync_lock_test_and_set (p, 1); |
500 | b8076a74 | bellard | } |
501 | 204a1b8d | ths | #elif defined(__mips__)
|
502 | c4b89d18 | ths | static inline int testandset (int *p) |
503 | c4b89d18 | ths | { |
504 | c4b89d18 | ths | int ret;
|
505 | c4b89d18 | ths | |
506 | c4b89d18 | ths | __asm__ __volatile__ ( |
507 | c4b89d18 | ths | " .set push \n"
|
508 | c4b89d18 | ths | " .set noat \n"
|
509 | c4b89d18 | ths | " .set mips2 \n"
|
510 | c4b89d18 | ths | "1: li $1, 1 \n"
|
511 | c4b89d18 | ths | " ll %0, %1 \n"
|
512 | c4b89d18 | ths | " sc $1, %1 \n"
|
513 | 976a0d0d | ths | " beqz $1, 1b \n"
|
514 | c4b89d18 | ths | " .set pop "
|
515 | c4b89d18 | ths | : "=r" (ret), "+R" (*p) |
516 | c4b89d18 | ths | : |
517 | c4b89d18 | ths | : "memory");
|
518 | c4b89d18 | ths | |
519 | c4b89d18 | ths | return ret;
|
520 | c4b89d18 | ths | } |
521 | 204a1b8d | ths | #else
|
522 | 204a1b8d | ths | #error unimplemented CPU support
|
523 | c4b89d18 | ths | #endif
|
524 | c4b89d18 | ths | |
525 | d4e8164f | bellard | typedef int spinlock_t; |
526 | d4e8164f | bellard | |
527 | d4e8164f | bellard | #define SPIN_LOCK_UNLOCKED 0 |
528 | d4e8164f | bellard | |
529 | aebcb60e | bellard | #if defined(CONFIG_USER_ONLY)
|
530 | d4e8164f | bellard | static inline void spin_lock(spinlock_t *lock) |
531 | d4e8164f | bellard | { |
532 | d4e8164f | bellard | while (testandset(lock));
|
533 | d4e8164f | bellard | } |
534 | d4e8164f | bellard | |
535 | d4e8164f | bellard | static inline void spin_unlock(spinlock_t *lock) |
536 | d4e8164f | bellard | { |
537 | d4e8164f | bellard | *lock = 0;
|
538 | d4e8164f | bellard | } |
539 | d4e8164f | bellard | |
540 | d4e8164f | bellard | static inline int spin_trylock(spinlock_t *lock) |
541 | d4e8164f | bellard | { |
542 | d4e8164f | bellard | return !testandset(lock);
|
543 | d4e8164f | bellard | } |
544 | 3c1cf9fa | bellard | #else
|
545 | 3c1cf9fa | bellard | static inline void spin_lock(spinlock_t *lock) |
546 | 3c1cf9fa | bellard | { |
547 | 3c1cf9fa | bellard | } |
548 | 3c1cf9fa | bellard | |
549 | 3c1cf9fa | bellard | static inline void spin_unlock(spinlock_t *lock) |
550 | 3c1cf9fa | bellard | { |
551 | 3c1cf9fa | bellard | } |
552 | 3c1cf9fa | bellard | |
553 | 3c1cf9fa | bellard | static inline int spin_trylock(spinlock_t *lock) |
554 | 3c1cf9fa | bellard | { |
555 | 3c1cf9fa | bellard | return 1; |
556 | 3c1cf9fa | bellard | } |
557 | 3c1cf9fa | bellard | #endif
|
558 | d4e8164f | bellard | |
559 | d4e8164f | bellard | extern spinlock_t tb_lock;
|
560 | d4e8164f | bellard | |
561 | 36bdbe54 | bellard | extern int tb_invalidated_flag; |
562 | 6e59c1db | bellard | |
563 | e95c8d51 | bellard | #if !defined(CONFIG_USER_ONLY)
|
564 | 6e59c1db | bellard | |
565 | 6ebbf390 | j_mayer | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, |
566 | 6e59c1db | bellard | void *retaddr);
|
567 | 6e59c1db | bellard | |
568 | 6ebbf390 | j_mayer | #define ACCESS_TYPE (NB_MMU_MODES + 1) |
569 | 6e59c1db | bellard | #define MEMSUFFIX _code
|
570 | 6e59c1db | bellard | #define env cpu_single_env
|
571 | 6e59c1db | bellard | |
572 | 6e59c1db | bellard | #define DATA_SIZE 1 |
573 | 6e59c1db | bellard | #include "softmmu_header.h" |
574 | 6e59c1db | bellard | |
575 | 6e59c1db | bellard | #define DATA_SIZE 2 |
576 | 6e59c1db | bellard | #include "softmmu_header.h" |
577 | 6e59c1db | bellard | |
578 | 6e59c1db | bellard | #define DATA_SIZE 4 |
579 | 6e59c1db | bellard | #include "softmmu_header.h" |
580 | 6e59c1db | bellard | |
581 | c27004ec | bellard | #define DATA_SIZE 8 |
582 | c27004ec | bellard | #include "softmmu_header.h" |
583 | c27004ec | bellard | |
584 | 6e59c1db | bellard | #undef ACCESS_TYPE
|
585 | 6e59c1db | bellard | #undef MEMSUFFIX
|
586 | 6e59c1db | bellard | #undef env
|
587 | 6e59c1db | bellard | |
588 | 6e59c1db | bellard | #endif
|
589 | 4390df51 | bellard | |
590 | 4390df51 | bellard | #if defined(CONFIG_USER_ONLY)
|
591 | 4390df51 | bellard | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
592 | 4390df51 | bellard | { |
593 | 4390df51 | bellard | return addr;
|
594 | 4390df51 | bellard | } |
595 | 4390df51 | bellard | #else
|
596 | 4390df51 | bellard | /* NOTE: this function can trigger an exception */
|
597 | 1ccde1cb | bellard | /* NOTE2: the returned address is not exactly the physical address: it
|
598 | 1ccde1cb | bellard | is the offset relative to phys_ram_base */
|
599 | 4390df51 | bellard | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
600 | 4390df51 | bellard | { |
601 | 6ebbf390 | j_mayer | int mmu_idx, index, pd;
|
602 | 4390df51 | bellard | |
603 | 4390df51 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
604 | 6ebbf390 | j_mayer | mmu_idx = cpu_mmu_index(env); |
605 | 6ebbf390 | j_mayer | if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_code !=
|
606 | 4390df51 | bellard | (addr & TARGET_PAGE_MASK), 0)) {
|
607 | c27004ec | bellard | ldub_code(addr); |
608 | c27004ec | bellard | } |
609 | 6ebbf390 | j_mayer | pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK; |
610 | 2a4188a3 | bellard | if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
|
611 | 647de6ca | ths | #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
|
612 | 6c36d3fa | blueswir1 | do_unassigned_access(addr, 0, 1, 0); |
613 | 6c36d3fa | blueswir1 | #else
|
614 | 36d23958 | ths | cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); |
615 | 6c36d3fa | blueswir1 | #endif
|
616 | 4390df51 | bellard | } |
617 | 6ebbf390 | j_mayer | return addr + env->tlb_table[mmu_idx][index].addend - (unsigned long)phys_ram_base; |
618 | 4390df51 | bellard | } |
619 | 4390df51 | bellard | #endif
|
620 | 9df217a3 | bellard | |
621 | 9df217a3 | bellard | #ifdef USE_KQEMU
|
622 | f32fc648 | bellard | #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG)) |
623 | f32fc648 | bellard | |
624 | 9df217a3 | bellard | int kqemu_init(CPUState *env);
|
625 | 9df217a3 | bellard | int kqemu_cpu_exec(CPUState *env);
|
626 | 9df217a3 | bellard | void kqemu_flush_page(CPUState *env, target_ulong addr);
|
627 | 9df217a3 | bellard | void kqemu_flush(CPUState *env, int global); |
628 | 4b7df22f | bellard | void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
|
629 | f32fc648 | bellard | void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
|
630 | a332e112 | bellard | void kqemu_cpu_interrupt(CPUState *env);
|
631 | f32fc648 | bellard | void kqemu_record_dump(void); |
632 | 9df217a3 | bellard | |
633 | 9df217a3 | bellard | static inline int kqemu_is_ok(CPUState *env) |
634 | 9df217a3 | bellard | { |
635 | 9df217a3 | bellard | return(env->kqemu_enabled &&
|
636 | 5fafdf24 | ths | (env->cr[0] & CR0_PE_MASK) &&
|
637 | f32fc648 | bellard | !(env->hflags & HF_INHIBIT_IRQ_MASK) && |
638 | 9df217a3 | bellard | (env->eflags & IF_MASK) && |
639 | f32fc648 | bellard | !(env->eflags & VM_MASK) && |
640 | 5fafdf24 | ths | (env->kqemu_enabled == 2 ||
|
641 | f32fc648 | bellard | ((env->hflags & HF_CPL_MASK) == 3 &&
|
642 | f32fc648 | bellard | (env->eflags & IOPL_MASK) != IOPL_MASK))); |
643 | 9df217a3 | bellard | } |
644 | 9df217a3 | bellard | |
645 | 9df217a3 | bellard | #endif |