Revision 64adab3f
| b/cpu-exec.c | ||
|---|---|---|
| 918 | 918 |
/* we restore the process signal mask as the sigreturn should |
| 919 | 919 |
do it (XXX: use sigsetjmp) */ |
| 920 | 920 |
sigprocmask(SIG_SETMASK, old_set, NULL); |
| 921 |
do_raise_exception_err(env->exception_index, env->error_code);
|
|
| 921 |
raise_exception_err(env, env->exception_index, env->error_code);
|
|
| 922 | 922 |
} else {
|
| 923 | 923 |
/* activate soft MMU for this block */ |
| 924 | 924 |
cpu_resume_from_signal(env, puc); |
| b/target-ppc/exec.h | ||
|---|---|---|
| 94 | 94 |
#include "softmmu_exec.h" |
| 95 | 95 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
| 96 | 96 |
|
| 97 |
void do_raise_exception_err (uint32_t exception, int error_code);
|
|
| 98 |
void do_raise_exception (uint32_t exception);
|
|
| 97 |
void raise_exception_err (CPUState *env, int exception, int error_code);
|
|
| 98 |
void raise_exception (CPUState *env, int exception);
|
|
| 99 | 99 |
|
| 100 | 100 |
int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong vaddr, |
| 101 | 101 |
int rw, int access_type); |
| b/target-ppc/helper.c | ||
|---|---|---|
| 40 | 40 |
//#define FLUSH_ALL_TLBS |
| 41 | 41 |
|
| 42 | 42 |
/*****************************************************************************/ |
| 43 |
/* Exceptions processing */ |
|
| 44 |
|
|
| 45 |
void raise_exception_err (CPUState *env, int exception, int error_code) |
|
| 46 |
{
|
|
| 47 |
#if 0 |
|
| 48 |
printf("Raise exception %3x code : %d\n", exception, error_code);
|
|
| 49 |
#endif |
|
| 50 |
env->exception_index = exception; |
|
| 51 |
env->error_code = error_code; |
|
| 52 |
cpu_loop_exit(); |
|
| 53 |
} |
|
| 54 |
|
|
| 55 |
void raise_exception (CPUState *env, int exception) |
|
| 56 |
{
|
|
| 57 |
helper_raise_exception_err(exception, 0); |
|
| 58 |
} |
|
| 59 |
|
|
| 60 |
/*****************************************************************************/ |
|
| 43 | 61 |
/* PowerPC MMU emulation */ |
| 44 | 62 |
|
| 45 | 63 |
#if defined(CONFIG_USER_ONLY) |
| b/target-ppc/helper.h | ||
|---|---|---|
| 1 | 1 |
#include "def-helper.h" |
| 2 | 2 |
|
| 3 |
DEF_HELPER_2(raise_exception_err, void, i32, i32) |
|
| 4 |
DEF_HELPER_0(raise_debug, void) |
|
| 5 |
|
|
| 3 | 6 |
DEF_HELPER_2(fcmpo, i32, i64, i64) |
| 4 | 7 |
DEF_HELPER_2(fcmpu, i32, i64, i64) |
| 5 | 8 |
|
| b/target-ppc/op.c | ||
|---|---|---|
| 26 | 26 |
#include "helper_regs.h" |
| 27 | 27 |
#include "op_helper.h" |
| 28 | 28 |
|
| 29 |
/* Generate exceptions */ |
|
| 30 |
void OPPROTO op_raise_exception_err (void) |
|
| 31 |
{
|
|
| 32 |
do_raise_exception_err(PARAM1, PARAM2); |
|
| 33 |
} |
|
| 34 |
|
|
| 35 |
void OPPROTO op_debug (void) |
|
| 36 |
{
|
|
| 37 |
do_raise_exception(EXCP_DEBUG); |
|
| 38 |
} |
|
| 39 |
|
|
| 40 | 29 |
#if !defined(CONFIG_USER_ONLY) |
| 41 | 30 |
/* Segment registers load and store */ |
| 42 | 31 |
void OPPROTO op_load_sr (void) |
| b/target-ppc/op_helper.c | ||
|---|---|---|
| 46 | 46 |
/*****************************************************************************/ |
| 47 | 47 |
/* Exceptions processing helpers */ |
| 48 | 48 |
|
| 49 |
void do_raise_exception_err (uint32_t exception, int error_code)
|
|
| 49 |
void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
|
|
| 50 | 50 |
{
|
| 51 |
#if 0 |
|
| 52 |
printf("Raise exception %3x code : %d\n", exception, error_code);
|
|
| 53 |
#endif |
|
| 54 |
env->exception_index = exception; |
|
| 55 |
env->error_code = error_code; |
|
| 56 |
cpu_loop_exit(); |
|
| 51 |
raise_exception_err(env, exception, error_code); |
|
| 57 | 52 |
} |
| 58 | 53 |
|
| 59 |
void do_raise_exception (uint32_t exception)
|
|
| 54 |
void helper_raise_debug (void)
|
|
| 60 | 55 |
{
|
| 61 |
do_raise_exception_err(exception, 0);
|
|
| 56 |
raise_exception(env, EXCP_DEBUG);
|
|
| 62 | 57 |
} |
| 63 | 58 |
|
| 59 |
|
|
| 64 | 60 |
/*****************************************************************************/ |
| 65 | 61 |
/* Registers load and stores */ |
| 66 | 62 |
target_ulong helper_load_cr (void) |
| ... | ... | |
| 430 | 426 |
/* Update the floating-point enabled exception summary */ |
| 431 | 427 |
env->fpscr |= 1 << FPSCR_FEX; |
| 432 | 428 |
if (msr_fe0 != 0 || msr_fe1 != 0) |
| 433 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
|
|
| 429 |
raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
|
|
| 434 | 430 |
} |
| 435 | 431 |
return ret; |
| 436 | 432 |
} |
| ... | ... | |
| 445 | 441 |
/* Update the floating-point enabled exception summary */ |
| 446 | 442 |
env->fpscr |= 1 << FPSCR_FEX; |
| 447 | 443 |
if (msr_fe0 != 0 || msr_fe1 != 0) {
|
| 448 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM,
|
|
| 449 |
POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
|
|
| 444 |
raise_exception_err(env, POWERPC_EXCP_PROGRAM,
|
|
| 445 |
POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX); |
|
| 450 | 446 |
} |
| 451 | 447 |
} else {
|
| 452 | 448 |
/* Set the result to infinity */ |
| ... | ... | |
| 686 | 682 |
(env->error_code & POWERPC_EXCP_FP)) {
|
| 687 | 683 |
/* Differred floating-point exception after target FPR update */ |
| 688 | 684 |
if (msr_fe0 != 0 || msr_fe1 != 0) |
| 689 |
do_raise_exception_err(env->exception_index, env->error_code);
|
|
| 685 |
raise_exception_err(env, env->exception_index, env->error_code);
|
|
| 690 | 686 |
} else if (env->fp_status.float_exception_flags & float_flag_overflow) {
|
| 691 | 687 |
float_overflow_excp(); |
| 692 | 688 |
} else if (env->fp_status.float_exception_flags & float_flag_underflow) {
|
| ... | ... | |
| 699 | 695 |
(env->error_code & POWERPC_EXCP_FP)) {
|
| 700 | 696 |
/* Differred floating-point exception after target FPR update */ |
| 701 | 697 |
if (msr_fe0 != 0 || msr_fe1 != 0) |
| 702 |
do_raise_exception_err(env->exception_index, env->error_code);
|
|
| 698 |
raise_exception_err(env, env->exception_index, env->error_code);
|
|
| 703 | 699 |
} |
| 704 | 700 |
RETURN(); |
| 705 | 701 |
#endif |
| ... | ... | |
| 1356 | 1352 |
T0 = hreg_store_msr(env, T0, 0); |
| 1357 | 1353 |
if (T0 != 0) {
|
| 1358 | 1354 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
| 1359 |
do_raise_exception(T0);
|
|
| 1355 |
raise_exception(env, T0);
|
|
| 1360 | 1356 |
} |
| 1361 | 1357 |
} |
| 1362 | 1358 |
|
| ... | ... | |
| 1417 | 1413 |
((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) || |
| 1418 | 1414 |
((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) || |
| 1419 | 1415 |
((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) {
|
| 1420 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
|
|
| 1416 |
raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
|
|
| 1421 | 1417 |
} |
| 1422 | 1418 |
} |
| 1423 | 1419 |
|
| ... | ... | |
| 1429 | 1425 |
((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) || |
| 1430 | 1426 |
((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) || |
| 1431 | 1427 |
((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01))))) |
| 1432 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
|
|
| 1428 |
raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
|
|
| 1433 | 1429 |
} |
| 1434 | 1430 |
#endif |
| 1435 | 1431 |
|
| ... | ... | |
| 1670 | 1666 |
if (loglevel != 0) {
|
| 1671 | 1667 |
fprintf(logfile, "No DCR environment\n"); |
| 1672 | 1668 |
} |
| 1673 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM,
|
|
| 1674 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
|
|
| 1669 |
raise_exception_err(env, POWERPC_EXCP_PROGRAM,
|
|
| 1670 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); |
|
| 1675 | 1671 |
} else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
|
| 1676 | 1672 |
if (loglevel != 0) {
|
| 1677 | 1673 |
fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0); |
| 1678 | 1674 |
} |
| 1679 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM,
|
|
| 1680 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
|
|
| 1675 |
raise_exception_err(env, POWERPC_EXCP_PROGRAM,
|
|
| 1676 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG); |
|
| 1681 | 1677 |
} else {
|
| 1682 | 1678 |
T0 = val; |
| 1683 | 1679 |
} |
| ... | ... | |
| 1689 | 1685 |
if (loglevel != 0) {
|
| 1690 | 1686 |
fprintf(logfile, "No DCR environment\n"); |
| 1691 | 1687 |
} |
| 1692 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM,
|
|
| 1693 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
|
|
| 1688 |
raise_exception_err(env, POWERPC_EXCP_PROGRAM,
|
|
| 1689 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); |
|
| 1694 | 1690 |
} else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
|
| 1695 | 1691 |
if (loglevel != 0) {
|
| 1696 | 1692 |
fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0); |
| 1697 | 1693 |
} |
| 1698 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM,
|
|
| 1699 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
|
|
| 1694 |
raise_exception_err(env, POWERPC_EXCP_PROGRAM,
|
|
| 1695 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG); |
|
| 1700 | 1696 |
} |
| 1701 | 1697 |
} |
| 1702 | 1698 |
|
| ... | ... | |
| 2454 | 2450 |
cpu_restore_state(tb, env, pc, NULL); |
| 2455 | 2451 |
} |
| 2456 | 2452 |
} |
| 2457 |
do_raise_exception_err(env->exception_index, env->error_code);
|
|
| 2453 |
raise_exception_err(env, env->exception_index, env->error_code);
|
|
| 2458 | 2454 |
} |
| 2459 | 2455 |
env = saved_env; |
| 2460 | 2456 |
} |
| b/target-ppc/op_mem.h | ||
|---|---|---|
| 103 | 103 |
if (likely(T1 != 0)) {
|
| 104 | 104 |
if (unlikely((PARAM1 < PARAM2 && (PARAM1 + T1) > PARAM2) || |
| 105 | 105 |
(PARAM1 < PARAM3 && (PARAM1 + T1) > PARAM3))) {
|
| 106 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM,
|
|
| 107 |
POWERPC_EXCP_INVAL |
|
|
| 108 |
POWERPC_EXCP_INVAL_LSWX);
|
|
| 106 |
raise_exception_err(env, POWERPC_EXCP_PROGRAM,
|
|
| 107 |
POWERPC_EXCP_INVAL | |
|
| 108 |
POWERPC_EXCP_INVAL_LSWX); |
|
| 109 | 109 |
} else {
|
| 110 | 110 |
glue(do_lsw, MEMSUFFIX)(PARAM1); |
| 111 | 111 |
} |
| ... | ... | |
| 120 | 120 |
if (likely(T1 != 0)) {
|
| 121 | 121 |
if (unlikely((PARAM1 < PARAM2 && (PARAM1 + T1) > PARAM2) || |
| 122 | 122 |
(PARAM1 < PARAM3 && (PARAM1 + T1) > PARAM3))) {
|
| 123 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM,
|
|
| 124 |
POWERPC_EXCP_INVAL |
|
|
| 125 |
POWERPC_EXCP_INVAL_LSWX);
|
|
| 123 |
raise_exception_err(env, POWERPC_EXCP_PROGRAM,
|
|
| 124 |
POWERPC_EXCP_INVAL | |
|
| 125 |
POWERPC_EXCP_INVAL_LSWX); |
|
| 126 | 126 |
} else {
|
| 127 | 127 |
glue(do_lsw_64, MEMSUFFIX)(PARAM1); |
| 128 | 128 |
} |
| ... | ... | |
| 282 | 282 |
void OPPROTO glue(op_lwarx, MEMSUFFIX) (void) |
| 283 | 283 |
{
|
| 284 | 284 |
if (unlikely(T0 & 0x03)) {
|
| 285 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 285 |
raise_exception(env, POWERPC_EXCP_ALIGN);
|
|
| 286 | 286 |
} else {
|
| 287 | 287 |
T1 = glue(ldu32, MEMSUFFIX)((uint32_t)T0); |
| 288 | 288 |
env->reserve = (uint32_t)T0; |
| ... | ... | |
| 294 | 294 |
void OPPROTO glue(op_lwarx_64, MEMSUFFIX) (void) |
| 295 | 295 |
{
|
| 296 | 296 |
if (unlikely(T0 & 0x03)) {
|
| 297 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 297 |
raise_exception(env, POWERPC_EXCP_ALIGN);
|
|
| 298 | 298 |
} else {
|
| 299 | 299 |
T1 = glue(ldu32, MEMSUFFIX)((uint64_t)T0); |
| 300 | 300 |
env->reserve = (uint64_t)T0; |
| ... | ... | |
| 305 | 305 |
void OPPROTO glue(op_ldarx, MEMSUFFIX) (void) |
| 306 | 306 |
{
|
| 307 | 307 |
if (unlikely(T0 & 0x03)) {
|
| 308 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 308 |
raise_exception(env, POWERPC_EXCP_ALIGN);
|
|
| 309 | 309 |
} else {
|
| 310 | 310 |
T1 = glue(ldu64, MEMSUFFIX)((uint32_t)T0); |
| 311 | 311 |
env->reserve = (uint32_t)T0; |
| ... | ... | |
| 316 | 316 |
void OPPROTO glue(op_ldarx_64, MEMSUFFIX) (void) |
| 317 | 317 |
{
|
| 318 | 318 |
if (unlikely(T0 & 0x03)) {
|
| 319 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 319 |
raise_exception(env, POWERPC_EXCP_ALIGN);
|
|
| 320 | 320 |
} else {
|
| 321 | 321 |
T1 = glue(ldu64, MEMSUFFIX)((uint64_t)T0); |
| 322 | 322 |
env->reserve = (uint64_t)T0; |
| ... | ... | |
| 328 | 328 |
void OPPROTO glue(op_lwarx_le, MEMSUFFIX) (void) |
| 329 | 329 |
{
|
| 330 | 330 |
if (unlikely(T0 & 0x03)) {
|
| 331 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 331 |
raise_exception(env, POWERPC_EXCP_ALIGN);
|
|
| 332 | 332 |
} else {
|
| 333 | 333 |
T1 = glue(ldu32r, MEMSUFFIX)((uint32_t)T0); |
| 334 | 334 |
env->reserve = (uint32_t)T0; |
| ... | ... | |
| 340 | 340 |
void OPPROTO glue(op_lwarx_le_64, MEMSUFFIX) (void) |
| 341 | 341 |
{
|
| 342 | 342 |
if (unlikely(T0 & 0x03)) {
|
| 343 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 343 |
raise_exception(env, POWERPC_EXCP_ALIGN);
|
|
| 344 | 344 |
} else {
|
| 345 | 345 |
T1 = glue(ldu32r, MEMSUFFIX)((uint64_t)T0); |
| 346 | 346 |
env->reserve = (uint64_t)T0; |
| ... | ... | |
| 351 | 351 |
void OPPROTO glue(op_ldarx_le, MEMSUFFIX) (void) |
| 352 | 352 |
{
|
| 353 | 353 |
if (unlikely(T0 & 0x03)) {
|
| 354 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 354 |
raise_exception(env, POWERPC_EXCP_ALIGN);
|
|
| 355 | 355 |
} else {
|
| 356 | 356 |
T1 = glue(ldu64r, MEMSUFFIX)((uint32_t)T0); |
| 357 | 357 |
env->reserve = (uint32_t)T0; |
| ... | ... | |
| 362 | 362 |
void OPPROTO glue(op_ldarx_le_64, MEMSUFFIX) (void) |
| 363 | 363 |
{
|
| 364 | 364 |
if (unlikely(T0 & 0x03)) {
|
| 365 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 365 |
raise_exception(env, POWERPC_EXCP_ALIGN);
|
|
| 366 | 366 |
} else {
|
| 367 | 367 |
T1 = glue(ldu64r, MEMSUFFIX)((uint64_t)T0); |
| 368 | 368 |
env->reserve = (uint64_t)T0; |
| ... | ... | |
| 375 | 375 |
void OPPROTO glue(op_stwcx, MEMSUFFIX) (void) |
| 376 | 376 |
{
|
| 377 | 377 |
if (unlikely(T0 & 0x03)) {
|
| 378 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 378 |
raise_exception(env, POWERPC_EXCP_ALIGN);
|
|
| 379 | 379 |
} else {
|
| 380 | 380 |
if (unlikely(env->reserve != (uint32_t)T0)) {
|
| 381 | 381 |
env->crf[0] = xer_so; |
| ... | ... | |
| 392 | 392 |
void OPPROTO glue(op_stwcx_64, MEMSUFFIX) (void) |
| 393 | 393 |
{
|
| 394 | 394 |
if (unlikely(T0 & 0x03)) {
|
| 395 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 395 |
raise_exception(env, POWERPC_EXCP_ALIGN);
|
|
| 396 | 396 |
} else {
|
| 397 | 397 |
if (unlikely(env->reserve != (uint64_t)T0)) {
|
| 398 | 398 |
env->crf[0] = xer_so; |
| ... | ... | |
| 408 | 408 |
void OPPROTO glue(op_stdcx, MEMSUFFIX) (void) |
| 409 | 409 |
{
|
| 410 | 410 |
if (unlikely(T0 & 0x03)) {
|
| 411 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 411 |
raise_exception(env, POWERPC_EXCP_ALIGN);
|
|
| 412 | 412 |
} else {
|
| 413 | 413 |
if (unlikely(env->reserve != (uint32_t)T0)) {
|
| 414 | 414 |
env->crf[0] = xer_so; |
| ... | ... | |
| 424 | 424 |
void OPPROTO glue(op_stdcx_64, MEMSUFFIX) (void) |
| 425 | 425 |
{
|
| 426 | 426 |
if (unlikely(T0 & 0x03)) {
|
| 427 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 427 |
raise_exception(env, POWERPC_EXCP_ALIGN);
|
|
| 428 | 428 |
} else {
|
| 429 | 429 |
if (unlikely(env->reserve != (uint64_t)T0)) {
|
| 430 | 430 |
env->crf[0] = xer_so; |
| ... | ... | |
| 441 | 441 |
void OPPROTO glue(op_stwcx_le, MEMSUFFIX) (void) |
| 442 | 442 |
{
|
| 443 | 443 |
if (unlikely(T0 & 0x03)) {
|
| 444 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 444 |
raise_exception(env, POWERPC_EXCP_ALIGN);
|
|
| 445 | 445 |
} else {
|
| 446 | 446 |
if (unlikely(env->reserve != (uint32_t)T0)) {
|
| 447 | 447 |
env->crf[0] = xer_so; |
| ... | ... | |
| 458 | 458 |
void OPPROTO glue(op_stwcx_le_64, MEMSUFFIX) (void) |
| 459 | 459 |
{
|
| 460 | 460 |
if (unlikely(T0 & 0x03)) {
|
| 461 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 461 |
raise_exception(env, POWERPC_EXCP_ALIGN);
|
|
| 462 | 462 |
} else {
|
| 463 | 463 |
if (unlikely(env->reserve != (uint64_t)T0)) {
|
| 464 | 464 |
env->crf[0] = xer_so; |
| ... | ... | |
| 474 | 474 |
void OPPROTO glue(op_stdcx_le, MEMSUFFIX) (void) |
| 475 | 475 |
{
|
| 476 | 476 |
if (unlikely(T0 & 0x03)) {
|
| 477 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 477 |
raise_exception(env, POWERPC_EXCP_ALIGN);
|
|
| 478 | 478 |
} else {
|
| 479 | 479 |
if (unlikely(env->reserve != (uint32_t)T0)) {
|
| 480 | 480 |
env->crf[0] = xer_so; |
| ... | ... | |
| 490 | 490 |
void OPPROTO glue(op_stdcx_le_64, MEMSUFFIX) (void) |
| 491 | 491 |
{
|
| 492 | 492 |
if (unlikely(T0 & 0x03)) {
|
| 493 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 493 |
raise_exception(env, POWERPC_EXCP_ALIGN);
|
|
| 494 | 494 |
} else {
|
| 495 | 495 |
if (unlikely(env->reserve != (uint64_t)T0)) {
|
| 496 | 496 |
env->crf[0] = xer_so; |
| b/target-ppc/translate.c | ||
|---|---|---|
| 293 | 293 |
|
| 294 | 294 |
#define GEN_EXCP(ctx, excp, error) \ |
| 295 | 295 |
do { \
|
| 296 |
TCGv_i32 t0 = tcg_const_i32(excp); \ |
|
| 297 |
TCGv_i32 t1 = tcg_const_i32(error); \ |
|
| 296 | 298 |
if ((ctx)->exception == POWERPC_EXCP_NONE) { \
|
| 297 | 299 |
gen_update_nip(ctx, (ctx)->nip); \ |
| 298 | 300 |
} \ |
| 299 |
gen_op_raise_exception_err((excp), (error)); \ |
|
| 301 |
gen_helper_raise_exception_err(t0, t1); \ |
|
| 302 |
tcg_temp_free_i32(t0); \ |
|
| 303 |
tcg_temp_free_i32(t1); \ |
|
| 300 | 304 |
ctx->exception = (excp); \ |
| 301 | 305 |
} while (0) |
| 302 | 306 |
|
| ... | ... | |
| 3470 | 3474 |
} |
| 3471 | 3475 |
if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
|
| 3472 | 3476 |
gen_update_nip(ctx, dest); |
| 3473 |
gen_op_debug();
|
|
| 3477 |
gen_helper_raise_debug();
|
|
| 3474 | 3478 |
} |
| 3475 | 3479 |
} |
| 3476 | 3480 |
tcg_gen_exit_tb(0); |
| ... | ... | |
| 7233 | 7237 |
for (bp = env->breakpoints; bp != NULL; bp = bp->next) {
|
| 7234 | 7238 |
if (bp->pc == ctx.nip) {
|
| 7235 | 7239 |
gen_update_nip(&ctx, ctx.nip); |
| 7236 |
gen_op_debug();
|
|
| 7240 |
gen_helper_raise_debug();
|
|
| 7237 | 7241 |
break; |
| 7238 | 7242 |
} |
| 7239 | 7243 |
} |
| ... | ... | |
| 7344 | 7348 |
} else if (ctx.exception != POWERPC_EXCP_BRANCH) {
|
| 7345 | 7349 |
if (unlikely(env->singlestep_enabled)) {
|
| 7346 | 7350 |
gen_update_nip(&ctx, ctx.nip); |
| 7347 |
gen_op_debug();
|
|
| 7351 |
gen_helper_raise_debug();
|
|
| 7348 | 7352 |
} |
| 7349 | 7353 |
/* Generate the return instruction */ |
| 7350 | 7354 |
tcg_gen_exit_tb(0); |
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