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/*
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* QEMU KVM support
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*
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* Copyright (C) 2006-2008 Qumranet Technologies
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* Copyright IBM, Corp. 2008
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*
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* Authors:
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* Anthony Liguori <aliguori@us.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include <sys/types.h> |
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#include <sys/ioctl.h> |
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#include <sys/mman.h> |
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#include <linux/kvm.h> |
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#include "qemu-common.h" |
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#include "sysemu.h" |
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#include "kvm.h" |
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#include "cpu.h" |
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#include "gdbstub.h" |
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//#define DEBUG_KVM
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#ifdef DEBUG_KVM
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#define dprintf(fmt, ...) \
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do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
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#else
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#define dprintf(fmt, ...) \
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do { } while (0) |
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#endif
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int kvm_arch_init_vcpu(CPUState *env)
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{ |
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struct {
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struct kvm_cpuid2 cpuid;
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struct kvm_cpuid_entry2 entries[100]; |
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} __attribute__((packed)) cpuid_data; |
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uint32_t limit, i, j, cpuid_i; |
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uint32_t eax, ebx, ecx, edx; |
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cpuid_i = 0;
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cpu_x86_cpuid(env, 0, 0, &eax, &ebx, &ecx, &edx); |
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limit = eax; |
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for (i = 0; i <= limit; i++) { |
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struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
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switch (i) {
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case 2: { |
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/* Keep reading function 2 till all the input is received */
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int times;
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cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
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times = eax & 0xff;
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c->function = i; |
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c->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; |
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c->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; |
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c->eax = eax; |
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c->ebx = ebx; |
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c->ecx = ecx; |
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c->edx = edx; |
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for (j = 1; j < times; ++j) { |
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cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
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c->function = i; |
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c->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; |
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c->eax = eax; |
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c->ebx = ebx; |
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c->ecx = ecx; |
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c->edx = edx; |
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c = &cpuid_data.entries[++cpuid_i]; |
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} |
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break;
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} |
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case 4: |
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case 0xb: |
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case 0xd: |
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for (j = 0; ; j++) { |
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cpu_x86_cpuid(env, i, j, &eax, &ebx, &ecx, &edx); |
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c->function = i; |
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c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
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c->index = j; |
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c->eax = eax; |
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c->ebx = ebx; |
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c->ecx = ecx; |
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c->edx = edx; |
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c = &cpuid_data.entries[++cpuid_i]; |
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if (i == 4 && eax == 0) |
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break;
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if (i == 0xb && !(ecx & 0xff00)) |
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break;
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if (i == 0xd && eax == 0) |
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break;
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} |
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break;
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default:
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cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
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c->function = i; |
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c->eax = eax; |
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c->ebx = ebx; |
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c->ecx = ecx; |
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c->edx = edx; |
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break;
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} |
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} |
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cpu_x86_cpuid(env, 0x80000000, 0, &eax, &ebx, &ecx, &edx); |
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limit = eax; |
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for (i = 0x80000000; i <= limit; i++) { |
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struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
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cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
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c->function = i; |
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c->eax = eax; |
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c->ebx = ebx; |
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c->ecx = ecx; |
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c->edx = edx; |
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} |
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cpuid_data.cpuid.nent = cpuid_i; |
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return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
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} |
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static int kvm_has_msr_star(CPUState *env) |
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{ |
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static int has_msr_star; |
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int ret;
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/* first time */
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if (has_msr_star == 0) { |
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struct kvm_msr_list msr_list, *kvm_msr_list;
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has_msr_star = -1;
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/* Obtain MSR list from KVM. These are the MSRs that we must
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* save/restore */
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msr_list.nmsrs = 0;
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ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list); |
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if (ret < 0) |
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return 0; |
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kvm_msr_list = qemu_mallocz(sizeof(msr_list) +
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msr_list.nmsrs * sizeof(msr_list.indices[0])); |
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kvm_msr_list->nmsrs = msr_list.nmsrs; |
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ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); |
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if (ret >= 0) { |
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int i;
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for (i = 0; i < kvm_msr_list->nmsrs; i++) { |
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if (kvm_msr_list->indices[i] == MSR_STAR) {
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has_msr_star = 1;
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break;
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} |
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} |
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} |
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free(kvm_msr_list); |
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} |
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if (has_msr_star == 1) |
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return 1; |
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return 0; |
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} |
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int kvm_arch_init(KVMState *s, int smp_cpus) |
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{ |
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int ret;
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/* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code
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* directly. In order to use vm86 mode, a TSS is needed. Since this
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* must be part of guest physical memory, we need to allocate it. Older
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* versions of KVM just assumed that it would be at the end of physical
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* memory but that doesn't work with more than 4GB of memory. We simply
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* refuse to work with those older versions of KVM. */
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ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR); |
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if (ret <= 0) { |
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fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
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return ret;
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} |
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/* this address is 3 pages before the bios, and the bios should present
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* as unavaible memory. FIXME, need to ensure the e820 map deals with
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* this?
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*/
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return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000); |
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} |
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static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) |
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{ |
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lhs->selector = rhs->selector; |
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lhs->base = rhs->base; |
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lhs->limit = rhs->limit; |
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lhs->type = 3;
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lhs->present = 1;
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lhs->dpl = 3;
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lhs->db = 0;
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lhs->s = 1;
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lhs->l = 0;
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lhs->g = 0;
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lhs->avl = 0;
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lhs->unusable = 0;
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} |
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static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) |
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{ |
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unsigned flags = rhs->flags;
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lhs->selector = rhs->selector; |
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lhs->base = rhs->base; |
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lhs->limit = rhs->limit; |
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lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
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lhs->present = (flags & DESC_P_MASK) != 0;
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lhs->dpl = rhs->selector & 3;
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lhs->db = (flags >> DESC_B_SHIFT) & 1;
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lhs->s = (flags & DESC_S_MASK) != 0;
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lhs->l = (flags >> DESC_L_SHIFT) & 1;
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lhs->g = (flags & DESC_G_MASK) != 0;
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lhs->avl = (flags & DESC_AVL_MASK) != 0;
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lhs->unusable = 0;
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} |
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static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) |
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{ |
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lhs->selector = rhs->selector; |
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lhs->base = rhs->base; |
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lhs->limit = rhs->limit; |
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lhs->flags = |
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(rhs->type << DESC_TYPE_SHIFT) |
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| (rhs->present * DESC_P_MASK) |
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| (rhs->dpl << DESC_DPL_SHIFT) |
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| (rhs->db << DESC_B_SHIFT) |
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| (rhs->s * DESC_S_MASK) |
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| (rhs->l << DESC_L_SHIFT) |
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| (rhs->g * DESC_G_MASK) |
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| (rhs->avl * DESC_AVL_MASK); |
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} |
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static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) |
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{ |
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if (set)
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*kvm_reg = *qemu_reg; |
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else
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*qemu_reg = *kvm_reg; |
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} |
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static int kvm_getput_regs(CPUState *env, int set) |
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{ |
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struct kvm_regs regs;
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int ret = 0; |
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if (!set) {
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ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); |
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if (ret < 0) |
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return ret;
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} |
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kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); |
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kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); |
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kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); |
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kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); |
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kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); |
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kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); |
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kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); |
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kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); |
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#ifdef TARGET_X86_64
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kvm_getput_reg(®s.r8, &env->regs[8], set);
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kvm_getput_reg(®s.r9, &env->regs[9], set);
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kvm_getput_reg(®s.r10, &env->regs[10], set);
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kvm_getput_reg(®s.r11, &env->regs[11], set);
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kvm_getput_reg(®s.r12, &env->regs[12], set);
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kvm_getput_reg(®s.r13, &env->regs[13], set);
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kvm_getput_reg(®s.r14, &env->regs[14], set);
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kvm_getput_reg(®s.r15, &env->regs[15], set);
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#endif
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kvm_getput_reg(®s.rflags, &env->eflags, set); |
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kvm_getput_reg(®s.rip, &env->eip, set); |
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if (set)
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ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); |
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return ret;
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} |
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static int kvm_put_fpu(CPUState *env) |
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{ |
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struct kvm_fpu fpu;
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int i;
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memset(&fpu, 0, sizeof fpu); |
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fpu.fsw = env->fpus & ~(7 << 11); |
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fpu.fsw |= (env->fpstt & 7) << 11; |
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fpu.fcw = env->fpuc; |
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for (i = 0; i < 8; ++i) |
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fpu.ftwx |= (!env->fptags[i]) << i; |
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memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
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memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
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fpu.mxcsr = env->mxcsr; |
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return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
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} |
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static int kvm_put_sregs(CPUState *env) |
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{ |
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struct kvm_sregs sregs;
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memcpy(sregs.interrupt_bitmap, |
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env->interrupt_bitmap, |
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sizeof(sregs.interrupt_bitmap));
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if ((env->eflags & VM_MASK)) {
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set_v8086_seg(&sregs.cs, &env->segs[R_CS]); |
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set_v8086_seg(&sregs.ds, &env->segs[R_DS]); |
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set_v8086_seg(&sregs.es, &env->segs[R_ES]); |
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set_v8086_seg(&sregs.fs, &env->segs[R_FS]); |
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set_v8086_seg(&sregs.gs, &env->segs[R_GS]); |
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set_v8086_seg(&sregs.ss, &env->segs[R_SS]); |
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} else {
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set_seg(&sregs.cs, &env->segs[R_CS]); |
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set_seg(&sregs.ds, &env->segs[R_DS]); |
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set_seg(&sregs.es, &env->segs[R_ES]); |
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set_seg(&sregs.fs, &env->segs[R_FS]); |
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set_seg(&sregs.gs, &env->segs[R_GS]); |
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set_seg(&sregs.ss, &env->segs[R_SS]); |
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|
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if (env->cr[0] & CR0_PE_MASK) { |
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/* force ss cpl to cs cpl */
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sregs.ss.selector = (sregs.ss.selector & ~3) |
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(sregs.cs.selector & 3);
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sregs.ss.dpl = sregs.ss.selector & 3;
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} |
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} |
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set_seg(&sregs.tr, &env->tr); |
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set_seg(&sregs.ldt, &env->ldt); |
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sregs.idt.limit = env->idt.limit; |
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sregs.idt.base = env->idt.base; |
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sregs.gdt.limit = env->gdt.limit; |
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sregs.gdt.base = env->gdt.base; |
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sregs.cr0 = env->cr[0];
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sregs.cr2 = env->cr[2];
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sregs.cr3 = env->cr[3];
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sregs.cr4 = env->cr[4];
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sregs.cr8 = cpu_get_apic_tpr(env); |
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sregs.apic_base = cpu_get_apic_base(env); |
358 |
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sregs.efer = env->efer; |
360 |
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return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
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} |
363 |
|
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static void kvm_msr_entry_set(struct kvm_msr_entry *entry, |
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uint32_t index, uint64_t value) |
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{ |
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entry->index = index; |
368 |
entry->data = value; |
369 |
} |
370 |
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static int kvm_put_msrs(CPUState *env) |
372 |
{ |
373 |
struct {
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struct kvm_msrs info;
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struct kvm_msr_entry entries[100]; |
376 |
} msr_data; |
377 |
struct kvm_msr_entry *msrs = msr_data.entries;
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378 |
int n = 0; |
379 |
|
380 |
kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); |
381 |
kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); |
382 |
kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); |
383 |
if (kvm_has_msr_star(env))
|
384 |
kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); |
385 |
kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); |
386 |
#ifdef TARGET_X86_64
|
387 |
/* FIXME if lm capable */
|
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kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); |
389 |
kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); |
390 |
kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); |
391 |
kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); |
392 |
#endif
|
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msr_data.info.nmsrs = n; |
394 |
|
395 |
return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
|
396 |
|
397 |
} |
398 |
|
399 |
|
400 |
static int kvm_get_fpu(CPUState *env) |
401 |
{ |
402 |
struct kvm_fpu fpu;
|
403 |
int i, ret;
|
404 |
|
405 |
ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu); |
406 |
if (ret < 0) |
407 |
return ret;
|
408 |
|
409 |
env->fpstt = (fpu.fsw >> 11) & 7; |
410 |
env->fpus = fpu.fsw; |
411 |
env->fpuc = fpu.fcw; |
412 |
for (i = 0; i < 8; ++i) |
413 |
env->fptags[i] = !((fpu.ftwx >> i) & 1);
|
414 |
memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
|
415 |
memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
|
416 |
env->mxcsr = fpu.mxcsr; |
417 |
|
418 |
return 0; |
419 |
} |
420 |
|
421 |
static int kvm_get_sregs(CPUState *env) |
422 |
{ |
423 |
struct kvm_sregs sregs;
|
424 |
uint32_t hflags; |
425 |
int ret;
|
426 |
|
427 |
ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); |
428 |
if (ret < 0) |
429 |
return ret;
|
430 |
|
431 |
memcpy(env->interrupt_bitmap, |
432 |
sregs.interrupt_bitmap, |
433 |
sizeof(sregs.interrupt_bitmap));
|
434 |
|
435 |
get_seg(&env->segs[R_CS], &sregs.cs); |
436 |
get_seg(&env->segs[R_DS], &sregs.ds); |
437 |
get_seg(&env->segs[R_ES], &sregs.es); |
438 |
get_seg(&env->segs[R_FS], &sregs.fs); |
439 |
get_seg(&env->segs[R_GS], &sregs.gs); |
440 |
get_seg(&env->segs[R_SS], &sregs.ss); |
441 |
|
442 |
get_seg(&env->tr, &sregs.tr); |
443 |
get_seg(&env->ldt, &sregs.ldt); |
444 |
|
445 |
env->idt.limit = sregs.idt.limit; |
446 |
env->idt.base = sregs.idt.base; |
447 |
env->gdt.limit = sregs.gdt.limit; |
448 |
env->gdt.base = sregs.gdt.base; |
449 |
|
450 |
env->cr[0] = sregs.cr0;
|
451 |
env->cr[2] = sregs.cr2;
|
452 |
env->cr[3] = sregs.cr3;
|
453 |
env->cr[4] = sregs.cr4;
|
454 |
|
455 |
cpu_set_apic_base(env, sregs.apic_base); |
456 |
|
457 |
env->efer = sregs.efer; |
458 |
//cpu_set_apic_tpr(env, sregs.cr8);
|
459 |
|
460 |
#define HFLAG_COPY_MASK ~( \
|
461 |
HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ |
462 |
HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ |
463 |
HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ |
464 |
HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) |
465 |
|
466 |
|
467 |
|
468 |
hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; |
469 |
hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
|
470 |
hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
|
471 |
(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); |
472 |
hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); |
473 |
hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
|
474 |
(HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT); |
475 |
|
476 |
if (env->efer & MSR_EFER_LMA) {
|
477 |
hflags |= HF_LMA_MASK; |
478 |
} |
479 |
|
480 |
if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
|
481 |
hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; |
482 |
} else {
|
483 |
hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> |
484 |
(DESC_B_SHIFT - HF_CS32_SHIFT); |
485 |
hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> |
486 |
(DESC_B_SHIFT - HF_SS32_SHIFT); |
487 |
if (!(env->cr[0] & CR0_PE_MASK) || |
488 |
(env->eflags & VM_MASK) || |
489 |
!(hflags & HF_CS32_MASK)) { |
490 |
hflags |= HF_ADDSEG_MASK; |
491 |
} else {
|
492 |
hflags |= ((env->segs[R_DS].base | |
493 |
env->segs[R_ES].base | |
494 |
env->segs[R_SS].base) != 0) <<
|
495 |
HF_ADDSEG_SHIFT; |
496 |
} |
497 |
} |
498 |
env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags; |
499 |
|
500 |
return 0; |
501 |
} |
502 |
|
503 |
static int kvm_get_msrs(CPUState *env) |
504 |
{ |
505 |
struct {
|
506 |
struct kvm_msrs info;
|
507 |
struct kvm_msr_entry entries[100]; |
508 |
} msr_data; |
509 |
struct kvm_msr_entry *msrs = msr_data.entries;
|
510 |
int ret, i, n;
|
511 |
|
512 |
n = 0;
|
513 |
msrs[n++].index = MSR_IA32_SYSENTER_CS; |
514 |
msrs[n++].index = MSR_IA32_SYSENTER_ESP; |
515 |
msrs[n++].index = MSR_IA32_SYSENTER_EIP; |
516 |
if (kvm_has_msr_star(env))
|
517 |
msrs[n++].index = MSR_STAR; |
518 |
msrs[n++].index = MSR_IA32_TSC; |
519 |
#ifdef TARGET_X86_64
|
520 |
/* FIXME lm_capable_kernel */
|
521 |
msrs[n++].index = MSR_CSTAR; |
522 |
msrs[n++].index = MSR_KERNELGSBASE; |
523 |
msrs[n++].index = MSR_FMASK; |
524 |
msrs[n++].index = MSR_LSTAR; |
525 |
#endif
|
526 |
msr_data.info.nmsrs = n; |
527 |
ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data); |
528 |
if (ret < 0) |
529 |
return ret;
|
530 |
|
531 |
for (i = 0; i < ret; i++) { |
532 |
switch (msrs[i].index) {
|
533 |
case MSR_IA32_SYSENTER_CS:
|
534 |
env->sysenter_cs = msrs[i].data; |
535 |
break;
|
536 |
case MSR_IA32_SYSENTER_ESP:
|
537 |
env->sysenter_esp = msrs[i].data; |
538 |
break;
|
539 |
case MSR_IA32_SYSENTER_EIP:
|
540 |
env->sysenter_eip = msrs[i].data; |
541 |
break;
|
542 |
case MSR_STAR:
|
543 |
env->star = msrs[i].data; |
544 |
break;
|
545 |
#ifdef TARGET_X86_64
|
546 |
case MSR_CSTAR:
|
547 |
env->cstar = msrs[i].data; |
548 |
break;
|
549 |
case MSR_KERNELGSBASE:
|
550 |
env->kernelgsbase = msrs[i].data; |
551 |
break;
|
552 |
case MSR_FMASK:
|
553 |
env->fmask = msrs[i].data; |
554 |
break;
|
555 |
case MSR_LSTAR:
|
556 |
env->lstar = msrs[i].data; |
557 |
break;
|
558 |
#endif
|
559 |
case MSR_IA32_TSC:
|
560 |
env->tsc = msrs[i].data; |
561 |
break;
|
562 |
} |
563 |
} |
564 |
|
565 |
return 0; |
566 |
} |
567 |
|
568 |
int kvm_arch_put_registers(CPUState *env)
|
569 |
{ |
570 |
int ret;
|
571 |
|
572 |
ret = kvm_getput_regs(env, 1);
|
573 |
if (ret < 0) |
574 |
return ret;
|
575 |
|
576 |
ret = kvm_put_fpu(env); |
577 |
if (ret < 0) |
578 |
return ret;
|
579 |
|
580 |
ret = kvm_put_sregs(env); |
581 |
if (ret < 0) |
582 |
return ret;
|
583 |
|
584 |
ret = kvm_put_msrs(env); |
585 |
if (ret < 0) |
586 |
return ret;
|
587 |
|
588 |
return 0; |
589 |
} |
590 |
|
591 |
int kvm_arch_get_registers(CPUState *env)
|
592 |
{ |
593 |
int ret;
|
594 |
|
595 |
ret = kvm_getput_regs(env, 0);
|
596 |
if (ret < 0) |
597 |
return ret;
|
598 |
|
599 |
ret = kvm_get_fpu(env); |
600 |
if (ret < 0) |
601 |
return ret;
|
602 |
|
603 |
ret = kvm_get_sregs(env); |
604 |
if (ret < 0) |
605 |
return ret;
|
606 |
|
607 |
ret = kvm_get_msrs(env); |
608 |
if (ret < 0) |
609 |
return ret;
|
610 |
|
611 |
return 0; |
612 |
} |
613 |
|
614 |
int kvm_arch_pre_run(CPUState *env, struct kvm_run *run) |
615 |
{ |
616 |
/* Try to inject an interrupt if the guest can accept it */
|
617 |
if (run->ready_for_interrupt_injection &&
|
618 |
(env->interrupt_request & CPU_INTERRUPT_HARD) && |
619 |
(env->eflags & IF_MASK)) { |
620 |
int irq;
|
621 |
|
622 |
env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
623 |
irq = cpu_get_pic_interrupt(env); |
624 |
if (irq >= 0) { |
625 |
struct kvm_interrupt intr;
|
626 |
intr.irq = irq; |
627 |
/* FIXME: errors */
|
628 |
dprintf("injected interrupt %d\n", irq);
|
629 |
kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr); |
630 |
} |
631 |
} |
632 |
|
633 |
/* If we have an interrupt but the guest is not ready to receive an
|
634 |
* interrupt, request an interrupt window exit. This will
|
635 |
* cause a return to userspace as soon as the guest is ready to
|
636 |
* receive interrupts. */
|
637 |
if ((env->interrupt_request & CPU_INTERRUPT_HARD))
|
638 |
run->request_interrupt_window = 1;
|
639 |
else
|
640 |
run->request_interrupt_window = 0;
|
641 |
|
642 |
dprintf("setting tpr\n");
|
643 |
run->cr8 = cpu_get_apic_tpr(env); |
644 |
|
645 |
return 0; |
646 |
} |
647 |
|
648 |
int kvm_arch_post_run(CPUState *env, struct kvm_run *run) |
649 |
{ |
650 |
if (run->if_flag)
|
651 |
env->eflags |= IF_MASK; |
652 |
else
|
653 |
env->eflags &= ~IF_MASK; |
654 |
|
655 |
cpu_set_apic_tpr(env, run->cr8); |
656 |
cpu_set_apic_base(env, run->apic_base); |
657 |
|
658 |
return 0; |
659 |
} |
660 |
|
661 |
static int kvm_handle_halt(CPUState *env) |
662 |
{ |
663 |
if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
|
664 |
(env->eflags & IF_MASK)) && |
665 |
!(env->interrupt_request & CPU_INTERRUPT_NMI)) { |
666 |
env->halted = 1;
|
667 |
env->exception_index = EXCP_HLT; |
668 |
return 0; |
669 |
} |
670 |
|
671 |
return 1; |
672 |
} |
673 |
|
674 |
int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) |
675 |
{ |
676 |
int ret = 0; |
677 |
|
678 |
switch (run->exit_reason) {
|
679 |
case KVM_EXIT_HLT:
|
680 |
dprintf("handle_hlt\n");
|
681 |
ret = kvm_handle_halt(env); |
682 |
break;
|
683 |
} |
684 |
|
685 |
return ret;
|
686 |
} |
687 |
|
688 |
#ifdef KVM_CAP_SET_GUEST_DEBUG
|
689 |
int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) |
690 |
{ |
691 |
const static uint8_t int3 = 0xcc; |
692 |
|
693 |
if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || |
694 |
cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) |
695 |
return -EINVAL;
|
696 |
return 0; |
697 |
} |
698 |
|
699 |
int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp) |
700 |
{ |
701 |
uint8_t int3; |
702 |
|
703 |
if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc || |
704 |
cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) |
705 |
return -EINVAL;
|
706 |
return 0; |
707 |
} |
708 |
|
709 |
static struct { |
710 |
target_ulong addr; |
711 |
int len;
|
712 |
int type;
|
713 |
} hw_breakpoint[4];
|
714 |
|
715 |
static int nb_hw_breakpoint; |
716 |
|
717 |
static int find_hw_breakpoint(target_ulong addr, int len, int type) |
718 |
{ |
719 |
int n;
|
720 |
|
721 |
for (n = 0; n < nb_hw_breakpoint; n++) |
722 |
if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
|
723 |
(hw_breakpoint[n].len == len || len == -1))
|
724 |
return n;
|
725 |
return -1; |
726 |
} |
727 |
|
728 |
int kvm_arch_insert_hw_breakpoint(target_ulong addr,
|
729 |
target_ulong len, int type)
|
730 |
{ |
731 |
switch (type) {
|
732 |
case GDB_BREAKPOINT_HW:
|
733 |
len = 1;
|
734 |
break;
|
735 |
case GDB_WATCHPOINT_WRITE:
|
736 |
case GDB_WATCHPOINT_ACCESS:
|
737 |
switch (len) {
|
738 |
case 1: |
739 |
break;
|
740 |
case 2: |
741 |
case 4: |
742 |
case 8: |
743 |
if (addr & (len - 1)) |
744 |
return -EINVAL;
|
745 |
break;
|
746 |
default:
|
747 |
return -EINVAL;
|
748 |
} |
749 |
break;
|
750 |
default:
|
751 |
return -ENOSYS;
|
752 |
} |
753 |
|
754 |
if (nb_hw_breakpoint == 4) |
755 |
return -ENOBUFS;
|
756 |
|
757 |
if (find_hw_breakpoint(addr, len, type) >= 0) |
758 |
return -EEXIST;
|
759 |
|
760 |
hw_breakpoint[nb_hw_breakpoint].addr = addr; |
761 |
hw_breakpoint[nb_hw_breakpoint].len = len; |
762 |
hw_breakpoint[nb_hw_breakpoint].type = type; |
763 |
nb_hw_breakpoint++; |
764 |
|
765 |
return 0; |
766 |
} |
767 |
|
768 |
int kvm_arch_remove_hw_breakpoint(target_ulong addr,
|
769 |
target_ulong len, int type)
|
770 |
{ |
771 |
int n;
|
772 |
|
773 |
n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
|
774 |
if (n < 0) |
775 |
return -ENOENT;
|
776 |
|
777 |
nb_hw_breakpoint--; |
778 |
hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; |
779 |
|
780 |
return 0; |
781 |
} |
782 |
|
783 |
void kvm_arch_remove_all_hw_breakpoints(void) |
784 |
{ |
785 |
nb_hw_breakpoint = 0;
|
786 |
} |
787 |
|
788 |
static CPUWatchpoint hw_watchpoint;
|
789 |
|
790 |
int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info) |
791 |
{ |
792 |
int handle = 0; |
793 |
int n;
|
794 |
|
795 |
if (arch_info->exception == 1) { |
796 |
if (arch_info->dr6 & (1 << 14)) { |
797 |
if (cpu_single_env->singlestep_enabled)
|
798 |
handle = 1;
|
799 |
} else {
|
800 |
for (n = 0; n < 4; n++) |
801 |
if (arch_info->dr6 & (1 << n)) |
802 |
switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { |
803 |
case 0x0: |
804 |
handle = 1;
|
805 |
break;
|
806 |
case 0x1: |
807 |
handle = 1;
|
808 |
cpu_single_env->watchpoint_hit = &hw_watchpoint; |
809 |
hw_watchpoint.vaddr = hw_breakpoint[n].addr; |
810 |
hw_watchpoint.flags = BP_MEM_WRITE; |
811 |
break;
|
812 |
case 0x3: |
813 |
handle = 1;
|
814 |
cpu_single_env->watchpoint_hit = &hw_watchpoint; |
815 |
hw_watchpoint.vaddr = hw_breakpoint[n].addr; |
816 |
hw_watchpoint.flags = BP_MEM_ACCESS; |
817 |
break;
|
818 |
} |
819 |
} |
820 |
} else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) |
821 |
handle = 1;
|
822 |
|
823 |
if (!handle)
|
824 |
kvm_update_guest_debug(cpu_single_env, |
825 |
(arch_info->exception == 1) ?
|
826 |
KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP); |
827 |
|
828 |
return handle;
|
829 |
} |
830 |
|
831 |
void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg) |
832 |
{ |
833 |
const uint8_t type_code[] = {
|
834 |
[GDB_BREAKPOINT_HW] = 0x0,
|
835 |
[GDB_WATCHPOINT_WRITE] = 0x1,
|
836 |
[GDB_WATCHPOINT_ACCESS] = 0x3
|
837 |
}; |
838 |
const uint8_t len_code[] = {
|
839 |
[1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 |
840 |
}; |
841 |
int n;
|
842 |
|
843 |
if (kvm_sw_breakpoints_active(env))
|
844 |
dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; |
845 |
|
846 |
if (nb_hw_breakpoint > 0) { |
847 |
dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; |
848 |
dbg->arch.debugreg[7] = 0x0600; |
849 |
for (n = 0; n < nb_hw_breakpoint; n++) { |
850 |
dbg->arch.debugreg[n] = hw_breakpoint[n].addr; |
851 |
dbg->arch.debugreg[7] |= (2 << (n * 2)) | |
852 |
(type_code[hw_breakpoint[n].type] << (16 + n*4)) | |
853 |
(len_code[hw_breakpoint[n].len] << (18 + n*4)); |
854 |
} |
855 |
} |
856 |
} |
857 |
#endif /* KVM_CAP_SET_GUEST_DEBUG */ |