Revision 64d7e9a4

b/hw/i8254.c
53 53
    qemu_irq irq;
54 54
} PITChannelState;
55 55

  
56
struct PITState {
56
typedef struct PITState {
57
    ISADevice dev;
58
    uint32_t irq;
59
    uint32_t iobase;
57 60
    PITChannelState channels[3];
58
};
61
} PITState;
59 62

  
60 63
static PITState pit_state;
61 64

  
......
119 122
    return out;
120 123
}
121 124

  
122
int pit_get_out(PITState *pit, int channel, int64_t current_time)
125
int pit_get_out(ISADevice *dev, int channel, int64_t current_time)
123 126
{
127
    PITState *pit = DO_UPCAST(PITState, dev, dev);
124 128
    PITChannelState *s = &pit->channels[channel];
125 129
    return pit_get_out1(s, current_time);
126 130
}
......
179 183
}
180 184

  
181 185
/* val must be 0 or 1 */
182
void pit_set_gate(PITState *pit, int channel, int val)
186
void pit_set_gate(ISADevice *dev, int channel, int val)
183 187
{
188
    PITState *pit = DO_UPCAST(PITState, dev, dev);
184 189
    PITChannelState *s = &pit->channels[channel];
185 190

  
186 191
    switch(s->mode) {
......
210 215
    s->gate = val;
211 216
}
212 217

  
213
int pit_get_gate(PITState *pit, int channel)
218
int pit_get_gate(ISADevice *dev, int channel)
214 219
{
220
    PITState *pit = DO_UPCAST(PITState, dev, dev);
215 221
    PITChannelState *s = &pit->channels[channel];
216 222
    return s->gate;
217 223
}
218 224

  
219
int pit_get_initial_count(PITState *pit, int channel)
225
int pit_get_initial_count(ISADevice *dev, int channel)
220 226
{
227
    PITState *pit = DO_UPCAST(PITState, dev, dev);
221 228
    PITChannelState *s = &pit->channels[channel];
222 229
    return s->count;
223 230
}
224 231

  
225
int pit_get_mode(PITState *pit, int channel)
232
int pit_get_mode(ISADevice *dev, int channel)
226 233
{
234
    PITState *pit = DO_UPCAST(PITState, dev, dev);
227 235
    PITChannelState *s = &pit->channels[channel];
228 236
    return s->mode;
229 237
}
......
462 470
    }
463 471
};
464 472

  
465
static void pit_reset(void *opaque)
473
static void pit_reset(DeviceState *dev)
466 474
{
467
    PITState *pit = opaque;
475
    PITState *pit = container_of(dev, PITState, dev.qdev);
468 476
    PITChannelState *s;
469 477
    int i;
470 478

  
......
498 506
    pit_load_count(s, 0);
499 507
}
500 508

  
501
PITState *pit_init(int base, qemu_irq irq)
509
static int pit_initfn(ISADevice *dev)
502 510
{
503
    PITState *pit = &pit_state;
511
    PITState *pit = DO_UPCAST(PITState, dev, dev);
504 512
    PITChannelState *s;
505 513

  
506 514
    s = &pit->channels[0];
507 515
    /* the timer 0 is connected to an IRQ */
508 516
    s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
509
    s->irq = irq;
517
    s->irq = isa_reserve_irq(pit->irq);
510 518

  
511
    vmstate_register(NULL, base, &vmstate_pit, pit);
512
    qemu_register_reset(pit_reset, pit);
513
    register_ioport_write(base, 4, 1, pit_ioport_write, pit);
514
    register_ioport_read(base, 3, 1, pit_ioport_read, pit);
519
    register_ioport_write(pit->iobase, 4, 1, pit_ioport_write, pit);
520
    register_ioport_read(pit->iobase, 3, 1, pit_ioport_read, pit);
521
    isa_init_ioport(dev, pit->iobase);
515 522

  
516
    return pit;
523
    return 0;
524
}
525

  
526
static ISADeviceInfo pit_info = {
527
    .qdev.name     = "isa-pit",
528
    .qdev.size     = sizeof(PITState),
529
    .qdev.vmsd     = &vmstate_pit,
530
    .qdev.reset    = pit_reset,
531
    .qdev.no_user  = 1,
532
    .init          = pit_initfn,
533
    .qdev.props = (Property[]) {
534
        DEFINE_PROP_UINT32("irq", PITState, irq,  -1),
535
        DEFINE_PROP_HEX32("iobase", PITState, iobase,  -1),
536
        DEFINE_PROP_END_OF_LIST(),
537
    },
538
};
539

  
540
static void pit_register(void)
541
{
542
    isa_qdev_register(&pit_info);
517 543
}
544
device_init(pit_register)
b/hw/mips_fulong2e.c
67 67
#define FULONG2E_ATI_SLOT        6
68 68
#define FULONG2E_RTL8139_SLOT    7
69 69

  
70
static PITState *pit;
70
static ISADevice *pit;
71 71

  
72 72
static struct _loaderparams {
73 73
    int ram_size;
......
369 369
    qdev_init_nofail(eeprom);
370 370

  
371 371
    /* init other devices */
372
    pit = pit_init(0x40, isa_reserve_irq(0));
372
    pit = pit_init(0x40, 0);
373 373
    cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
374 374
    DMA_init(0, cpu_exit_irq);
375 375

  
b/hw/mips_jazz.c
115 115
    void* rc4030_opaque;
116 116
    int s_rtc, s_dma_dummy;
117 117
    NICInfo *nd;
118
    PITState *pit;
118
    ISADevice *pit;
119 119
    DriveInfo *fds[MAX_FD];
120 120
    qemu_irq esp_reset, dma_enable;
121 121
    qemu_irq *cpu_exit_irq;
......
181 181
    isa_bus_irqs(i8259);
182 182
    cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
183 183
    DMA_init(0, cpu_exit_irq);
184
    pit = pit_init(0x40, i8259[0]);
184
    pit = pit_init(0x40, 0);
185 185
    pcspk_init(pit);
186 186

  
187 187
    /* ISA IO space at 0x90000000 */
b/hw/mips_malta.c
68 68
    SerialState *uart;
69 69
} MaltaFPGAState;
70 70

  
71
static PITState *pit;
71
static ISADevice *pit;
72 72

  
73 73
static struct _loaderparams {
74 74
    int ram_size;
......
930 930
        qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
931 931
        qdev_init_nofail(eeprom);
932 932
    }
933
    pit = pit_init(0x40, isa_reserve_irq(0));
933
    pit = pit_init(0x40, 0);
934 934
    cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
935 935
    DMA_init(0, cpu_exit_irq);
936 936

  
b/hw/mips_r4k.c
30 30
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
31 31
static const int ide_irq[2] = { 14, 15 };
32 32

  
33
static PITState *pit; /* PIT i8254 */
33
static ISADevice *pit; /* PIT i8254 */
34 34

  
35 35
/* i8254 PIT is attached to the IRQ0 at PIC i8259 */
36 36

  
......
274 274
    isa_mmio_init(0x14000000, 0x00010000);
275 275
    isa_mem_base = 0x10000000;
276 276

  
277
    pit = pit_init(0x40, i8259[0]);
277
    pit = pit_init(0x40, 0);
278 278

  
279 279
    for(i = 0; i < MAX_SERIAL_PORTS; i++) {
280 280
        if (serial_hds[i]) {
b/hw/pc.c
1104 1104
{
1105 1105
    int i;
1106 1106
    DriveInfo *fd[MAX_FD];
1107
    PITState *pit;
1108 1107
    qemu_irq rtc_irq = NULL;
1109 1108
    qemu_irq *a20_line;
1110
    ISADevice *i8042, *port92, *vmmouse;
1109
    ISADevice *i8042, *port92, *vmmouse, *pit;
1111 1110
    qemu_irq *cpu_exit_irq;
1112 1111

  
1113 1112
    register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
......
1128 1127

  
1129 1128
    qemu_register_boot_set(pc_boot_set, *rtc_state);
1130 1129

  
1131
    pit = pit_init(0x40, isa_reserve_irq(0));
1130
    pit = pit_init(0x40, 0);
1132 1131
    pcspk_init(pit);
1133 1132

  
1134 1133
    for(i = 0; i < MAX_SERIAL_PORTS; i++) {
b/hw/pc.h
82 82

  
83 83
#define PIT_FREQ 1193182
84 84

  
85
typedef struct PITState PITState;
85
static inline ISADevice *pit_init(int base, int irq)
86
{
87
    ISADevice *dev;
88

  
89
    dev = isa_create("isa-pit");
90
    qdev_prop_set_uint32(&dev->qdev, "iobase", base);
91
    qdev_prop_set_uint32(&dev->qdev, "irq", irq);
92
    qdev_init_nofail(&dev->qdev);
93

  
94
    return dev;
95
}
86 96

  
87
PITState *pit_init(int base, qemu_irq irq);
88
void pit_set_gate(PITState *pit, int channel, int val);
89
int pit_get_gate(PITState *pit, int channel);
90
int pit_get_initial_count(PITState *pit, int channel);
91
int pit_get_mode(PITState *pit, int channel);
92
int pit_get_out(PITState *pit, int channel, int64_t current_time);
97
void pit_set_gate(ISADevice *dev, int channel, int val);
98
int pit_get_gate(ISADevice *dev, int channel);
99
int pit_get_initial_count(ISADevice *dev, int channel);
100
int pit_get_mode(ISADevice *dev, int channel);
101
int pit_get_out(ISADevice *dev, int channel, int64_t current_time);
93 102

  
94 103
void hpet_pit_disable(void);
95 104
void hpet_pit_enable(void);
......
159 168
extern int no_hpet;
160 169

  
161 170
/* pcspk.c */
162
void pcspk_init(PITState *);
171
void pcspk_init(ISADevice *pit);
163 172
int pcspk_audio_init(qemu_irq *pic);
164 173

  
165 174
/* piix_pci.c */
b/hw/pcspk.c
37 37
    uint8_t sample_buf[PCSPK_BUF_LEN];
38 38
    QEMUSoundCard card;
39 39
    SWVoiceOut *voice;
40
    PITState *pit;
40
    ISADevice *pit;
41 41
    unsigned int pit_count;
42 42
    unsigned int samples;
43 43
    unsigned int play_pos;
......
137 137
    }
138 138
}
139 139

  
140
void pcspk_init(PITState *pit)
140
void pcspk_init(ISADevice *pit)
141 141
{
142 142
    PCSpkState *s = &pcspk_state;
143 143

  
b/hw/ppc_prep.c
82 82
static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
83 83
static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
84 84

  
85
//static PITState *pit;
85
//static ISADevice *pit;
86 86

  
87 87
/* ISA IO ports bridge */
88 88
#define PPC_IO_BASE 0x80000000
......
662 662
    /* init basic PC hardware */
663 663
    pci_vga_init(pci_bus);
664 664
    //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
665
    //    pit = pit_init(0x40, i8259[0]);
665
    //    pit = pit_init(0x40, 0);
666 666
    rtc_init(2000, NULL);
667 667

  
668 668
    if (serial_hds[0])

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