Fix Sparc host build breakage
Fix error: CC sparc-bsd-user/op_helper.oIn file included from /src/qemu/tcg/tcg.c:158:/src/qemu/tcg/sparc/tcg-target.c:728:5: "TARGET_PHYS_ADDR_BITS" is not defined
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg/ppc64: Only define addend load helpers in softmmu case
Signed-off-by: malc <av1474@comtv.ru>
Remove TLB from userspace
Remove TLB from userspace CPU structure.
Signed-off-by: Paul Brook <paul@codesourcery.com>
tcg/arm: merge the two sets of #define for optional ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/arm: accept immediate arguments for brcond/setcond
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
Add a missing break
tcg/arm: implement setcond2
tcg/arm: implement setcond
tcg/arm: fix div2/divu2
When restoring register values, increase the stack register for skippedvalues.
tcg/ppc: Fix right rotation
tcg/ppc: Fix typo
tcg/ppc64: Use C90 style comments
tcg/ppc: Implement some of the optional ops
tcg: fix build on 32-bit hppa, ppc and sparc hosts
The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64.
Signed-off-by: Jay Foad <jay.foad@gmail.com>Signed-off-by: malc <av1474@comtv.ru>
tcg: fix assertion with --enable-debug
On 32-bit hosts op_qemu_ld32s is unused. Remove it to fix thefollowing assertion failure:
qemu-alpha: tcg/tcg.c:1055:tcg_add_target_add_op_defs: Assertion `tcg_op_defs[op].used' failed.
Signed-off-by: Jay Foad <jay.foad@gmail.com>...
tcg: Add comments for all optional instructions not implemented.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg-sparc: Implement ORC.
tcg-sparc: Implement ANDC.
tcg: Optional target implementation of ORC.
Previously ORC was always implemented by tcg-op.h withan explicit NOT opcode. Allow a target implementation.
tcg: Optional target implementation of ANDC.
Previously ANDC was always implemented by tcg-op.h withan explicit NOT opcode. Allow a target implementation.
tcg-sparc: Implement not.
The fallback implementation of "ret = arg1 ^ -1" isn't idealbecause of the extra tcg op to load the minus one.
tcg-sparc: Implement neg.
The fallback implementation of "ret = 0 - arg1" isn't ideal,first because of the extra tcg op to load the zero, and secondbecause we fail to handle zero as %g0 for arg1 of the sub.
Signed-off-by: Richard Henderson <rth@twiddle.net>...
tcg/ppc: Consistently use calling convention selection macros
Use ppc host calling convention definitions to set TCG_TARGET_CALL_{ALIGN_ARGS,STACK_OFFSET}.
New version after malc's comments. (This avoids having to do #if defined linux || defined FreeBSD || defined FreeBSD_kernelfor the third case.)...
tcg: Add consistency checks for op definitions
When compiled with CONFIG_DEBUG_TCG, this code looksfor missing, duplicate and wrong entries in theop definitions.
Errors will raise an assertion at program start(all checks are done in the initial phase)....
tcg-sparc: Implement setcond, setcond2.
tcg: Add tcg_swap_cond.
Returns the condition as if with swapped comparison operands.
tcg/mips: fix crash in tcg_out_qemu_ld()
The address register is overriden when it corresponds to v0 and the fastpath is taken, which leads to a crash. Fix that by using the a0 registerinstead.
tcg/mips: implement setcond2
tcg/mips: implement setcond
tcg: move setcond* ops to non-optional section
setcond is not an optional op, move it to the non-optional section.
tcg: add setcondi pseudo-op
tcg/ppc64: implement setcond
tcg/ppc32: proper setcond implementation
tcg/ppc32: implement setcond2
tcg-i386: Implement setcond.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg-i386: Implement small forward branches.
There are places, like brcond2, where we know that the destinationof a forward branch will be within 127 bytes.
Add the R_386_PC8 relocation type to support this. Add a flag totcg_out_jxx and tcg_out_brcond* to enable it. Set the flag in the...
tcg: document double-word support opcodes.
The internal opcodes brcond2, add2, sub2, mulu2 were undocumented.Place these in a new section that clearly indicates that they arenot to be emitted by translators.
tcg: generic support for conditional set
Defines setcond_{i32,i64} and setcond2_i32 for 64-on-32-bit.
tcg: add tcg_invert_cond
It is very handy to have a reliable mapping of a condition to its inverse.
tcg-x86_64: implement setcond
tcg/x86_64: Avoid unnecessary REX.B prefixes.
The existing P_REXB internal opcode flag unconditionally emitsthe REX prefix. Technically it's not needed if the register inquestion is %al, %bl, %cl, %dl.
Eliding the prefix requires splitting the P_REXB flag into two,...
tcg/x86_64: Special-case all 32-bit AND operands.
This avoids an unnecessary REX.W prefix when dealing with ANDoperands that fit into a 32-bit quantity. The most common changeactually seen is movz[wb]q -> movz[wb]l.
Similarly, avoid REXW in ext{8,16}u_i64 tcg opcodes....
tcg-sparc: Implement ext32[su]_i64
The 32-bit right-shift instructions is defined to extend the shiftedoutput to 64-bits. A shift count of zero therefore is a simpleextension without actually shifting.
tcg-sparc: Implement division properly.
The {div,divu}2 opcodes are intended for systems for which thedivision instruction produces both quotient and remainder. Sparcis not such a system. Indeed, the remainder must be computed as
quot = a / b rem = a - (quot * b)...
tcg-sparc: Do not remove %o012 from 'r' constraint.
Only 'L' constraint needs that.
tcg-sparc: Implement add2, sub2, mulu2.
Add missing 32-bit double-word support opcodes.
tcg-sparc: Add tcg_out_arithc.
Add a function to handle the register-vs-immediate test for arithmetic.
Also, adjust the OP_32_64 macro so that it auto-indents properly.Rename the gen_arith32 label to gen_arith, since it handles 64-bitarithmetic as well....
tcg: Add tcg_unsigned_cond.
Returns an unsigned version of a signed condition;returns the original condition otherwise.
tcg-sparc: Implement brcond2.
Split out tcg_out_cmp and properly handle immediate arguments.Fix constraints on brcond to match what SUBCC accepts.Add tcg_out_brcond2_i32 for 32-bit host.
tcg-sparc: Use TCG_TARGET_REG_BITS in conditional compilation.
The test TCG_TARGET_REG_BITS==64 is exactly the feature that weare checking for, whereas something involving sparc_v9 orsparc_v8plus should be reserved for something ISA related,as with SMULX....
tcg-sparc: Improve tcg_out_movi for sparc64.
Generate sign-extended 32-bit constants with SETHI+XOR.Otherwise tidy the routine to avoid the need forconditional compilation and code duplication with movi_imm32.
tcg-sparc: Fix imm13 check in movi.
We were unnecessarily restricting imm13 constants to 12 bits.
tcg/ppc64: Fix loading of 32bit constants
TCG: Mac OS X support for ppc64 target
Darwin/ppc64 does not use function descriptors,adapt prologue and tcg_out_call accordingly.GPR2 is available for general use, so let's use it.
http://developer.apple.com/mac/library/documentation/DeveloperTools/Conceptual/LowLevelABI/110-64-bit_PowerPC_Function_Calling_Conventions/64bitPowerPC.html...
S/390 fake TCG implementation
Qemu won't let us run a KVM target without having host TCG support. Well, fornow we don't have any so let's implement a fake target that only stubs outeverything.
I tried to keep the patch as close to Uli's source as possible, so whenever...
tcg: initial mips support
Based on a patch from Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
tcg: fix tcg_regset_{set,reset}_reg with more than 32 registers
tcg/ppc64,x86_64: fix constraints of op_qemu_st64
This op only takes two arguments, not two.
tcg/i386: remove duplicate sar opcode
Signed-off-by: Magnus Damm <damm@opensource.se>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: improve output log
tcg: allocate s->op_dead_iargs dynamically
Similarly to what is already done in tcg_liveness_analysis() whenUSE_LIVENESS_ANALYSIS is not set.
tcg: remove dead code
tcg: add ext{8,16,32}u_i{32,64} TCG ops
Currently zero extensions ops are implemented by a and op with aconstant. This is then catched in some backend, and replaced bya zero extension instruction. While this works well on RISCmachines, this adds a useless register move on non-RISC machines....
tcg/x86_64: add support for ext{8,16,32}u_i{32,64} TCG ops
tcg/i386: add support for ext{8,16}u_i32 TCG ops
Revert part of 6692b043198d58a12317009edb98654c6839f043
Committed by accident.
TCG: fix DEF2 macro
tcg/i386: generates dec/inc instead of sub/add when possible
We must take care that dec/inc do not compute CF, which is needed byadd2/sub2.
tcg/i386: optimize and $0xff(ff), reg
tcg/x86_64: generated dec/inc instead of sub/add when possible
tcg/ppc: always use tcg_out_call
ARM back-end: Use sxt[bh] instructions for ext{8, 6}s
This patch uses sxtb for ext8s_i32 and sxth for ext16s_i32 in ARM back-end.
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Suppress some variants of English in comments
Replace surpress, supress by suppress.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Compile TCG runtime library only once
tcg: fix size of local variables in tcg_gen_bswap64_i64
t0, t1 must be 64 bit values, not 32 bit.
X86_64: Use proper jumps/calls when displacement exceeds +-2G
When targeting PPU use rlwinm instead of andi. if possible
andi. is microcoded and slow there.
ARM back-end: Fix encode_imm
the encode_imm function in tcg/arm/tcg-target.c lacks shift declaration.
Laurent
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
ARM back-end: Handle all possible immediates for ALU ops
this patch handles all possible constants for immediate operand of ALU ops.I'm not very satisfied by the implementation.
ARM back-end: Add TCG not
this patch:
- implements TCG not.
rename DEBUG_TCG to CONFIG_DEBUG_TCG
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
change HOST_SOLARIS to CONFIG_SOLARIS{_VERSION}
Fix CONFIG_PROFILER
Fix rbase initialization
this patch improves the ARM back-end in the following way:
- use movw/movt to load immediate values for ARMv7-A- implement add/sub/and/or/xor with immediate (only 8-bit)
tcg: Fix tcg_gen_rotr_i64
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
PPC 32/64 GUEST_BASE support
Fix LHZX opcode value
Userspace guest address offsetting
Fix type in i386 tcg.
Signed-off-by: Juan Quintela <quintela@redhat.com>
Re-implement GUEST_BASE support.Offset guest ddress space by default if the guest binary containsregions below the host mmap_min_addr.Implement support for i386, x86-64 and arm hosts.
Signed-off-by: Riku Voipio <riku.voipio@iki.fi>...
ARM host fixes
Minor TCG cleanups and warning fixes for ARM hosts.
Include assert.h from qemu-common.h
Include assert.h from qemu-common.h and remove other direct uses.cpu-all.h still need to include it because of the dyngen-exec.h hacks
tcg: make sure NDEBUG is defined before including <assert.h>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7122 c046a42c-6fe2-441c-8c8c-71466251a162
Add a --enable-debug-tcg option to configure
This patch allows DEBUG_TCGV to be defined (and also prevents NDEBUGfrom being defined) when passing an option to the configure script.This should help to prevent any accidental changes that enableDEBUG_TCGV in tcg/tcg.h from being committed in future, and may...
Remove reserved registers from tcg_target_reg_alloc_order
Noticed by Andreas Faerber
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7082 c046a42c-6fe2-441c-8c8c-71466251a162
Whack [LS]MW
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7081 c046a42c-6fe2-441c-8c8c-71466251a162
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7080 c046a42c-6fe2-441c-8c8c-71466251a162
tcg/tcg.h: fix a few typos
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7024 c046a42c-6fe2-441c-8c8c-71466251a162