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# Date Author Comment
65850a02 03/13/2010 11:52 am Blue Swirl

Fix Sparc host build breakage

Fix error:
CC sparc-bsd-user/op_helper.o
In file included from /src/qemu/tcg/tcg.c:158:
/src/qemu/tcg/sparc/tcg-target.c:728:5: "TARGET_PHYS_ADDR_BITS" is not defined

Signed-off-by: Blue Swirl <>

30c0c76c 02/22/2010 06:38 pm Jay Foad

tcg: fix build on 32-bit hppa, ppc and sparc hosts

The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64.

Signed-off-by: Jay Foad <>
Signed-off-by: malc <>

18c8f7a3 02/20/2010 10:34 am Richard Henderson

tcg-sparc: Implement ORC.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

dc69960d 02/20/2010 10:34 am Richard Henderson

tcg-sparc: Implement ANDC.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

be6551b1 02/20/2010 10:32 am Richard Henderson

tcg-sparc: Implement not.

The fallback implementation of "ret = arg1 ^ -1" isn't ideal
because of the extra tcg op to load the minus one.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

4b5a85c1 02/20/2010 10:31 am Richard Henderson

tcg-sparc: Implement neg.

The fallback implementation of "ret = 0 - arg1" isn't ideal,
first because of the extra tcg op to load the zero, and second
because we fail to handle zero as %g0 for arg1 of the sub.

Signed-off-by: Richard Henderson <>...

dbfe80e1 02/16/2010 07:53 pm Richard Henderson

tcg-sparc: Implement setcond, setcond2.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

cc6dfecf 01/12/2010 09:59 pm Richard Henderson

tcg-sparc: Implement ext32[su]_i64

The 32-bit right-shift instructions is defined to extend the shifted
output to 64-bits. A shift count of zero therefore is a simple
extension without actually shifting.

Signed-off-by: Richard Henderson <>...

583d1215 01/12/2010 09:59 pm Richard Henderson

tcg-sparc: Implement division properly.

The {div,divu}2 opcodes are intended for systems for which the
division instruction produces both quotient and remainder. Sparc
is not such a system. Indeed, the remainder must be computed as

quot = a / b
rem = a - (quot * b)...
5e143c43 01/12/2010 09:59 pm Richard Henderson

tcg-sparc: Do not remove %o012 from 'r' constraint.

Only 'L' constraint needs that.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

7a3766f3 01/12/2010 09:59 pm Richard Henderson

tcg-sparc: Implement add2, sub2, mulu2.

Add missing 32-bit double-word support opcodes.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

ba225198 01/12/2010 09:59 pm Richard Henderson

tcg-sparc: Add tcg_out_arithc.

Add a function to handle the register-vs-immediate test for arithmetic.

Also, adjust the OP_32_64 macro so that it auto-indents properly.
Rename the gen_arith32 label to gen_arith, since it handles 64-bit
arithmetic as well....

56f4927e 12/21/2009 10:52 pm Richard Henderson

tcg-sparc: Implement brcond2.

Split out tcg_out_cmp and properly handle immediate arguments.
Fix constraints on brcond to match what SUBCC accepts.
Add tcg_out_brcond2_i32 for 32-bit host.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

a212ea75 12/21/2009 10:52 pm Richard Henderson

tcg-sparc: Use TCG_TARGET_REG_BITS in conditional compilation.

The test TCG_TARGET_REG_BITS==64 is exactly the feature that we
are checking for, whereas something involving sparc_v9 or
sparc_v8plus should be reserved for something ISA related,
as with SMULX....

43172207 12/21/2009 10:52 pm Richard Henderson

tcg-sparc: Improve tcg_out_movi for sparc64.

Generate sign-extended 32-bit constants with SETHI+XOR.
Otherwise tidy the routine to avoid the need for
conditional compilation and code duplication with movi_imm32.

Signed-off-by: Richard Henderson <>...

4a09aa89 12/21/2009 10:49 pm Richard Henderson

tcg-sparc: Fix imm13 check in movi.

We were unnecessarily restricting imm13 constants to 12 bits.

Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>

1da92db2 04/04/2009 10:10 pm blueswir1

Fix branches and TLB matches for 64 bit targets

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6974 c046a42c-6fe2-441c-8c8c-71466251a162

f843e528 04/04/2009 06:33 pm blueswir1

Allocate space for static call args, increase stack frame size on Sparc64

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6973 c046a42c-6fe2-441c-8c8c-71466251a162

d4a9eb1f 10/05/2008 12:59 pm blueswir1

Add some missing static and const qualifiers, reg_names only used if NDEBUG set

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162

9d0efc88 09/13/2008 11:07 pm blueswir1

Use 64 bit loads for tlb addend only if addend size is 64 bits

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5203 c046a42c-6fe2-441c-8c8c-71466251a162

79383c9c 08/30/2008 12:51 pm blueswir1

Fix some warnings that would be generated by gcc -Wredundant-decls

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162

6f41b777 08/17/2008 11:14 pm blueswir1

Fix 64 bit constant generation

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5020 c046a42c-6fe2-441c-8c8c-71466251a162

90cbed46 08/17/2008 07:13 pm blueswir1

Fix 32 bit address overflow

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5019 c046a42c-6fe2-441c-8c8c-71466251a162

bffe1431 08/17/2008 05:34 pm blueswir1

Restore AREG0 after calls

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5018 c046a42c-6fe2-441c-8c8c-71466251a162

56fc64df 08/16/2008 10:54 pm blueswir1

Sparc code generator update (fix qemu_ld & qemu_st)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5014 c046a42c-6fe2-441c-8c8c-71466251a162

53c37487 08/15/2008 09:14 pm blueswir1

Sparc code generator update

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5009 c046a42c-6fe2-441c-8c8c-71466251a162

e97b640d 07/26/2008 08:19 pm blueswir1

Try to avoid glibc global register mangling, again

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4953 c046a42c-6fe2-441c-8c8c-71466251a162

d795eb86 07/07/2008 10:34 pm blueswir1

Fix 64 bit constant generation

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4854 c046a42c-6fe2-441c-8c8c-71466251a162

8384dd67 05/25/2008 02:19 pm blueswir1

Implement byte swapping accesses

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4574 c046a42c-6fe2-441c-8c8c-71466251a162

b101234a 05/24/2008 09:09 pm blueswir1

Implement 64-bit constant loads

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4561 c046a42c-6fe2-441c-8c8c-71466251a162

26cc915c 05/24/2008 09:06 pm blueswir1

Use sethi and arith functions, fix comment

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4560 c046a42c-6fe2-441c-8c8c-71466251a162

57e49b40 05/18/2008 11:11 am blueswir1

Fix constant checks on Sparc64 host

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4486 c046a42c-6fe2-441c-8c8c-71466251a162

9a7f3228 05/17/2008 12:41 pm blueswir1

Fix qemu_ld/st branches, constification, use orcc for tst synthetic op

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4466 c046a42c-6fe2-441c-8c8c-71466251a162

f5ef6aac 05/16/2008 11:15 pm blueswir1

Implement qemu_ld/st, fix brcond, handle more corner cases

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4463 c046a42c-6fe2-441c-8c8c-71466251a162

cf7c2ca5 05/15/2008 10:44 pm blueswir1

Implement brcond, ldst with large offset; fix direct jump, prologue

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4461 c046a42c-6fe2-441c-8c8c-71466251a162

f02ca5cb 05/15/2008 08:30 pm blueswir1

Fix bit fitting checks

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4460 c046a42c-6fe2-441c-8c8c-71466251a162

7d551702 05/14/2008 10:22 pm blueswir1

Fix compilation on Sparc host, implement ld and st

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4457 c046a42c-6fe2-441c-8c8c-71466251a162

f54b3f92 04/12/2008 11:14 pm aurel32

HPPA (PA-RISC) host support

(Stuart Brady)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4199 c046a42c-6fe2-441c-8c8c-71466251a162

e4d5434c 03/13/2008 07:34 pm blueswir1

Fix i32 memory backed variables on 64-bit host

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4044 c046a42c-6fe2-441c-8c8c-71466251a162

0954d0d9 03/11/2008 11:01 pm blueswir1

Remove blank elements in tcg_target_reg_alloc_order[] (Stuart Brady)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4039 c046a42c-6fe2-441c-8c8c-71466251a162

b3db8758 03/08/2008 03:33 pm blueswir1

Add function prologue, fix pointer load on Sparc64 host

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4027 c046a42c-6fe2-441c-8c8c-71466251a162

53cd9273 03/07/2008 08:21 pm blueswir1

Update based on Stuart Brady's comments

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4026 c046a42c-6fe2-441c-8c8c-71466251a162

2f0a5008 02/29/2008 09:34 pm blueswir1

Fix register references (Igor Kovalenko)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4002 c046a42c-6fe2-441c-8c8c-71466251a162

8289b279 02/27/2008 07:53 pm blueswir1

Preliminary Sparc TCG target

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3995 c046a42c-6fe2-441c-8c8c-71466251a162