Revision 65fe043e

b/tcg/ppc/tcg-target.c
333 333
#define STWU   OPCD(37)
334 334

  
335 335
#define RLWINM OPCD(21)
336
#define RLWNM  OPCD(23)
336 337

  
337 338
#define BCLR   XO19( 16)
338 339
#define BCCTR  XO19(528)
......
369 370
#define NEG    XO31(104)
370 371
#define MFCR   XO31( 19)
371 372
#define CNTLZW XO31( 26)
373
#define NOR    XO31(124)
374
#define ANDC   XO31( 60)
375
#define ORC    XO31(412)
372 376

  
373 377
#define LBZX   XO31( 87)
374 378
#define LHZX   XO31(279)
......
1468 1472
        else
1469 1473
            tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1470 1474
        break;
1475
    case INDEX_op_andc_i32:
1476
        tcg_out32 (s, ANDC | SAB (args[1], args[0], args[2]));
1477
        break;
1478
    case INDEX_op_orc_i32:
1479
        tcg_out32 (s, ORC | SAB (args[1], args[0], args[2]));
1480
        break;
1471 1481

  
1472 1482
    case INDEX_op_mul_i32:
1473 1483
        if (const_args[2]) {
......
1549 1559
        else
1550 1560
            tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1551 1561
        break;
1562
    case INDEX_op_rotl_i32:
1563
        {
1564
            int op = 0
1565
                | RA (args[0])
1566
                | RS (args[1])
1567
                | MB (0)
1568
                | ME (31)
1569
                | (const_args[2] ? RLWINM | SH (args[2])
1570
                                 : RLWNM | RB (args[2]))
1571
                ;
1572
            tcg_out32 (s, op);
1573
        }
1574
        break;
1575
    case INDEX_op_rotr_i32:
1576
        if (const_args[2]) {
1577
            if (!args[2]) {
1578
                tcg_out_mov (s, args[0], args[2]);
1579
            }
1580
            else {
1581
                tcg_out32 (s, RLWINM
1582
                           | RA (args[0])
1583
                           | RS (args[1])
1584
                           | SH (32 - args[2])
1585
                           | MB (0)
1586
                           | ME (31)
1587
                    );
1588
            }
1589
        }
1590
        else {
1591
            tcg_out32 (s, ADDI | RT (0) | RA (args[2]) | 0xffe0);
1592
            tcg_out32 (s, RLWNM
1593
                       | RA (args[0])
1594
                       | RS (args[1])
1595
                       | RB (0)
1596
                       | MB (0)
1597
                       | ME (31)
1598
                );
1599
        }
1600
        break;
1552 1601

  
1553 1602
    case INDEX_op_add2_i32:
1554 1603
        if (args[0] == args[3] || args[0] == args[5]) {
......
1591 1640
        tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1592 1641
        break;
1593 1642

  
1643
    case INDEX_op_not_i32:
1644
        tcg_out32 (s, NOR | SAB (args[1], args[0], args[0]));
1645
        break;
1646

  
1594 1647
    case INDEX_op_qemu_ld8u:
1595 1648
        tcg_out_qemu_ld(s, args, 0);
1596 1649
        break;
......
1625 1678
    case INDEX_op_ext8s_i32:
1626 1679
        tcg_out32 (s, EXTSB | RS (args[1]) | RA (args[0]));
1627 1680
        break;
1681
    case INDEX_op_ext8u_i32:
1682
        tcg_out32 (s, RLWINM
1683
                   | RA (args[0])
1684
                   | RS (args[1])
1685
                   | SH (0)
1686
                   | MB (24)
1687
                   | ME (31)
1688
            );
1689
        break;
1628 1690
    case INDEX_op_ext16s_i32:
1629 1691
        tcg_out32 (s, EXTSH | RS (args[1]) | RA (args[0]));
1630 1692
        break;
1693
    case INDEX_op_ext16u_i32:
1694
        tcg_out32 (s, RLWINM
1695
                   | RA (args[0])
1696
                   | RS (args[1])
1697
                   | SH (0)
1698
                   | MB (16)
1699
                   | ME (31)
1700
            );
1701
        break;
1631 1702

  
1632 1703
    case INDEX_op_setcond_i32:
1633 1704
        tcg_out_setcond (s, args[3], args[0], args[1], args[2], const_args[2]);
......
1676 1747
    { INDEX_op_shr_i32, { "r", "r", "ri" } },
1677 1748
    { INDEX_op_sar_i32, { "r", "r", "ri" } },
1678 1749

  
1750
    { INDEX_op_rotl_i32, { "r", "r", "ri" } },
1751
    { INDEX_op_rotr_i32, { "r", "r", "ri" } },
1752

  
1679 1753
    { INDEX_op_brcond_i32, { "r", "ri" } },
1680 1754

  
1681 1755
    { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
......
1683 1757
    { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1684 1758

  
1685 1759
    { INDEX_op_neg_i32, { "r", "r" } },
1760
    { INDEX_op_not_i32, { "r", "r" } },
1761

  
1762
    { INDEX_op_andc_i32, { "r", "r", "r" } },
1763
    { INDEX_op_orc_i32, { "r", "r", "r" } },
1686 1764

  
1687 1765
    { INDEX_op_setcond_i32, { "r", "r", "ri" } },
1688 1766
    { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
......
1714 1792
#endif
1715 1793

  
1716 1794
    { INDEX_op_ext8s_i32, { "r", "r" } },
1795
    { INDEX_op_ext8u_i32, { "r", "r" } },
1717 1796
    { INDEX_op_ext16s_i32, { "r", "r" } },
1797
    { INDEX_op_ext16u_i32, { "r", "r" } },
1718 1798

  
1719 1799
    { -1 },
1720 1800
};
b/tcg/ppc/tcg-target.h
78 78

  
79 79
/* optional instructions */
80 80
#define TCG_TARGET_HAS_div_i32
81
// #define TCG_TARGET_HAS_rot_i32
81
#define TCG_TARGET_HAS_rot_i32
82 82
#define TCG_TARGET_HAS_ext8s_i32
83 83
#define TCG_TARGET_HAS_ext16s_i32
84
// #define TCG_TARGET_HAS_ext8u_i32
85
// #define TCG_TARGET_HAS_ext16u_i32
86
// #define TCG_TARGET_HAS_bswap16_i32
87
// #define TCG_TARGET_HAS_bswap32_i32
88
// #define TCG_TARGET_HAS_not_i32
84
#define TCG_TARGET_HAS_ext8u_i32
85
#define TCG_TARGET_HAS_ext16u_i32
86
/* #define TCG_TARGET_HAS_bswap16_i32 */
87
/* #define TCG_TARGET_HAS_bswap32_i32 */
88
#define TCG_TARGET_HAS_not_i32
89 89
#define TCG_TARGET_HAS_neg_i32
90
// #define TCG_TARGET_HAS_andc_i32
91
// #define TCG_TARGET_HAS_orc_i32
90
#define TCG_TARGET_HAS_andc_i32
91
#define TCG_TARGET_HAS_orc_i32
92 92

  
93 93
#define TCG_AREG0 TCG_REG_R27
94 94
#define TCG_AREG1 TCG_REG_R24

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