Revision 661a1799
b/hw/pcnet-pci.c | ||
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/* |
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* QEMU AMD PC-Net II (Am79C970A) PCI emulation |
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* |
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* Copyright (c) 2004 Antony T Curtis |
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a copy |
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* of this software and associated documentation files (the "Software"), to deal |
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* in the Software without restriction, including without limitation the rights |
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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* copies of the Software, and to permit persons to whom the Software is |
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* furnished to do so, subject to the following conditions: |
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* |
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* The above copyright notice and this permission notice shall be included in |
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* all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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* THE SOFTWARE. |
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*/ |
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/* This software was written to be compatible with the specification: |
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* AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet |
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* AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000 |
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*/ |
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#include "pci.h" |
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#include "net.h" |
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#include "loader.h" |
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#include "qemu-timer.h" |
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#include "pcnet.h" |
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//#define PCNET_DEBUG |
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//#define PCNET_DEBUG_IO |
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//#define PCNET_DEBUG_BCR |
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//#define PCNET_DEBUG_CSR |
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//#define PCNET_DEBUG_RMD |
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//#define PCNET_DEBUG_TMD |
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//#define PCNET_DEBUG_MATCH |
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typedef struct { |
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PCIDevice pci_dev; |
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PCNetState state; |
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} PCIPCNetState; |
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|
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static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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PCNetState *s = opaque; |
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#ifdef PCNET_DEBUG |
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printf("pcnet_aprom_writeb addr=0x%08x val=0x%02x\n", addr, val); |
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#endif |
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/* Check APROMWE bit to enable write access */ |
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if (pcnet_bcr_readw(s,2) & 0x100) |
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s->prom[addr & 15] = val; |
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} |
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static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr) |
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{ |
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PCNetState *s = opaque; |
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uint32_t val = s->prom[addr & 15]; |
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#ifdef PCNET_DEBUG |
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printf("pcnet_aprom_readb addr=0x%08x val=0x%02x\n", addr, val); |
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#endif |
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return val; |
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} |
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static void pcnet_ioport_map(PCIDevice *pci_dev, int region_num, |
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pcibus_t addr, pcibus_t size, int type) |
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{ |
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PCNetState *d = &DO_UPCAST(PCIPCNetState, pci_dev, pci_dev)->state; |
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#ifdef PCNET_DEBUG_IO |
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printf("pcnet_ioport_map addr=0x%04"FMT_PCIBUS" size=0x%04"FMT_PCIBUS"\n", |
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addr, size); |
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#endif |
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register_ioport_write(addr, 16, 1, pcnet_aprom_writeb, d); |
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register_ioport_read(addr, 16, 1, pcnet_aprom_readb, d); |
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register_ioport_write(addr + 0x10, 0x10, 2, pcnet_ioport_writew, d); |
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register_ioport_read(addr + 0x10, 0x10, 2, pcnet_ioport_readw, d); |
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register_ioport_write(addr + 0x10, 0x10, 4, pcnet_ioport_writel, d); |
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register_ioport_read(addr + 0x10, 0x10, 4, pcnet_ioport_readl, d); |
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} |
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static void pcnet_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
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{ |
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PCNetState *d = opaque; |
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#ifdef PCNET_DEBUG_IO |
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printf("pcnet_mmio_writeb addr=0x" TARGET_FMT_plx" val=0x%02x\n", addr, |
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val); |
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#endif |
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if (!(addr & 0x10)) |
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pcnet_aprom_writeb(d, addr & 0x0f, val); |
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} |
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static uint32_t pcnet_mmio_readb(void *opaque, target_phys_addr_t addr) |
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{ |
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PCNetState *d = opaque; |
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uint32_t val = -1; |
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if (!(addr & 0x10)) |
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val = pcnet_aprom_readb(d, addr & 0x0f); |
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#ifdef PCNET_DEBUG_IO |
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printf("pcnet_mmio_readb addr=0x" TARGET_FMT_plx " val=0x%02x\n", addr, |
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val & 0xff); |
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#endif |
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return val; |
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} |
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static void pcnet_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
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{ |
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PCNetState *d = opaque; |
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#ifdef PCNET_DEBUG_IO |
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printf("pcnet_mmio_writew addr=0x" TARGET_FMT_plx " val=0x%04x\n", addr, |
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val); |
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#endif |
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if (addr & 0x10) |
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pcnet_ioport_writew(d, addr & 0x0f, val); |
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else { |
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addr &= 0x0f; |
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pcnet_aprom_writeb(d, addr, val & 0xff); |
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pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8); |
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} |
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} |
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static uint32_t pcnet_mmio_readw(void *opaque, target_phys_addr_t addr) |
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{ |
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PCNetState *d = opaque; |
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uint32_t val = -1; |
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if (addr & 0x10) |
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val = pcnet_ioport_readw(d, addr & 0x0f); |
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else { |
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addr &= 0x0f; |
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val = pcnet_aprom_readb(d, addr+1); |
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val <<= 8; |
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val |= pcnet_aprom_readb(d, addr); |
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} |
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#ifdef PCNET_DEBUG_IO |
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printf("pcnet_mmio_readw addr=0x" TARGET_FMT_plx" val = 0x%04x\n", addr, |
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val & 0xffff); |
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#endif |
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return val; |
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} |
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static void pcnet_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
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{ |
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PCNetState *d = opaque; |
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#ifdef PCNET_DEBUG_IO |
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printf("pcnet_mmio_writel addr=0x" TARGET_FMT_plx" val=0x%08x\n", addr, |
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val); |
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#endif |
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if (addr & 0x10) |
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pcnet_ioport_writel(d, addr & 0x0f, val); |
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else { |
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addr &= 0x0f; |
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pcnet_aprom_writeb(d, addr, val & 0xff); |
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pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8); |
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pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16); |
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pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24); |
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} |
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} |
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static uint32_t pcnet_mmio_readl(void *opaque, target_phys_addr_t addr) |
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{ |
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PCNetState *d = opaque; |
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uint32_t val; |
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if (addr & 0x10) |
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val = pcnet_ioport_readl(d, addr & 0x0f); |
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else { |
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addr &= 0x0f; |
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val = pcnet_aprom_readb(d, addr+3); |
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val <<= 8; |
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val |= pcnet_aprom_readb(d, addr+2); |
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val <<= 8; |
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val |= pcnet_aprom_readb(d, addr+1); |
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val <<= 8; |
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val |= pcnet_aprom_readb(d, addr); |
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} |
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#ifdef PCNET_DEBUG_IO |
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printf("pcnet_mmio_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, |
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val); |
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#endif |
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return val; |
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} |
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static const VMStateDescription vmstate_pci_pcnet = { |
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.name = "pcnet", |
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.version_id = 3, |
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.minimum_version_id = 2, |
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.minimum_version_id_old = 2, |
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.fields = (VMStateField []) { |
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VMSTATE_PCI_DEVICE(pci_dev, PCIPCNetState), |
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VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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/* PCI interface */ |
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static CPUWriteMemoryFunc * const pcnet_mmio_write[] = { |
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&pcnet_mmio_writeb, |
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&pcnet_mmio_writew, |
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&pcnet_mmio_writel |
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}; |
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static CPUReadMemoryFunc * const pcnet_mmio_read[] = { |
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&pcnet_mmio_readb, |
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&pcnet_mmio_readw, |
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&pcnet_mmio_readl |
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}; |
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static void pcnet_mmio_map(PCIDevice *pci_dev, int region_num, |
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pcibus_t addr, pcibus_t size, int type) |
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{ |
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PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, pci_dev); |
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#ifdef PCNET_DEBUG_IO |
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printf("pcnet_mmio_map addr=0x%08"FMT_PCIBUS" 0x%08"FMT_PCIBUS"\n", |
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addr, size); |
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#endif |
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cpu_register_physical_memory(addr, PCNET_PNPMMIO_SIZE, d->state.mmio_index); |
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} |
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static void pci_physical_memory_write(void *dma_opaque, target_phys_addr_t addr, |
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uint8_t *buf, int len, int do_bswap) |
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{ |
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cpu_physical_memory_write(addr, buf, len); |
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} |
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static void pci_physical_memory_read(void *dma_opaque, target_phys_addr_t addr, |
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uint8_t *buf, int len, int do_bswap) |
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{ |
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cpu_physical_memory_read(addr, buf, len); |
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} |
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static void pci_pcnet_cleanup(VLANClientState *nc) |
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{ |
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PCNetState *d = DO_UPCAST(NICState, nc, nc)->opaque; |
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pcnet_common_cleanup(d); |
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} |
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static int pci_pcnet_uninit(PCIDevice *dev) |
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{ |
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PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, dev); |
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cpu_unregister_io_memory(d->state.mmio_index); |
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qemu_del_timer(d->state.poll_timer); |
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qemu_free_timer(d->state.poll_timer); |
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qemu_del_vlan_client(&d->state.nic->nc); |
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return 0; |
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} |
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static NetClientInfo net_pci_pcnet_info = { |
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.type = NET_CLIENT_TYPE_NIC, |
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.size = sizeof(NICState), |
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.can_receive = pcnet_can_receive, |
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.receive = pcnet_receive, |
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.cleanup = pci_pcnet_cleanup, |
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}; |
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static int pci_pcnet_init(PCIDevice *pci_dev) |
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{ |
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PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, pci_dev); |
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PCNetState *s = &d->state; |
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uint8_t *pci_conf; |
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#if 0 |
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printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n", |
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sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD)); |
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#endif |
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pci_conf = pci_dev->config; |
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_AMD); |
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_AMD_LANCE); |
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pci_set_word(pci_conf + PCI_STATUS, |
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PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); |
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pci_conf[PCI_REVISION_ID] = 0x10; |
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pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
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pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0); |
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pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0); |
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pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0 |
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pci_conf[PCI_MIN_GNT] = 0x06; |
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pci_conf[PCI_MAX_LAT] = 0xff; |
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/* Handler for memory-mapped I/O */ |
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s->mmio_index = |
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cpu_register_io_memory(pcnet_mmio_read, pcnet_mmio_write, &d->state); |
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pci_register_bar(pci_dev, 0, PCNET_IOPORT_SIZE, |
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PCI_BASE_ADDRESS_SPACE_IO, pcnet_ioport_map); |
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pci_register_bar(pci_dev, 1, PCNET_PNPMMIO_SIZE, |
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PCI_BASE_ADDRESS_SPACE_MEMORY, pcnet_mmio_map); |
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s->irq = pci_dev->irq[0]; |
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s->phys_mem_read = pci_physical_memory_read; |
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s->phys_mem_write = pci_physical_memory_write; |
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if (!pci_dev->qdev.hotplugged) { |
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static int loaded = 0; |
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if (!loaded) { |
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rom_add_option("pxe-pcnet.bin"); |
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loaded = 1; |
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} |
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} |
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return pcnet_common_init(&pci_dev->qdev, s, &net_pci_pcnet_info); |
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} |
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static void pci_reset(DeviceState *dev) |
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{ |
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PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev.qdev, dev); |
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pcnet_h_reset(&d->state); |
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} |
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static PCIDeviceInfo pcnet_info = { |
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.qdev.name = "pcnet", |
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.qdev.size = sizeof(PCIPCNetState), |
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.qdev.reset = pci_reset, |
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.qdev.vmsd = &vmstate_pci_pcnet, |
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.init = pci_pcnet_init, |
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.exit = pci_pcnet_uninit, |
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.qdev.props = (Property[]) { |
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DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf), |
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DEFINE_PROP_END_OF_LIST(), |
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} |
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}; |
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static void pci_pcnet_register_devices(void) |
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{ |
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pci_qdev_register(&pcnet_info); |
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} |
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|
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device_init(pci_pcnet_register_devices) |
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