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/* Print mips instructions for GDB, the GNU debugger, or for objdump. |
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Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
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2000, 2001, 2002, 2003 |
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Free Software Foundation, Inc. |
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Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp). |
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|
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This file is part of GDB, GAS, and the GNU binutils. |
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|
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This program is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 2 of the License, or |
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(at your option) any later version. |
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|
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This program is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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|
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You should have received a copy of the GNU General Public License |
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along with this program; if not, write to the Free Software |
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
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#include "dis-asm.h" |
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|
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/* mips.h. Mips opcode list for GDB, the GNU debugger. |
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Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 |
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Free Software Foundation, Inc. |
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Contributed by Ralph Campbell and OSF |
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Commented and modified by Ian Lance Taylor, Cygnus Support |
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|
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This file is part of GDB, GAS, and the GNU binutils. |
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|
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GDB, GAS, and the GNU binutils are free software; you can redistribute |
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them and/or modify them under the terms of the GNU General Public |
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License as published by the Free Software Foundation; either version |
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1, or (at your option) any later version. |
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|
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GDB, GAS, and the GNU binutils are distributed in the hope that they |
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will be useful, but WITHOUT ANY WARRANTY; without even the implied |
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
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the GNU General Public License for more details. |
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|
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You should have received a copy of the GNU General Public License |
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along with this file; see the file COPYING. If not, write to the Free |
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
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|
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/* mips.h. Mips opcode list for GDB, the GNU debugger. |
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Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 |
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Free Software Foundation, Inc. |
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Contributed by Ralph Campbell and OSF |
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Commented and modified by Ian Lance Taylor, Cygnus Support |
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|
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This file is part of GDB, GAS, and the GNU binutils. |
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|
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GDB, GAS, and the GNU binutils are free software; you can redistribute |
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them and/or modify them under the terms of the GNU General Public |
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License as published by the Free Software Foundation; either version |
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1, or (at your option) any later version. |
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|
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GDB, GAS, and the GNU binutils are distributed in the hope that they |
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will be useful, but WITHOUT ANY WARRANTY; without even the implied |
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
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the GNU General Public License for more details. |
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|
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You should have received a copy of the GNU General Public License |
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along with this file; see the file COPYING. If not, write to the Free |
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
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/* These are bit masks and shift counts to use to access the various |
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fields of an instruction. To retrieve the X field of an |
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instruction, use the expression |
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(i >> OP_SH_X) & OP_MASK_X |
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To set the same field (to j), use |
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i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) |
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Make sure you use fields that are appropriate for the instruction, |
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of course. |
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The 'i' format uses OP, RS, RT and IMMEDIATE. |
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The 'j' format uses OP and TARGET. |
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The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. |
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The 'b' format uses OP, RS, RT and DELTA. |
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The floating point 'i' format uses OP, RS, RT and IMMEDIATE. |
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The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. |
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A breakpoint instruction uses OP, CODE and SPEC (10 bits of the |
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breakpoint instruction are not defined; Kane says the breakpoint |
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code field in BREAK is 20 bits; yet MIPS assemblers and debuggers |
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only use ten bits). An optional two-operand form of break/sdbbp |
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allows the lower ten bits to be set too, and MIPS32 and later |
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architectures allow 20 bits to be set with a signal operand |
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(using CODE20). |
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The syscall instruction uses CODE20. |
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The general coprocessor instructions use COPZ. */ |
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#define OP_MASK_OP 0x3f |
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#define OP_SH_OP 26 |
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#define OP_MASK_RS 0x1f |
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#define OP_SH_RS 21 |
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#define OP_MASK_FR 0x1f |
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#define OP_SH_FR 21 |
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#define OP_MASK_FMT 0x1f |
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#define OP_SH_FMT 21 |
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#define OP_MASK_BCC 0x7 |
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#define OP_SH_BCC 18 |
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#define OP_MASK_CODE 0x3ff |
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#define OP_SH_CODE 16 |
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#define OP_MASK_CODE2 0x3ff |
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#define OP_SH_CODE2 6 |
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#define OP_MASK_RT 0x1f |
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#define OP_SH_RT 16 |
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#define OP_MASK_FT 0x1f |
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#define OP_SH_FT 16 |
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#define OP_MASK_CACHE 0x1f |
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#define OP_SH_CACHE 16 |
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#define OP_MASK_RD 0x1f |
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#define OP_SH_RD 11 |
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#define OP_MASK_FS 0x1f |
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#define OP_SH_FS 11 |
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#define OP_MASK_PREFX 0x1f |
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#define OP_SH_PREFX 11 |
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#define OP_MASK_CCC 0x7 |
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#define OP_SH_CCC 8 |
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#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ |
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#define OP_SH_CODE20 6 |
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#define OP_MASK_SHAMT 0x1f |
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#define OP_SH_SHAMT 6 |
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#define OP_MASK_FD 0x1f |
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#define OP_SH_FD 6 |
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#define OP_MASK_TARGET 0x3ffffff |
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#define OP_SH_TARGET 0 |
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#define OP_MASK_COPZ 0x1ffffff |
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#define OP_SH_COPZ 0 |
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#define OP_MASK_IMMEDIATE 0xffff |
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#define OP_SH_IMMEDIATE 0 |
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#define OP_MASK_DELTA 0xffff |
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#define OP_SH_DELTA 0 |
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#define OP_MASK_FUNCT 0x3f |
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#define OP_SH_FUNCT 0 |
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#define OP_MASK_SPEC 0x3f |
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#define OP_SH_SPEC 0 |
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#define OP_SH_LOCC 8 /* FP condition code. */ |
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#define OP_SH_HICC 18 /* FP condition code. */ |
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#define OP_MASK_CC 0x7 |
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#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ |
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#define OP_MASK_COP1NORM 0x1 /* a single bit. */ |
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#define OP_SH_COP1SPEC 21 /* COP1 encodings. */ |
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#define OP_MASK_COP1SPEC 0xf |
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#define OP_MASK_COP1SCLR 0x4 |
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#define OP_MASK_COP1CMP 0x3 |
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#define OP_SH_COP1CMP 4 |
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#define OP_SH_FORMAT 21 /* FP short format field. */ |
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#define OP_MASK_FORMAT 0x7 |
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#define OP_SH_TRUE 16 |
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#define OP_MASK_TRUE 0x1 |
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#define OP_SH_GE 17 |
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#define OP_MASK_GE 0x01 |
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#define OP_SH_UNSIGNED 16 |
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#define OP_MASK_UNSIGNED 0x1 |
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#define OP_SH_HINT 16 |
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#define OP_MASK_HINT 0x1f |
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#define OP_SH_MMI 0 /* Multimedia (parallel) op. */ |
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#define OP_MASK_MMI 0x3f |
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#define OP_SH_MMISUB 6 |
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#define OP_MASK_MMISUB 0x1f |
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#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ |
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#define OP_SH_PERFREG 1 |
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#define OP_SH_SEL 0 /* Coprocessor select field. */ |
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#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ |
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#define OP_SH_CODE19 6 /* 19 bit wait code. */ |
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#define OP_MASK_CODE19 0x7ffff |
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#define OP_SH_ALN 21 |
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#define OP_MASK_ALN 0x7 |
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#define OP_SH_VSEL 21 |
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#define OP_MASK_VSEL 0x1f |
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#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, |
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but 0x8-0xf don't select bytes. */ |
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#define OP_SH_VECBYTE 22 |
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#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ |
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#define OP_SH_VECALIGN 21 |
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#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ |
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#define OP_SH_INSMSB 11 |
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#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ |
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#define OP_SH_EXTMSBD 11 |
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#define OP_OP_COP0 0x10 |
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#define OP_OP_COP1 0x11 |
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#define OP_OP_COP2 0x12 |
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#define OP_OP_COP3 0x13 |
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#define OP_OP_LWC1 0x31 |
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#define OP_OP_LWC2 0x32 |
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#define OP_OP_LWC3 0x33 /* a.k.a. pref */ |
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#define OP_OP_LDC1 0x35 |
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#define OP_OP_LDC2 0x36 |
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#define OP_OP_LDC3 0x37 /* a.k.a. ld */ |
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#define OP_OP_SWC1 0x39 |
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#define OP_OP_SWC2 0x3a |
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#define OP_OP_SWC3 0x3b |
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#define OP_OP_SDC1 0x3d |
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#define OP_OP_SDC2 0x3e |
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#define OP_OP_SDC3 0x3f /* a.k.a. sd */ |
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/* Values in the 'VSEL' field. */ |
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#define MDMX_FMTSEL_IMM_QH 0x1d |
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#define MDMX_FMTSEL_IMM_OB 0x1e |
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#define MDMX_FMTSEL_VEC_QH 0x15 |
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#define MDMX_FMTSEL_VEC_OB 0x16 |
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/* This structure holds information for a particular instruction. */ |
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struct mips_opcode |
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{ |
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/* The name of the instruction. */ |
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const char *name; |
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/* A string describing the arguments for this instruction. */ |
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const char *args; |
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/* The basic opcode for the instruction. When assembling, this |
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opcode is modified by the arguments to produce the actual opcode |
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that is used. If pinfo is INSN_MACRO, then this is 0. */ |
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unsigned long match; |
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/* If pinfo is not INSN_MACRO, then this is a bit mask for the |
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relevant portions of the opcode when disassembling. If the |
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actual opcode anded with the match field equals the opcode field, |
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then we have found the correct instruction. If pinfo is |
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INSN_MACRO, then this field is the macro identifier. */ |
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unsigned long mask; |
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/* For a macro, this is INSN_MACRO. Otherwise, it is a collection |
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of bits describing the instruction, notably any relevant hazard |
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information. */ |
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unsigned long pinfo; |
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/* A collection of bits describing the instruction sets of which this |
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instruction or macro is a member. */ |
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unsigned long membership; |
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}; |
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/* These are the characters which may appear in the args field of an |
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instruction. They appear in the order in which the fields appear |
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when the instruction is used. Commas and parentheses in the args |
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string are ignored when assembling, and written into the output |
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when disassembling. |
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Each of these characters corresponds to a mask field defined above. |
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"<" 5 bit shift amount (OP_*_SHAMT) |
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">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) |
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"a" 26 bit target address (OP_*_TARGET) |
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"b" 5 bit base register (OP_*_RS) |
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"c" 10 bit breakpoint code (OP_*_CODE) |
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"d" 5 bit destination register specifier (OP_*_RD) |
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"h" 5 bit prefx hint (OP_*_PREFX) |
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"i" 16 bit unsigned immediate (OP_*_IMMEDIATE) |
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"j" 16 bit signed immediate (OP_*_DELTA) |
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"k" 5 bit cache opcode in target register position (OP_*_CACHE) |
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Also used for immediate operands in vr5400 vector insns. |
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"o" 16 bit signed offset (OP_*_DELTA) |
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"p" 16 bit PC relative branch target address (OP_*_DELTA) |
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"q" 10 bit extra breakpoint code (OP_*_CODE2) |
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"r" 5 bit same register used as both source and target (OP_*_RS) |
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"s" 5 bit source register specifier (OP_*_RS) |
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"t" 5 bit target register (OP_*_RT) |
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"u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) |
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"v" 5 bit same register used as both source and destination (OP_*_RS) |
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"w" 5 bit same register used as both target and destination (OP_*_RT) |
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"U" 5 bit same destination register in both OP_*_RD and OP_*_RT |
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(used by clo and clz) |
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"C" 25 bit coprocessor function code (OP_*_COPZ) |
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"B" 20 bit syscall/breakpoint function code (OP_*_CODE20) |
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"J" 19 bit wait function code (OP_*_CODE19) |
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"x" accept and ignore register name |
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"z" must be zero register |
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"K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) |
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"+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT). |
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Enforces: 0 <= pos < 32. |
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"+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB). |
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Requires that "+A" or "+E" occur first to set position. |
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Enforces: 0 < (pos+size) <= 32. |
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"+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD). |
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Requires that "+A" or "+E" occur first to set position. |
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Enforces: 0 < (pos+size) <= 32. |
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(Also used by "dext" w/ different limits, but limits for |
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that are checked by the M_DEXT macro.) |
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"+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT). |
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Enforces: 32 <= pos < 64. |
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"+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB). |
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Requires that "+A" or "+E" occur first to set position. |
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Enforces: 32 < (pos+size) <= 64. |
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"+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). |
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Requires that "+A" or "+E" occur first to set position. |
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Enforces: 32 < (pos+size) <= 64. |
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"+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). |
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Requires that "+A" or "+E" occur first to set position. |
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Enforces: 32 < (pos+size) <= 64. |
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Floating point instructions: |
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"D" 5 bit destination register (OP_*_FD) |
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"M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) |
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"N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) |
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"S" 5 bit fs source 1 register (OP_*_FS) |
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"T" 5 bit ft source 2 register (OP_*_FT) |
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"R" 5 bit fr source 3 register (OP_*_FR) |
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"V" 5 bit same register used as floating source and destination (OP_*_FS) |
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"W" 5 bit same register used as floating target and destination (OP_*_FT) |
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Coprocessor instructions: |
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"E" 5 bit target register (OP_*_RT) |
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"G" 5 bit destination register (OP_*_RD) |
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"H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) |
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"P" 5 bit performance-monitor register (OP_*_PERFREG) |
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"e" 5 bit vector register byte specifier (OP_*_VECBYTE) |
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"%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) |
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see also "k" above |
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"+D" Combined destination register ("G") and sel ("H") for CP0 ops, |
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for pretty-printing in disassembly only. |
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Macro instructions: |
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"A" General 32 bit expression |
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"I" 32 bit immediate (value placed in imm_expr). |
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"+I" 32 bit immediate (value placed in imm2_expr). |
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"F" 64 bit floating point constant in .rdata |
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"L" 64 bit floating point constant in .lit8 |
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"f" 32 bit floating point constant |
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"l" 32 bit floating point constant in .lit4 |
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MDMX instruction operands (note that while these use the FP register |
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fields, they accept both $fN and $vN names for the registers): |
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"O" MDMX alignment offset (OP_*_ALN) |
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"Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) |
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"X" MDMX destination register (OP_*_FD) |
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"Y" MDMX source register (OP_*_FS) |
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"Z" MDMX source register (OP_*_FT) |
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Other: |
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"()" parens surrounding optional value |
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"," separates operands |
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"[]" brackets around index for vector-op scalar operand specifier (vr5400) |
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"+" Start of extension sequence. |
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|
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Characters used so far, for quick reference when adding more: |
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"%[]<>(),+" |
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"ABCDEFGHIJKLMNOPQRSTUVWXYZ" |
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"abcdefhijklopqrstuvwxz" |
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|
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Extension character sequences used so far ("+" followed by the |
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following), for quick reference when adding more: |
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"ABCDEFGHI" |
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*/ |
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|
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/* These are the bits which may be set in the pinfo field of an |
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instructions, if it is not equal to INSN_MACRO. */ |
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|
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/* Modifies the general purpose register in OP_*_RD. */ |
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#define INSN_WRITE_GPR_D 0x00000001 |
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/* Modifies the general purpose register in OP_*_RT. */ |
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#define INSN_WRITE_GPR_T 0x00000002 |
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/* Modifies general purpose register 31. */ |
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#define INSN_WRITE_GPR_31 0x00000004 |
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/* Modifies the floating point register in OP_*_FD. */ |
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#define INSN_WRITE_FPR_D 0x00000008 |
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/* Modifies the floating point register in OP_*_FS. */ |
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#define INSN_WRITE_FPR_S 0x00000010 |
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/* Modifies the floating point register in OP_*_FT. */ |
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#define INSN_WRITE_FPR_T 0x00000020 |
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/* Reads the general purpose register in OP_*_RS. */ |
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#define INSN_READ_GPR_S 0x00000040 |
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/* Reads the general purpose register in OP_*_RT. */ |
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#define INSN_READ_GPR_T 0x00000080 |
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/* Reads the floating point register in OP_*_FS. */ |
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#define INSN_READ_FPR_S 0x00000100 |
|
376 |
/* Reads the floating point register in OP_*_FT. */ |
|
377 |
#define INSN_READ_FPR_T 0x00000200 |
|
378 |
/* Reads the floating point register in OP_*_FR. */ |
|
379 |
#define INSN_READ_FPR_R 0x00000400 |
|
380 |
/* Modifies coprocessor condition code. */ |
|
381 |
#define INSN_WRITE_COND_CODE 0x00000800 |
|
382 |
/* Reads coprocessor condition code. */ |
|
383 |
#define INSN_READ_COND_CODE 0x00001000 |
|
384 |
/* TLB operation. */ |
|
385 |
#define INSN_TLB 0x00002000 |
|
386 |
/* Reads coprocessor register other than floating point register. */ |
|
387 |
#define INSN_COP 0x00004000 |
|
388 |
/* Instruction loads value from memory, requiring delay. */ |
|
389 |
#define INSN_LOAD_MEMORY_DELAY 0x00008000 |
|
390 |
/* Instruction loads value from coprocessor, requiring delay. */ |
|
391 |
#define INSN_LOAD_COPROC_DELAY 0x00010000 |
|
392 |
/* Instruction has unconditional branch delay slot. */ |
|
393 |
#define INSN_UNCOND_BRANCH_DELAY 0x00020000 |
|
394 |
/* Instruction has conditional branch delay slot. */ |
|
395 |
#define INSN_COND_BRANCH_DELAY 0x00040000 |
|
396 |
/* Conditional branch likely: if branch not taken, insn nullified. */ |
|
397 |
#define INSN_COND_BRANCH_LIKELY 0x00080000 |
|
398 |
/* Moves to coprocessor register, requiring delay. */ |
|
399 |
#define INSN_COPROC_MOVE_DELAY 0x00100000 |
|
400 |
/* Loads coprocessor register from memory, requiring delay. */ |
|
401 |
#define INSN_COPROC_MEMORY_DELAY 0x00200000 |
|
402 |
/* Reads the HI register. */ |
|
403 |
#define INSN_READ_HI 0x00400000 |
|
404 |
/* Reads the LO register. */ |
|
405 |
#define INSN_READ_LO 0x00800000 |
|
406 |
/* Modifies the HI register. */ |
|
407 |
#define INSN_WRITE_HI 0x01000000 |
|
408 |
/* Modifies the LO register. */ |
|
409 |
#define INSN_WRITE_LO 0x02000000 |
|
410 |
/* Takes a trap (easier to keep out of delay slot). */ |
|
411 |
#define INSN_TRAP 0x04000000 |
|
412 |
/* Instruction stores value into memory. */ |
|
413 |
#define INSN_STORE_MEMORY 0x08000000 |
|
414 |
/* Instruction uses single precision floating point. */ |
|
415 |
#define FP_S 0x10000000 |
|
416 |
/* Instruction uses double precision floating point. */ |
|
417 |
#define FP_D 0x20000000 |
|
418 |
/* Instruction is part of the tx39's integer multiply family. */ |
|
419 |
#define INSN_MULT 0x40000000 |
|
420 |
/* Instruction synchronize shared memory. */ |
|
421 |
#define INSN_SYNC 0x80000000 |
|
422 |
/* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */ |
|
423 |
#define INSN_READ_MDMX_ACC 0 |
|
424 |
/* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */ |
|
425 |
#define INSN_WRITE_MDMX_ACC 0 |
|
426 |
|
|
427 |
/* Instruction is actually a macro. It should be ignored by the |
|
428 |
disassembler, and requires special treatment by the assembler. */ |
|
429 |
#define INSN_MACRO 0xffffffff |
|
430 |
|
|
431 |
/* Masks used to mark instructions to indicate which MIPS ISA level |
|
432 |
they were introduced in. ISAs, as defined below, are logical |
|
433 |
ORs of these bits, indicating that they support the instructions |
|
434 |
defined at the given level. */ |
|
435 |
|
|
436 |
#define INSN_ISA_MASK 0x00000fff |
|
437 |
#define INSN_ISA1 0x00000001 |
|
438 |
#define INSN_ISA2 0x00000002 |
|
439 |
#define INSN_ISA3 0x00000004 |
|
440 |
#define INSN_ISA4 0x00000008 |
|
441 |
#define INSN_ISA5 0x00000010 |
|
442 |
#define INSN_ISA32 0x00000020 |
|
443 |
#define INSN_ISA64 0x00000040 |
|
444 |
#define INSN_ISA32R2 0x00000080 |
|
445 |
#define INSN_ISA64R2 0x00000100 |
|
446 |
|
|
447 |
/* Masks used for MIPS-defined ASEs. */ |
|
448 |
#define INSN_ASE_MASK 0x0000f000 |
|
449 |
|
|
450 |
/* MIPS 16 ASE */ |
|
451 |
#define INSN_MIPS16 0x00002000 |
|
452 |
/* MIPS-3D ASE */ |
|
453 |
#define INSN_MIPS3D 0x00004000 |
|
454 |
/* MDMX ASE */ |
|
455 |
#define INSN_MDMX 0x00008000 |
|
456 |
|
|
457 |
/* Chip specific instructions. These are bitmasks. */ |
|
458 |
|
|
459 |
/* MIPS R4650 instruction. */ |
|
460 |
#define INSN_4650 0x00010000 |
|
461 |
/* LSI R4010 instruction. */ |
|
462 |
#define INSN_4010 0x00020000 |
|
463 |
/* NEC VR4100 instruction. */ |
|
464 |
#define INSN_4100 0x00040000 |
|
465 |
/* Toshiba R3900 instruction. */ |
|
466 |
#define INSN_3900 0x00080000 |
|
467 |
/* MIPS R10000 instruction. */ |
|
468 |
#define INSN_10000 0x00100000 |
|
469 |
/* Broadcom SB-1 instruction. */ |
|
470 |
#define INSN_SB1 0x00200000 |
|
471 |
/* NEC VR4111/VR4181 instruction. */ |
|
472 |
#define INSN_4111 0x00400000 |
|
473 |
/* NEC VR4120 instruction. */ |
|
474 |
#define INSN_4120 0x00800000 |
|
475 |
/* NEC VR5400 instruction. */ |
|
476 |
#define INSN_5400 0x01000000 |
|
477 |
/* NEC VR5500 instruction. */ |
|
478 |
#define INSN_5500 0x02000000 |
|
479 |
|
|
480 |
/* MIPS ISA defines, use instead of hardcoding ISA level. */ |
|
481 |
|
|
482 |
#define ISA_UNKNOWN 0 /* Gas internal use. */ |
|
483 |
#define ISA_MIPS1 (INSN_ISA1) |
|
484 |
#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2) |
|
485 |
#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) |
|
486 |
#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) |
|
487 |
#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) |
|
488 |
|
|
489 |
#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) |
|
490 |
#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) |
|
491 |
|
|
492 |
#define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) |
|
493 |
#define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) |
|
494 |
|
|
495 |
|
|
496 |
/* CPU defines, use instead of hardcoding processor number. Keep this |
|
497 |
in sync with bfd/archures.c in order for machine selection to work. */ |
|
498 |
#define CPU_UNKNOWN 0 /* Gas internal use. */ |
|
499 |
#define CPU_R3000 3000 |
|
500 |
#define CPU_R3900 3900 |
|
501 |
#define CPU_R4000 4000 |
|
502 |
#define CPU_R4010 4010 |
|
503 |
#define CPU_VR4100 4100 |
|
504 |
#define CPU_R4111 4111 |
|
505 |
#define CPU_VR4120 4120 |
|
506 |
#define CPU_R4300 4300 |
|
507 |
#define CPU_R4400 4400 |
|
508 |
#define CPU_R4600 4600 |
|
509 |
#define CPU_R4650 4650 |
|
510 |
#define CPU_R5000 5000 |
|
511 |
#define CPU_VR5400 5400 |
|
512 |
#define CPU_VR5500 5500 |
|
513 |
#define CPU_R6000 6000 |
|
514 |
#define CPU_RM7000 7000 |
|
515 |
#define CPU_R8000 8000 |
|
516 |
#define CPU_R10000 10000 |
|
517 |
#define CPU_R12000 12000 |
|
518 |
#define CPU_MIPS16 16 |
|
519 |
#define CPU_MIPS32 32 |
|
520 |
#define CPU_MIPS32R2 33 |
|
521 |
#define CPU_MIPS5 5 |
|
522 |
#define CPU_MIPS64 64 |
|
523 |
#define CPU_MIPS64R2 65 |
|
524 |
#define CPU_SB1 12310201 /* octal 'SB', 01. */ |
|
525 |
|
|
526 |
/* Test for membership in an ISA including chip specific ISAs. INSN |
|
527 |
is pointer to an element of the opcode table; ISA is the specified |
|
528 |
ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to |
|
529 |
test, or zero if no CPU specific ISA test is desired. */ |
|
530 |
|
|
531 |
#define OPCODE_IS_MEMBER(insn, isa, cpu) \ |
|
532 |
(((insn)->membership & isa) != 0 \ |
|
533 |
|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ |
|
534 |
|| (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ |
|
535 |
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ |
|
536 |
|| (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ |
|
537 |
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ |
|
538 |
|| ((cpu == CPU_R10000 || cpu == CPU_R12000) \ |
|
539 |
&& ((insn)->membership & INSN_10000) != 0) \ |
|
540 |
|| (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ |
|
541 |
|| (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ |
|
542 |
|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ |
|
543 |
|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ |
|
544 |
|| (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ |
|
545 |
|| 0) /* Please keep this term for easier source merging. */ |
|
546 |
|
|
547 |
/* This is a list of macro expanded instructions. |
|
548 |
|
|
549 |
_I appended means immediate |
|
550 |
_A appended means address |
|
551 |
_AB appended means address with base register |
|
552 |
_D appended means 64 bit floating point constant |
|
553 |
_S appended means 32 bit floating point constant. */ |
|
554 |
|
|
555 |
enum |
|
556 |
{ |
|
557 |
M_ABS, |
|
558 |
M_ADD_I, |
|
559 |
M_ADDU_I, |
|
560 |
M_AND_I, |
|
561 |
M_BEQ, |
|
562 |
M_BEQ_I, |
|
563 |
M_BEQL_I, |
|
564 |
M_BGE, |
|
565 |
M_BGEL, |
|
566 |
M_BGE_I, |
|
567 |
M_BGEL_I, |
|
568 |
M_BGEU, |
|
569 |
M_BGEUL, |
|
570 |
M_BGEU_I, |
|
571 |
M_BGEUL_I, |
|
572 |
M_BGT, |
|
573 |
M_BGTL, |
|
574 |
M_BGT_I, |
|
575 |
M_BGTL_I, |
|
576 |
M_BGTU, |
|
577 |
M_BGTUL, |
|
578 |
M_BGTU_I, |
|
579 |
M_BGTUL_I, |
|
580 |
M_BLE, |
|
581 |
M_BLEL, |
|
582 |
M_BLE_I, |
|
583 |
M_BLEL_I, |
|
584 |
M_BLEU, |
|
585 |
M_BLEUL, |
|
586 |
M_BLEU_I, |
|
587 |
M_BLEUL_I, |
|
588 |
M_BLT, |
|
589 |
M_BLTL, |
|
590 |
M_BLT_I, |
|
591 |
M_BLTL_I, |
|
592 |
M_BLTU, |
|
593 |
M_BLTUL, |
|
594 |
M_BLTU_I, |
|
595 |
M_BLTUL_I, |
|
596 |
M_BNE, |
|
597 |
M_BNE_I, |
|
598 |
M_BNEL_I, |
|
599 |
M_DABS, |
|
600 |
M_DADD_I, |
|
601 |
M_DADDU_I, |
|
602 |
M_DDIV_3, |
|
603 |
M_DDIV_3I, |
|
604 |
M_DDIVU_3, |
|
605 |
M_DDIVU_3I, |
|
606 |
M_DEXT, |
|
607 |
M_DINS, |
|
608 |
M_DIV_3, |
|
609 |
M_DIV_3I, |
|
610 |
M_DIVU_3, |
|
611 |
M_DIVU_3I, |
|
612 |
M_DLA_AB, |
|
613 |
M_DLCA_AB, |
|
614 |
M_DLI, |
|
615 |
M_DMUL, |
|
616 |
M_DMUL_I, |
|
617 |
M_DMULO, |
|
618 |
M_DMULO_I, |
|
619 |
M_DMULOU, |
|
620 |
M_DMULOU_I, |
|
621 |
M_DREM_3, |
|
622 |
M_DREM_3I, |
|
623 |
M_DREMU_3, |
|
624 |
M_DREMU_3I, |
|
625 |
M_DSUB_I, |
|
626 |
M_DSUBU_I, |
|
627 |
M_DSUBU_I_2, |
|
628 |
M_J_A, |
|
629 |
M_JAL_1, |
|
630 |
M_JAL_2, |
|
631 |
M_JAL_A, |
|
632 |
M_L_DOB, |
|
633 |
M_L_DAB, |
|
634 |
M_LA_AB, |
|
635 |
M_LB_A, |
|
636 |
M_LB_AB, |
|
637 |
M_LBU_A, |
|
638 |
M_LBU_AB, |
|
639 |
M_LCA_AB, |
|
640 |
M_LD_A, |
|
641 |
M_LD_OB, |
|
642 |
M_LD_AB, |
|
643 |
M_LDC1_AB, |
|
644 |
M_LDC2_AB, |
|
645 |
M_LDC3_AB, |
|
646 |
M_LDL_AB, |
|
647 |
M_LDR_AB, |
|
648 |
M_LH_A, |
|
649 |
M_LH_AB, |
|
650 |
M_LHU_A, |
|
651 |
M_LHU_AB, |
|
652 |
M_LI, |
|
653 |
M_LI_D, |
|
654 |
M_LI_DD, |
|
655 |
M_LI_S, |
|
656 |
M_LI_SS, |
|
657 |
M_LL_AB, |
|
658 |
M_LLD_AB, |
|
659 |
M_LS_A, |
|
660 |
M_LW_A, |
|
661 |
M_LW_AB, |
|
662 |
M_LWC0_A, |
|
663 |
M_LWC0_AB, |
|
664 |
M_LWC1_A, |
|
665 |
M_LWC1_AB, |
|
666 |
M_LWC2_A, |
|
667 |
M_LWC2_AB, |
|
668 |
M_LWC3_A, |
|
669 |
M_LWC3_AB, |
|
670 |
M_LWL_A, |
|
671 |
M_LWL_AB, |
|
672 |
M_LWR_A, |
|
673 |
M_LWR_AB, |
|
674 |
M_LWU_AB, |
|
675 |
M_MOVE, |
|
676 |
M_MUL, |
|
677 |
M_MUL_I, |
|
678 |
M_MULO, |
|
679 |
M_MULO_I, |
|
680 |
M_MULOU, |
|
681 |
M_MULOU_I, |
|
682 |
M_NOR_I, |
|
683 |
M_OR_I, |
|
684 |
M_REM_3, |
|
685 |
M_REM_3I, |
|
686 |
M_REMU_3, |
|
687 |
M_REMU_3I, |
|
688 |
M_DROL, |
|
689 |
M_ROL, |
|
690 |
M_DROL_I, |
|
691 |
M_ROL_I, |
|
692 |
M_DROR, |
|
693 |
M_ROR, |
|
694 |
M_DROR_I, |
|
695 |
M_ROR_I, |
|
696 |
M_S_DA, |
|
697 |
M_S_DOB, |
|
698 |
M_S_DAB, |
|
699 |
M_S_S, |
|
700 |
M_SC_AB, |
|
701 |
M_SCD_AB, |
|
702 |
M_SD_A, |
|
703 |
M_SD_OB, |
|
704 |
M_SD_AB, |
|
705 |
M_SDC1_AB, |
|
706 |
M_SDC2_AB, |
|
707 |
M_SDC3_AB, |
|
708 |
M_SDL_AB, |
|
709 |
M_SDR_AB, |
|
710 |
M_SEQ, |
|
711 |
M_SEQ_I, |
|
712 |
M_SGE, |
|
713 |
M_SGE_I, |
|
714 |
M_SGEU, |
|
715 |
M_SGEU_I, |
|
716 |
M_SGT, |
|
717 |
M_SGT_I, |
|
718 |
M_SGTU, |
|
719 |
M_SGTU_I, |
|
720 |
M_SLE, |
|
721 |
M_SLE_I, |
|
722 |
M_SLEU, |
|
723 |
M_SLEU_I, |
|
724 |
M_SLT_I, |
|
725 |
M_SLTU_I, |
|
726 |
M_SNE, |
|
727 |
M_SNE_I, |
|
728 |
M_SB_A, |
|
729 |
M_SB_AB, |
|
730 |
M_SH_A, |
|
731 |
M_SH_AB, |
|
732 |
M_SW_A, |
|
733 |
M_SW_AB, |
|
734 |
M_SWC0_A, |
|
735 |
M_SWC0_AB, |
|
736 |
M_SWC1_A, |
|
737 |
M_SWC1_AB, |
|
738 |
M_SWC2_A, |
|
739 |
M_SWC2_AB, |
|
740 |
M_SWC3_A, |
|
741 |
M_SWC3_AB, |
|
742 |
M_SWL_A, |
|
743 |
M_SWL_AB, |
|
744 |
M_SWR_A, |
|
745 |
M_SWR_AB, |
|
746 |
M_SUB_I, |
|
747 |
M_SUBU_I, |
|
748 |
M_SUBU_I_2, |
|
749 |
M_TEQ_I, |
|
750 |
M_TGE_I, |
|
751 |
M_TGEU_I, |
|
752 |
M_TLT_I, |
|
753 |
M_TLTU_I, |
|
754 |
M_TNE_I, |
|
755 |
M_TRUNCWD, |
|
756 |
M_TRUNCWS, |
|
757 |
M_ULD, |
|
758 |
M_ULD_A, |
|
759 |
M_ULH, |
|
760 |
M_ULH_A, |
|
761 |
M_ULHU, |
|
762 |
M_ULHU_A, |
|
763 |
M_ULW, |
|
764 |
M_ULW_A, |
|
765 |
M_USH, |
|
766 |
M_USH_A, |
|
767 |
M_USW, |
|
768 |
M_USW_A, |
|
769 |
M_USD, |
|
770 |
M_USD_A, |
|
771 |
M_XOR_I, |
|
772 |
M_COP0, |
|
773 |
M_COP1, |
|
774 |
M_COP2, |
|
775 |
M_COP3, |
|
776 |
M_NUM_MACROS |
|
777 |
}; |
|
778 |
|
|
779 |
|
|
780 |
/* The order of overloaded instructions matters. Label arguments and |
|
781 |
register arguments look the same. Instructions that can have either |
|
782 |
for arguments must apear in the correct order in this table for the |
|
783 |
assembler to pick the right one. In other words, entries with |
|
784 |
immediate operands must apear after the same instruction with |
|
785 |
registers. |
|
786 |
|
|
787 |
Many instructions are short hand for other instructions (i.e., The |
|
788 |
jal <register> instruction is short for jalr <register>). */ |
|
789 |
|
|
790 |
extern const struct mips_opcode mips_builtin_opcodes[]; |
|
791 |
extern const int bfd_mips_num_builtin_opcodes; |
|
792 |
extern struct mips_opcode *mips_opcodes; |
|
793 |
extern int bfd_mips_num_opcodes; |
|
794 |
#define NUMOPCODES bfd_mips_num_opcodes |
|
795 |
|
|
796 |
|
|
797 |
/* The rest of this file adds definitions for the mips16 TinyRISC |
|
798 |
processor. */ |
|
799 |
|
|
800 |
/* These are the bitmasks and shift counts used for the different |
|
801 |
fields in the instruction formats. Other than OP, no masks are |
|
802 |
provided for the fixed portions of an instruction, since they are |
|
803 |
not needed. |
|
804 |
|
|
805 |
The I format uses IMM11. |
|
806 |
|
|
807 |
The RI format uses RX and IMM8. |
|
808 |
|
|
809 |
The RR format uses RX, and RY. |
|
810 |
|
|
811 |
The RRI format uses RX, RY, and IMM5. |
|
812 |
|
|
813 |
The RRR format uses RX, RY, and RZ. |
|
814 |
|
|
815 |
The RRI_A format uses RX, RY, and IMM4. |
|
816 |
|
|
817 |
The SHIFT format uses RX, RY, and SHAMT. |
|
818 |
|
|
819 |
The I8 format uses IMM8. |
|
820 |
|
|
821 |
The I8_MOVR32 format uses RY and REGR32. |
|
822 |
|
|
823 |
The IR_MOV32R format uses REG32R and MOV32Z. |
|
824 |
|
|
825 |
The I64 format uses IMM8. |
|
826 |
|
|
827 |
The RI64 format uses RY and IMM5. |
|
828 |
*/ |
|
829 |
|
|
830 |
#define MIPS16OP_MASK_OP 0x1f |
|
831 |
#define MIPS16OP_SH_OP 11 |
|
832 |
#define MIPS16OP_MASK_IMM11 0x7ff |
|
833 |
#define MIPS16OP_SH_IMM11 0 |
|
834 |
#define MIPS16OP_MASK_RX 0x7 |
|
835 |
#define MIPS16OP_SH_RX 8 |
|
836 |
#define MIPS16OP_MASK_IMM8 0xff |
|
837 |
#define MIPS16OP_SH_IMM8 0 |
|
838 |
#define MIPS16OP_MASK_RY 0x7 |
|
839 |
#define MIPS16OP_SH_RY 5 |
|
840 |
#define MIPS16OP_MASK_IMM5 0x1f |
|
841 |
#define MIPS16OP_SH_IMM5 0 |
|
842 |
#define MIPS16OP_MASK_RZ 0x7 |
|
843 |
#define MIPS16OP_SH_RZ 2 |
|
844 |
#define MIPS16OP_MASK_IMM4 0xf |
|
845 |
#define MIPS16OP_SH_IMM4 0 |
|
846 |
#define MIPS16OP_MASK_REGR32 0x1f |
|
847 |
#define MIPS16OP_SH_REGR32 0 |
|
848 |
#define MIPS16OP_MASK_REG32R 0x1f |
|
849 |
#define MIPS16OP_SH_REG32R 3 |
|
850 |
#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) |
|
851 |
#define MIPS16OP_MASK_MOVE32Z 0x7 |
|
852 |
#define MIPS16OP_SH_MOVE32Z 0 |
|
853 |
#define MIPS16OP_MASK_IMM6 0x3f |
|
854 |
#define MIPS16OP_SH_IMM6 5 |
|
855 |
|
|
856 |
/* These are the characters which may appears in the args field of an |
|
857 |
instruction. They appear in the order in which the fields appear |
|
858 |
when the instruction is used. Commas and parentheses in the args |
|
859 |
string are ignored when assembling, and written into the output |
|
860 |
when disassembling. |
|
861 |
|
|
862 |
"y" 3 bit register (MIPS16OP_*_RY) |
|
863 |
"x" 3 bit register (MIPS16OP_*_RX) |
|
864 |
"z" 3 bit register (MIPS16OP_*_RZ) |
|
865 |
"Z" 3 bit register (MIPS16OP_*_MOVE32Z) |
|
866 |
"v" 3 bit same register as source and destination (MIPS16OP_*_RX) |
|
867 |
"w" 3 bit same register as source and destination (MIPS16OP_*_RY) |
|
868 |
"0" zero register ($0) |
|
869 |
"S" stack pointer ($sp or $29) |
|
870 |
"P" program counter |
|
871 |
"R" return address register ($ra or $31) |
|
872 |
"X" 5 bit MIPS register (MIPS16OP_*_REGR32) |
|
873 |
"Y" 5 bit MIPS register (MIPS16OP_*_REG32R) |
|
874 |
"6" 6 bit unsigned break code (MIPS16OP_*_IMM6) |
|
875 |
"a" 26 bit jump address |
|
876 |
"e" 11 bit extension value |
|
877 |
"l" register list for entry instruction |
|
878 |
"L" register list for exit instruction |
|
879 |
|
|
880 |
The remaining codes may be extended. Except as otherwise noted, |
|
881 |
the full extended operand is a 16 bit signed value. |
|
882 |
"<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) |
|
883 |
">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) |
|
884 |
"[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) |
|
885 |
"]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) |
|
886 |
"4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) |
|
887 |
"5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) |
|
888 |
"H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) |
|
889 |
"W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) |
|
890 |
"D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) |
|
891 |
"j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) |
|
892 |
"8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) |
|
893 |
"V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) |
|
894 |
"C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) |
|
895 |
"U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) |
|
896 |
"k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) |
|
897 |
"K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) |
|
898 |
"p" 8 bit conditional branch address (MIPS16OP_*_IMM8) |
|
899 |
"q" 11 bit branch address (MIPS16OP_*_IMM11) |
|
900 |
"A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) |
|
901 |
"B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) |
|
902 |
"E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) |
|
903 |
*/ |
|
904 |
|
|
905 |
/* For the mips16, we use the same opcode table format and a few of |
|
906 |
the same flags. However, most of the flags are different. */ |
|
907 |
|
|
908 |
/* Modifies the register in MIPS16OP_*_RX. */ |
|
909 |
#define MIPS16_INSN_WRITE_X 0x00000001 |
|
910 |
/* Modifies the register in MIPS16OP_*_RY. */ |
|
911 |
#define MIPS16_INSN_WRITE_Y 0x00000002 |
|
912 |
/* Modifies the register in MIPS16OP_*_RZ. */ |
|
913 |
#define MIPS16_INSN_WRITE_Z 0x00000004 |
|
914 |
/* Modifies the T ($24) register. */ |
|
915 |
#define MIPS16_INSN_WRITE_T 0x00000008 |
|
916 |
/* Modifies the SP ($29) register. */ |
|
917 |
#define MIPS16_INSN_WRITE_SP 0x00000010 |
|
918 |
/* Modifies the RA ($31) register. */ |
|
919 |
#define MIPS16_INSN_WRITE_31 0x00000020 |
|
920 |
/* Modifies the general purpose register in MIPS16OP_*_REG32R. */ |
|
921 |
#define MIPS16_INSN_WRITE_GPR_Y 0x00000040 |
|
922 |
/* Reads the register in MIPS16OP_*_RX. */ |
|
923 |
#define MIPS16_INSN_READ_X 0x00000080 |
|
924 |
/* Reads the register in MIPS16OP_*_RY. */ |
|
925 |
#define MIPS16_INSN_READ_Y 0x00000100 |
|
926 |
/* Reads the register in MIPS16OP_*_MOVE32Z. */ |
|
927 |
#define MIPS16_INSN_READ_Z 0x00000200 |
|
928 |
/* Reads the T ($24) register. */ |
|
929 |
#define MIPS16_INSN_READ_T 0x00000400 |
|
930 |
/* Reads the SP ($29) register. */ |
|
931 |
#define MIPS16_INSN_READ_SP 0x00000800 |
|
932 |
/* Reads the RA ($31) register. */ |
|
933 |
#define MIPS16_INSN_READ_31 0x00001000 |
|
934 |
/* Reads the program counter. */ |
|
935 |
#define MIPS16_INSN_READ_PC 0x00002000 |
|
936 |
/* Reads the general purpose register in MIPS16OP_*_REGR32. */ |
|
937 |
#define MIPS16_INSN_READ_GPR_X 0x00004000 |
|
938 |
/* Is a branch insn. */ |
|
939 |
#define MIPS16_INSN_BRANCH 0x00010000 |
|
940 |
|
|
941 |
/* The following flags have the same value for the mips16 opcode |
|
942 |
table: |
|
943 |
INSN_UNCOND_BRANCH_DELAY |
|
944 |
INSN_COND_BRANCH_DELAY |
|
945 |
INSN_COND_BRANCH_LIKELY (never used) |
|
946 |
INSN_READ_HI |
|
947 |
INSN_READ_LO |
|
948 |
INSN_WRITE_HI |
|
949 |
INSN_WRITE_LO |
|
950 |
INSN_TRAP |
|
951 |
INSN_ISA3 |
|
952 |
*/ |
|
953 |
|
|
954 |
extern const struct mips_opcode mips16_opcodes[]; |
|
955 |
extern const int bfd_mips16_num_opcodes; |
|
956 |
|
|
957 |
/* Short hand so the lines aren't too long. */ |
|
958 |
|
|
959 |
#define LDD INSN_LOAD_MEMORY_DELAY |
|
960 |
#define LCD INSN_LOAD_COPROC_DELAY |
|
961 |
#define UBD INSN_UNCOND_BRANCH_DELAY |
|
962 |
#define CBD INSN_COND_BRANCH_DELAY |
|
963 |
#define COD INSN_COPROC_MOVE_DELAY |
|
964 |
#define CLD INSN_COPROC_MEMORY_DELAY |
|
965 |
#define CBL INSN_COND_BRANCH_LIKELY |
|
966 |
#define TRAP INSN_TRAP |
|
967 |
#define SM INSN_STORE_MEMORY |
|
968 |
|
|
969 |
#define WR_d INSN_WRITE_GPR_D |
|
970 |
#define WR_t INSN_WRITE_GPR_T |
|
971 |
#define WR_31 INSN_WRITE_GPR_31 |
|
972 |
#define WR_D INSN_WRITE_FPR_D |
|
973 |
#define WR_T INSN_WRITE_FPR_T |
|
974 |
#define WR_S INSN_WRITE_FPR_S |
|
975 |
#define RD_s INSN_READ_GPR_S |
|
976 |
#define RD_b INSN_READ_GPR_S |
|
977 |
#define RD_t INSN_READ_GPR_T |
|
978 |
#define RD_S INSN_READ_FPR_S |
|
979 |
#define RD_T INSN_READ_FPR_T |
|
980 |
#define RD_R INSN_READ_FPR_R |
|
981 |
#define WR_CC INSN_WRITE_COND_CODE |
|
982 |
#define RD_CC INSN_READ_COND_CODE |
|
983 |
#define RD_C0 INSN_COP |
|
984 |
#define RD_C1 INSN_COP |
|
985 |
#define RD_C2 INSN_COP |
|
986 |
#define RD_C3 INSN_COP |
|
987 |
#define WR_C0 INSN_COP |
|
988 |
#define WR_C1 INSN_COP |
|
989 |
#define WR_C2 INSN_COP |
|
990 |
#define WR_C3 INSN_COP |
|
991 |
|
|
992 |
#define WR_HI INSN_WRITE_HI |
|
993 |
#define RD_HI INSN_READ_HI |
|
994 |
#define MOD_HI WR_HI|RD_HI |
|
995 |
|
|
996 |
#define WR_LO INSN_WRITE_LO |
|
997 |
#define RD_LO INSN_READ_LO |
|
998 |
#define MOD_LO WR_LO|RD_LO |
|
999 |
|
|
1000 |
#define WR_HILO WR_HI|WR_LO |
|
1001 |
#define RD_HILO RD_HI|RD_LO |
|
1002 |
#define MOD_HILO WR_HILO|RD_HILO |
|
1003 |
|
|
1004 |
#define IS_M INSN_MULT |
|
1005 |
|
|
1006 |
#define WR_MACC INSN_WRITE_MDMX_ACC |
|
1007 |
#define RD_MACC INSN_READ_MDMX_ACC |
|
1008 |
|
|
1009 |
#define I1 INSN_ISA1 |
|
1010 |
#define I2 INSN_ISA2 |
|
1011 |
#define I3 INSN_ISA3 |
|
1012 |
#define I4 INSN_ISA4 |
|
1013 |
#define I5 INSN_ISA5 |
|
1014 |
#define I32 INSN_ISA32 |
|
1015 |
#define I64 INSN_ISA64 |
|
1016 |
#define I33 INSN_ISA32R2 |
|
1017 |
#define I65 INSN_ISA64R2 |
|
1018 |
|
|
1019 |
/* MIPS64 MIPS-3D ASE support. */ |
|
1020 |
#define I16 INSN_MIPS16 |
|
1021 |
|
|
1022 |
/* MIPS64 MIPS-3D ASE support. */ |
|
1023 |
#define M3D INSN_MIPS3D |
|
1024 |
|
|
1025 |
/* MIPS64 MDMX ASE support. */ |
|
1026 |
#define MX INSN_MDMX |
|
1027 |
|
|
1028 |
#define P3 INSN_4650 |
|
1029 |
#define L1 INSN_4010 |
|
1030 |
#define V1 (INSN_4100 | INSN_4111 | INSN_4120) |
|
1031 |
#define T3 INSN_3900 |
|
1032 |
#define M1 INSN_10000 |
|
1033 |
#define SB1 INSN_SB1 |
|
1034 |
#define N411 INSN_4111 |
|
1035 |
#define N412 INSN_4120 |
|
1036 |
#define N5 (INSN_5400 | INSN_5500) |
|
1037 |
#define N54 INSN_5400 |
|
1038 |
#define N55 INSN_5500 |
|
1039 |
|
|
1040 |
#define G1 (T3 \ |
|
1041 |
) |
|
1042 |
|
|
1043 |
#define G2 (T3 \ |
|
1044 |
) |
|
1045 |
|
|
1046 |
#define G3 (I4 \ |
|
1047 |
) |
|
1048 |
|
|
1049 |
/* The order of overloaded instructions matters. Label arguments and |
|
1050 |
register arguments look the same. Instructions that can have either |
|
1051 |
for arguments must apear in the correct order in this table for the |
|
1052 |
assembler to pick the right one. In other words, entries with |
|
1053 |
immediate operands must apear after the same instruction with |
|
1054 |
registers. |
|
1055 |
|
|
1056 |
Because of the lookup algorithm used, entries with the same opcode |
|
1057 |
name must be contiguous. |
|
1058 |
|
|
1059 |
Many instructions are short hand for other instructions (i.e., The |
|
1060 |
jal <register> instruction is short for jalr <register>). */ |
|
1061 |
|
|
1062 |
const struct mips_opcode mips_builtin_opcodes[] = |
|
1063 |
{ |
|
1064 |
/* These instructions appear first so that the disassembler will find |
|
1065 |
them first. The assemblers uses a hash table based on the |
|
1066 |
instruction name anyhow. */ |
|
1067 |
/* name, args, match, mask, pinfo, membership */ |
|
1068 |
{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, I4|I32|G3 }, |
|
1069 |
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 }, |
|
1070 |
{"nop", "", 0x00000000, 0xffffffff, 0, I1 }, /* sll */ |
|
1071 |
{"ssnop", "", 0x00000040, 0xffffffff, 0, I32|N55 }, /* sll */ |
|
1072 |
{"ehb", "", 0x000000c0, 0xffffffff, 0, I33 }, /* sll */ |
|
1073 |
{"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */ |
|
1074 |
{"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */ |
|
1075 |
{"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 }, |
|
1076 |
{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, I1 }, |
|
1077 |
{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */ |
|
1078 |
{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */ |
|
1079 |
{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */ |
|
1080 |
{"b", "p", 0x10000000, 0xffff0000, UBD, I1 },/* beq 0,0 */ |
|
1081 |
{"b", "p", 0x04010000, 0xffff0000, UBD, I1 },/* bgez 0 */ |
|
1082 |
{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, I1 },/* bgezal 0*/ |
|
1083 |
|
|
1084 |
{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, I1 }, |
|
1085 |
{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, I1 }, |
|
1086 |
{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, I1 }, |
|
1087 |
{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, I5 }, |
|
1088 |
{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, |
|
1089 |
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, I1 }, |
|
1090 |
{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, |
|
1091 |
{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, |
|
1092 |
{"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, |
|
1093 |
{"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, |
|
1094 |
{"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, N54 }, |
|
1095 |
{"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, |
|
1096 |
{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, |
|
1097 |
{"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, |
|
1098 |
{"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 }, |
|
1099 |
{"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX }, |
|
1100 |
{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 }, |
|
1101 |
{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 }, |
|
1102 |
{"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 }, |
|
1103 |
{"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX }, |
|
1104 |
{"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D }, |
|
1105 |
{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, |
|
1106 |
{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, I1 }, |
|
1107 |
{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, |
|
1108 |
{"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, N54 }, |
|
1109 |
{"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, MX }, |
|
1110 |
{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, I5 }, |
|
1111 |
{"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, MX|SB1 }, |
|
1112 |
{"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, MX }, |
|
1113 |
{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, |
|
1114 |
{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, I1 }, |
|
1115 |
{"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, |
|
1116 |
{"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, |
|
1117 |
{"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, N54 }, |
|
1118 |
{"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, |
|
1119 |
{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, |
|
1120 |
{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 }, |
|
1121 |
/* b is at the top of the table. */ |
|
1122 |
/* bal is at the top of the table. */ |
|
1123 |
{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, I1 }, |
|
1124 |
{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, I2|T3 }, |
|
1125 |
{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, I1 }, |
|
1126 |
{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, I2|T3 }, |
|
1127 |
{"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, M3D }, |
|
1128 |
{"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, M3D }, |
|
1129 |
{"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, M3D }, |
|
1130 |
{"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, M3D }, |
|
1131 |
{"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, I1 }, |
|
1132 |
{"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, I4|I32 }, |
|
1133 |
{"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 }, |
|
1134 |
{"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, I4|I32 }, |
|
1135 |
{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, I1 }, |
|
1136 |
{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4|I32 }, |
|
1137 |
{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 }, |
|
1138 |
{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4|I32 }, |
|
1139 |
/* bc2* are at the bottom of the table. */ |
|
1140 |
{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, I1 }, |
|
1141 |
{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, I2|T3 }, |
|
1142 |
{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, I1 }, |
|
1143 |
{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, I2|T3 }, |
|
1144 |
{"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, I1 }, |
|
1145 |
{"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, |
|
1146 |
{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, I1 }, |
|
1147 |
{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, I1 }, |
|
1148 |
{"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 }, |
|
1149 |
{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, I2|T3 }, |
|
1150 |
{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, I1 }, |
|
1151 |
{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, I1 }, |
|
1152 |
{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, I2|T3 }, |
|
1153 |
{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, I2|T3 }, |
|
1154 |
{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, I1 }, |
|
1155 |
{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, I1 }, |
|
1156 |
{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, I2|T3 }, |
|
1157 |
{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, I2|T3 }, |
|
1158 |
{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, I1 }, |
|
1159 |
{"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, I2|T3 }, |
|
1160 |
{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, I1 }, |
|
1161 |
{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, I2|T3 }, |
|
1162 |
{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, I1 }, |
|
1163 |
{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, I1 }, |
|
1164 |
{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, I2|T3 }, |
|
1165 |
{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, I2|T3 }, |
|
1166 |
{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, I1 }, |
|
1167 |
{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, I1 }, |
|
1168 |
{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, I2|T3 }, |
|
1169 |
{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, I2|T3 }, |
|
1170 |
{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, I1 }, |
|
1171 |
{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, |
|
1172 |
{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, I1 }, |
|
1173 |
{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, I1 }, |
|
1174 |
{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, I2|T3 }, |
|
1175 |
{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, I2|T3 }, |
|
1176 |
{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, I1 }, |
|
1177 |
{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, I1 }, |
|
1178 |
{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, I2|T3 }, |
|
1179 |
{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, I2|T3 }, |
|
1180 |
{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, I1 }, |
|
1181 |
{"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, |
|
1182 |
{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, I1 }, |
|
1183 |
{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, I1 }, |
|
1184 |
{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, I2|T3 }, |
|
1185 |
{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, I2|T3 }, |
|
1186 |
{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, I1 }, |
|
1187 |
{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, I1 }, |
|
1188 |
{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, I2|T3 }, |
|
1189 |
{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, I2|T3 }, |
|
1190 |
{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, I1 }, |
|
1191 |
{"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, I2|T3 }, |
|
1192 |
{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, I1 }, |
|
1193 |
{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, I2|T3 }, |
|
1194 |
{"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, I1 }, |
|
1195 |
{"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, |
|
1196 |
{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, I1 }, |
|
1197 |
{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, I1 }, |
|
1198 |
{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 }, |
|
1199 |
{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, I2|T3 }, |
|
1200 |
{"break", "", 0x0000000d, 0xffffffff, TRAP, I1 }, |
|
1201 |
{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 }, |
|
1202 |
{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, I1 }, |
|
1203 |
{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
|
1204 |
{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, |
|
1205 |
{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
|
1206 |
{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, |
|
1207 |
{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1208 |
{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1209 |
{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
|
1210 |
{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, |
|
1211 |
{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
|
1212 |
{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, |
|
1213 |
{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1214 |
{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1215 |
{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
|
1216 |
{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, |
|
1217 |
{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
|
1218 |
{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, |
|
1219 |
{"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX|SB1 }, |
|
1220 |
{"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, N54 }, |
|
1221 |
{"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 }, |
|
1222 |
{"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, N54 }, |
|
1223 |
{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1224 |
{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1225 |
{"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX }, |
|
1226 |
{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
|
1227 |
{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, |
|
1228 |
{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
|
1229 |
{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, |
|
1230 |
{"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1231 |
{"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1232 |
{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
|
1233 |
{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, |
|
1234 |
{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
|
1235 |
{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, |
|
1236 |
{"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1237 |
{"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1238 |
{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
|
1239 |
{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, |
|
1240 |
{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
|
1241 |
{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, |
|
1242 |
{"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1243 |
{"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1244 |
{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
|
1245 |
{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, |
|
1246 |
{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
|
1247 |
{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, |
|
1248 |
{"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1249 |
{"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1250 |
{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
|
1251 |
{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, |
|
1252 |
{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
|
1253 |
{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, |
|
1254 |
{"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1255 |
{"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1256 |
{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
|
1257 |
{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, |
|
1258 |
{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
|
1259 |
{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, |
|
1260 |
{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1261 |
{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1262 |
{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
|
1263 |
{"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, |
|
1264 |
{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
|
1265 |
{"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, |
|
1266 |
{"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1267 |
{"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1268 |
{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
|
1269 |
{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, |
|
1270 |
{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
|
1271 |
{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, |
|
1272 |
{"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1273 |
{"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1274 |
{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
|
1275 |
{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, |
|
1276 |
{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
|
1277 |
{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, |
|
1278 |
{"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1279 |
{"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1280 |
{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
|
1281 |
{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, |
|
1282 |
{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
|
1283 |
{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, |
|
1284 |
{"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX|SB1 }, |
|
1285 |
{"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, N54 }, |
|
1286 |
{"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 }, |
|
1287 |
{"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, N54 }, |
|
1288 |
{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1289 |
{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1290 |
{"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX }, |
|
1291 |
{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
|
1292 |
{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, |
|
1293 |
{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
|
1294 |
{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, |
|
1295 |
{"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1296 |
{"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1297 |
{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
|
1298 |
{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, |
|
1299 |
{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
|
1300 |
{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, |
|
1301 |
{"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX|SB1 }, |
|
1302 |
{"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, N54 }, |
|
1303 |
{"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 }, |
|
1304 |
{"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, N54 }, |
|
1305 |
{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1306 |
{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1307 |
{"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX }, |
|
1308 |
{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, |
|
1309 |
{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, |
|
1310 |
{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, |
|
1311 |
{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, |
|
1312 |
{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1313 |
{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, |
|
1314 |
{"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1315 |
{"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1316 |
{"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, |
|
1317 |
{"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1318 |
{"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1319 |
{"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, |
|
1320 |
{"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1321 |
{"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1322 |
{"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, |
|
1323 |
{"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1324 |
{"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1325 |
{"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, |
|
1326 |
{"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1327 |
{"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1328 |
{"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, |
|
1329 |
{"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1330 |
{"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1331 |
{"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, |
|
1332 |
{"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1333 |
{"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1334 |
{"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, |
|
1335 |
{"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1336 |
{"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1337 |
{"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, |
|
1338 |
{"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1339 |
{"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1340 |
{"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, |
|
1341 |
{"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1342 |
{"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1343 |
{"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, |
|
1344 |
{"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1345 |
{"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1346 |
{"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, |
|
1347 |
{"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1348 |
{"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1349 |
{"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, |
|
1350 |
{"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1351 |
{"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1352 |
{"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, |
|
1353 |
{"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1354 |
{"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1355 |
{"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, |
|
1356 |
{"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1357 |
{"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1358 |
{"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, |
|
1359 |
{"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1360 |
{"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, |
|
1361 |
{"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, |
|
1362 |
{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|I32|T3}, |
|
1363 |
{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 }, |
|
1364 |
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 }, |
|
1365 |
{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2 }, |
|
1366 |
{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, I2 }, |
|
1367 |
{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, I1 }, |
|
1368 |
{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 }, |
|
1369 |
{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 }, |
|
1370 |
/* cfc2 is at the bottom of the table. */ |
|
1371 |
{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 }, |
|
1372 |
{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, I32|N55 }, |
|
1373 |
{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, I32|N55 }, |
|
1374 |
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, |
|
1375 |
{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 }, |
|
1376 |
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 }, |
|
1377 |
/* ctc2 is at the bottom of the table. */ |
|
1378 |
{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, |
|
1379 |
{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, I3 }, |
|
1380 |
{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, I1 }, |
|
1381 |
{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_D, I1 }, |
|
1382 |
{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, I3 }, |
|
1383 |
{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S, I3 }, |
|
1384 |
{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S, I3 }, |
|
1385 |
{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I1 }, |
|
1386 |
{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, I1 }, |
|
1387 |
{"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I5 }, |
|
1388 |
{"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I5 }, |
|
1389 |
{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_D, I1 }, |
|
1390 |
{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, I1 }, |
|
1391 |
{"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, M3D }, |
|
1392 |
{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, |
|
1393 |
{"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, M3D }, |
|
1394 |
{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, I3 }, |
|
1395 |
{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, |
|
1396 |
{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, I3 }, |
|
1397 |
{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, I3 }, |
|
1398 |
{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, I3 }, |
|
1399 |
{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, |
|
1400 |
{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, I3 }, |
|
1401 |
{"dbreak", "", 0x7000003f, 0xffffffff, 0, N5 }, |
|
1402 |
{"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, I64|N55 }, |
|
1403 |
{"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, I64|N55 }, |
|
1404 |
/* dctr and dctw are used on the r5000. */ |
|
1405 |
{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 }, |
|
1406 |
{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 }, |
|
1407 |
{"deret", "", 0x4200001f, 0xffffffff, 0, I32|G2 }, |
|
1408 |
{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, I65 }, |
|
1409 |
{"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, I65 }, |
|
1410 |
{"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, I65 }, |
|
1411 |
{"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, I65 }, |
|
1412 |
/* For ddiv, see the comments about div. */ |
|
1413 |
{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 }, |
|
1414 |
{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, I3 }, |
|
1415 |
{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, I3 }, |
|
1416 |
/* For ddivu, see the comments about div. */ |
|
1417 |
{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 }, |
|
1418 |
{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, I3 }, |
|
1419 |
{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, I3 }, |
|
1420 |
{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, I33 }, |
|
1421 |
{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, I33 }, |
|
1422 |
{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, I65 }, |
|
1423 |
{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, I65 }, |
|
1424 |
{"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, I65 }, |
|
1425 |
{"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, I65 }, |
|
1426 |
/* The MIPS assembler treats the div opcode with two operands as |
|
1427 |
though the first operand appeared twice (the first operand is both |
|
1428 |
a source and a destination). To get the div machine instruction, |
|
1429 |
you must use an explicit destination of $0. */ |
|
1430 |
{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 }, |
|
1431 |
{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, I1 }, |
|
1432 |
{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, I1 }, |
|
1433 |
{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, I1 }, |
|
1434 |
{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, |
|
1435 |
{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, |
|
1436 |
{"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, SB1 }, |
|
1437 |
/* For divu, see the comments about div. */ |
|
1438 |
{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 }, |
|
1439 |
{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, I1 }, |
|
1440 |
{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, I1 }, |
|
1441 |
{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, I1 }, |
|
1442 |
{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, I3 }, |
|
1443 |
{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, I3 }, |
|
1444 |
{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, I3 }, /* addiu */ |
|
1445 |
{"dli", "t,i", 0x34000000, 0xffe00000, WR_t, I3 }, /* ori */ |
|
1446 |
{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, I3 }, |
|
1447 |
{"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 }, |
|
1448 |
{"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 }, |
|
1449 |
{"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 }, |
|
1450 |
{"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 }, |
|
1451 |
{"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 }, |
|
1452 |
{"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 }, |
|
1453 |
{"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 }, |
|
1454 |
{"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 }, |
|
1455 |
{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, N411 }, |
|
1456 |
{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 }, |
|
1457 |
{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, I64 }, |
|
1458 |
{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, I64 }, |
|
1459 |
{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I3 }, |
|
1460 |
{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I64 }, |
|
1461 |
{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I64 }, |
|
1462 |
{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 }, |
|
1463 |
{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 }, |
|
1464 |
{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 }, |
|
1465 |
{"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 }, |
|
1466 |
/* dmfc2 is at the bottom of the table. */ |
|
1467 |
/* dmtc2 is at the bottom of the table. */ |
|
1468 |
{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, I3 }, |
|
1469 |
{"dmfc3", "t,G,H", 0x4c200000, 0xffe007f8, LCD|WR_t|RD_C3, I64 }, |
|
1470 |
{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I3 }, |
|
1471 |
{"dmtc3", "t,G,H", 0x4ca00000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, I64 }, |
|
1472 |
{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, I3 }, |
|
1473 |
{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, I3 }, |
|
1474 |
{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, I3 }, |
|
1475 |
{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, I3 }, |
|
1476 |
{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, I3 }, |
|
1477 |
{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, I3 }, |
|
1478 |
{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 }, |
|
1479 |
{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 }, |
|
1480 |
{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, I3 }, /* dsub 0 */ |
|
1481 |
{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, I3 }, /* dsubu 0*/ |
|
1482 |
{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 }, |
|
1483 |
{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, I3 }, |
|
1484 |
{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, I3 }, |
|
1485 |
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 }, |
|
1486 |
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 }, |
Also available in: Unified diff