Revision 66450b15 hw/omap.c
| b/hw/omap.c | ||
|---|---|---|
| 22 | 22 |
#include "arm_pic.h" |
| 23 | 23 |
|
| 24 | 24 |
/* Should signal the TCMI */ |
| 25 |
uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr) |
|
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{
|
|
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OMAP_8B_REG(addr); |
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return 0; |
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} |
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| 30 |
|
|
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void omap_badwidth_write8(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
|
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{
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|
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OMAP_8B_REG(addr); |
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} |
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| 36 |
|
|
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uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr) |
| 26 | 38 |
{
|
| 27 | 39 |
OMAP_16B_REG(addr); |
| ... | ... | |
| 3140 | 3152 |
return; |
| 3141 | 3153 |
|
| 3142 | 3154 |
case 0x04: /* DATA_OUTPUT */ |
| 3143 |
diff = s->outputs ^ (value & ~s->dir);
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diff = (s->outputs ^ value) & ~s->dir;
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s->outputs = value; |
| 3145 |
value &= ~s->dir; |
|
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while ((ln = ffs(diff))) {
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ln --; |
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if (s->handler[ln]) |
| ... | ... | |
| 3369 | 3380 |
|
| 3370 | 3381 |
void omap_uwire_reset(struct omap_uwire_s *s) |
| 3371 | 3382 |
{
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s->control= 0; |
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s->control = 0;
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| 3373 | 3384 |
s->setup[0] = 0; |
| 3374 | 3385 |
s->setup[1] = 0; |
| 3375 | 3386 |
s->setup[2] = 0; |
| ... | ... | |
| 3407 | 3418 |
s->chip[chipselect] = slave; |
| 3408 | 3419 |
} |
| 3409 | 3420 |
|
| 3421 |
/* Pseudonoise Pulse-Width Light Modulator */ |
|
| 3422 |
void omap_pwl_update(struct omap_mpu_state_s *s) |
|
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{
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int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0; |
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|
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if (output != s->pwl.output) {
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s->pwl.output = output; |
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printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
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} |
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} |
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|
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static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr) |
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{
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struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
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int offset = addr - s->pwl.base; |
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switch (offset) {
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case 0x00: /* PWL_LEVEL */ |
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return s->pwl.level; |
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case 0x04: /* PWL_CTRL */ |
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return s->pwl.enable; |
|
| 3442 |
} |
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OMAP_BAD_REG(addr); |
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return 0; |
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} |
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| 3446 |
|
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static void omap_pwl_write(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{
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struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
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int offset = addr - s->pwl.base; |
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|
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switch (offset) {
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case 0x00: /* PWL_LEVEL */ |
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s->pwl.level = value; |
|
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omap_pwl_update(s); |
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break; |
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case 0x04: /* PWL_CTRL */ |
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s->pwl.enable = value & 1; |
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omap_pwl_update(s); |
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break; |
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default: |
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OMAP_BAD_REG(addr); |
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return; |
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} |
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} |
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|
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static CPUReadMemoryFunc *omap_pwl_readfn[] = {
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omap_badwidth_read8, |
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omap_badwidth_read8, |
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omap_pwl_read, |
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}; |
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|
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static CPUWriteMemoryFunc *omap_pwl_writefn[] = {
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omap_badwidth_write8, |
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omap_badwidth_write8, |
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omap_pwl_write, |
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| 3478 |
}; |
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| 3479 |
|
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void omap_pwl_reset(struct omap_mpu_state_s *s) |
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{
|
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s->pwl.output = 0; |
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s->pwl.level = 0; |
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s->pwl.enable = 0; |
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s->pwl.clk = 1; |
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omap_pwl_update(s); |
|
| 3487 |
} |
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|
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static void omap_pwl_clk_update(void *opaque, int line, int on) |
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{
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struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
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|
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s->pwl.clk = on; |
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omap_pwl_update(s); |
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} |
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|
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static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s, |
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omap_clk clk) |
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{
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int iomemtype; |
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|
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s->pwl.base = base; |
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omap_pwl_reset(s); |
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|
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iomemtype = cpu_register_io_memory(0, omap_pwl_readfn, |
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omap_pwl_writefn, s); |
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cpu_register_physical_memory(s->pwl.base, 0x800, iomemtype); |
|
| 3508 |
|
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omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]); |
|
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} |
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|
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/* General chip reset */ |
| 3411 | 3513 |
static void omap_mpu_reset(void *opaque) |
| 3412 | 3514 |
{
|
| ... | ... | |
| 3437 | 3539 |
omap_mpuio_reset(mpu->mpuio); |
| 3438 | 3540 |
omap_gpio_reset(mpu->gpio); |
| 3439 | 3541 |
omap_uwire_reset(mpu->microwire); |
| 3542 |
omap_pwl_reset(mpu); |
|
| 3440 | 3543 |
cpu_reset(mpu->env); |
| 3441 | 3544 |
} |
| 3442 | 3545 |
|
| ... | ... | |
| 3553 | 3656 |
s->wakeup, omap_findclk(s, "clk32-kHz")); |
| 3554 | 3657 |
|
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s->gpio = omap_gpio_init(0xfffce000, s->irq[0][OMAP_INT_GPIO_BANK1], |
| 3556 |
omap_findclk(s, "mpuper_ck"));
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| 3659 |
omap_findclk(s, "arm_gpio_ck"));
|
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| 3557 | 3660 |
|
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s->microwire = omap_uwire_init(0xfffb3000, &s->irq[1][OMAP_INT_uWireTX], |
| 3559 | 3662 |
s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck")); |
| 3560 | 3663 |
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omap_pwl_init(0xfffb5800, s, omap_findclk(s, "clk32-kHz")); |
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| 3665 |
|
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| 3561 | 3666 |
qemu_register_reset(omap_mpu_reset, s); |
| 3562 | 3667 |
|
| 3563 | 3668 |
return s; |
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