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/*
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 * i386 virtual CPU header
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 * 
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#ifndef CPU_I386_H
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#define CPU_I386_H
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#include "config.h"
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#ifdef TARGET_X86_64
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#define TARGET_LONG_BITS 64
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#else
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#define TARGET_LONG_BITS 32
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#endif
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/* target supports implicit self modifying code */
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#define TARGET_HAS_SMC
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/* support for self modifying code even if the modified instruction is
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   close to the modifying instruction */
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#define TARGET_HAS_PRECISE_SMC
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#include "cpu-defs.h"
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#if defined(__i386__) && !defined(CONFIG_SOFTMMU)
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#define USE_CODE_COPY
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#endif
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#define R_EAX 0
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#define R_ECX 1
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#define R_EDX 2
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#define R_EBX 3
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#define R_ESP 4
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#define R_EBP 5
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#define R_ESI 6
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#define R_EDI 7
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#define R_AL 0
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#define R_CL 1
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#define R_DL 2
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#define R_BL 3
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#define R_AH 4
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#define R_CH 5
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#define R_DH 6
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#define R_BH 7
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#define R_ES 0
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#define R_CS 1
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#define R_SS 2
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#define R_DS 3
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#define R_FS 4
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#define R_GS 5
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/* segment descriptor fields */
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#define DESC_G_MASK     (1 << 23)
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#define DESC_B_SHIFT    22
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#define DESC_B_MASK     (1 << DESC_B_SHIFT)
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#define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
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#define DESC_L_MASK     (1 << DESC_L_SHIFT)
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#define DESC_AVL_MASK   (1 << 20)
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#define DESC_P_MASK     (1 << 15)
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#define DESC_DPL_SHIFT  13
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#define DESC_S_MASK     (1 << 12)
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#define DESC_TYPE_SHIFT 8
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#define DESC_A_MASK     (1 << 8)
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#define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
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#define DESC_C_MASK     (1 << 10) /* code: conforming */
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#define DESC_R_MASK     (1 << 9)  /* code: readable */
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#define DESC_E_MASK     (1 << 10) /* data: expansion direction */
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#define DESC_W_MASK     (1 << 9)  /* data: writable */
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#define DESC_TSS_BUSY_MASK (1 << 9)
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/* eflags masks */
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#define CC_C           0x0001
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#define CC_P         0x0004
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#define CC_A        0x0010
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#define CC_Z        0x0040
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#define CC_S    0x0080
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#define CC_O    0x0800
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#define TF_SHIFT   8
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#define IOPL_SHIFT 12
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#define VM_SHIFT   17
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#define TF_MASK                 0x00000100
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#define IF_MASK                 0x00000200
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#define DF_MASK                 0x00000400
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#define IOPL_MASK                0x00003000
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#define NT_MASK                         0x00004000
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#define RF_MASK                        0x00010000
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#define VM_MASK                        0x00020000
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#define AC_MASK                        0x00040000 
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#define VIF_MASK                0x00080000
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#define VIP_MASK                0x00100000
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#define ID_MASK                 0x00200000
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114
/* hidden flags - used internally by qemu to represent additionnal cpu
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   states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
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   using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
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   with eflags. */
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/* current cpl */
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#define HF_CPL_SHIFT         0
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/* true if soft mmu is being used */
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#define HF_SOFTMMU_SHIFT     2
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/* true if hardware interrupts must be disabled for next instruction */
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#define HF_INHIBIT_IRQ_SHIFT 3
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/* 16 or 32 segments */
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#define HF_CS32_SHIFT        4
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#define HF_SS32_SHIFT        5
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/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
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#define HF_ADDSEG_SHIFT      6
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/* copy of CR0.PE (protected mode) */
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#define HF_PE_SHIFT          7
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#define HF_TF_SHIFT          8 /* must be same as eflags */
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#define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
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#define HF_EM_SHIFT         10
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#define HF_TS_SHIFT         11
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#define HF_IOPL_SHIFT       12 /* must be same as eflags */
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#define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
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#define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
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#define HF_OSFXSR_SHIFT     16 /* CR4.OSFXSR */
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#define HF_VM_SHIFT         17 /* must be same as eflags */
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#define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
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#define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
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#define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
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#define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
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#define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
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#define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
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#define HF_PE_MASK           (1 << HF_PE_SHIFT)
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#define HF_TF_MASK           (1 << HF_TF_SHIFT)
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#define HF_MP_MASK           (1 << HF_MP_SHIFT)
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#define HF_EM_MASK           (1 << HF_EM_SHIFT)
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#define HF_TS_MASK           (1 << HF_TS_SHIFT)
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#define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
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#define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
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#define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
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#define CR0_PE_MASK  (1 << 0)
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#define CR0_MP_MASK  (1 << 1)
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#define CR0_EM_MASK  (1 << 2)
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#define CR0_TS_MASK  (1 << 3)
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#define CR0_ET_MASK  (1 << 4)
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#define CR0_NE_MASK  (1 << 5)
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#define CR0_WP_MASK  (1 << 16)
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#define CR0_AM_MASK  (1 << 18)
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#define CR0_PG_MASK  (1 << 31)
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#define CR4_VME_MASK  (1 << 0)
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#define CR4_PVI_MASK  (1 << 1)
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#define CR4_TSD_MASK  (1 << 2)
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#define CR4_DE_MASK   (1 << 3)
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#define CR4_PSE_MASK  (1 << 4)
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#define CR4_PAE_MASK  (1 << 5)
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#define CR4_PGE_MASK  (1 << 7)
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#define CR4_PCE_MASK  (1 << 8)
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#define CR4_OSFXSR_MASK (1 << 9)
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#define CR4_OSXMMEXCPT_MASK  (1 << 10)
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#define PG_PRESENT_BIT        0
178
#define PG_RW_BIT        1
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#define PG_USER_BIT        2
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#define PG_PWT_BIT        3
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#define PG_PCD_BIT        4
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#define PG_ACCESSED_BIT        5
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#define PG_DIRTY_BIT        6
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#define PG_PSE_BIT        7
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#define PG_GLOBAL_BIT        8
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#define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
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#define PG_RW_MASK         (1 << PG_RW_BIT)
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#define PG_USER_MASK         (1 << PG_USER_BIT)
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#define PG_PWT_MASK         (1 << PG_PWT_BIT)
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#define PG_PCD_MASK         (1 << PG_PCD_BIT)
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#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
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#define PG_DIRTY_MASK         (1 << PG_DIRTY_BIT)
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#define PG_PSE_MASK         (1 << PG_PSE_BIT)
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#define PG_GLOBAL_MASK         (1 << PG_GLOBAL_BIT)
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#define PG_ERROR_W_BIT     1
198

    
199
#define PG_ERROR_P_MASK    0x01
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#define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
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#define PG_ERROR_U_MASK    0x04
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#define PG_ERROR_RSVD_MASK 0x08
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#define MSR_IA32_APICBASE               0x1b
205
#define MSR_IA32_APICBASE_BSP           (1<<8)
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#define MSR_IA32_APICBASE_ENABLE        (1<<11)
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#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
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#define MSR_IA32_SYSENTER_CS            0x174
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#define MSR_IA32_SYSENTER_ESP           0x175
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#define MSR_IA32_SYSENTER_EIP           0x176
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#define MSR_EFER                        0xc0000080
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#define MSR_EFER_SCE   (1 << 0)
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#define MSR_EFER_LME   (1 << 8)
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#define MSR_EFER_LMA   (1 << 10)
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#define MSR_EFER_NXE   (1 << 11)
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#define MSR_EFER_FFXSR (1 << 14)
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#define MSR_STAR                        0xc0000081
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#define MSR_LSTAR                       0xc0000082
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#define MSR_CSTAR                       0xc0000083
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#define MSR_FMASK                       0xc0000084
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#define MSR_FSBASE                      0xc0000100
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#define MSR_GSBASE                      0xc0000101
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#define MSR_KERNELGSBASE                0xc0000102
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/* cpuid_features bits */
230
#define CPUID_FP87 (1 << 0)
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#define CPUID_VME  (1 << 1)
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#define CPUID_DE   (1 << 2)
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#define CPUID_PSE  (1 << 3)
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#define CPUID_TSC  (1 << 4)
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#define CPUID_MSR  (1 << 5)
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#define CPUID_PAE  (1 << 6)
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#define CPUID_MCE  (1 << 7)
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#define CPUID_CX8  (1 << 8)
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#define CPUID_APIC (1 << 9)
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#define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
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#define CPUID_MTRR (1 << 12)
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#define CPUID_PGE  (1 << 13)
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#define CPUID_MCA  (1 << 14)
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#define CPUID_CMOV (1 << 15)
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/* ... */
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#define CPUID_MMX  (1 << 23)
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#define CPUID_FXSR (1 << 24)
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#define CPUID_SSE  (1 << 25)
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#define CPUID_SSE2 (1 << 26)
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#define EXCP00_DIVZ        0
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#define EXCP01_SSTP        1
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#define EXCP02_NMI        2
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#define EXCP03_INT3        3
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#define EXCP04_INTO        4
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#define EXCP05_BOUND        5
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#define EXCP06_ILLOP        6
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#define EXCP07_PREX        7
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#define EXCP08_DBLE        8
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#define EXCP09_XERR        9
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#define EXCP0A_TSS        10
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#define EXCP0B_NOSEG        11
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#define EXCP0C_STACK        12
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#define EXCP0D_GPF        13
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#define EXCP0E_PAGE        14
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#define EXCP10_COPR        16
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#define EXCP11_ALGN        17
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#define EXCP12_MCHK        18
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enum {
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    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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    CC_OP_EFLAGS,  /* all cc are explicitely computed, CC_SRC = flags */
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    CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
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    CC_OP_MULW,
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    CC_OP_MULL,
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    CC_OP_MULQ,
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    CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_ADDW,
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    CC_OP_ADDL,
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    CC_OP_ADDQ,
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    CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_ADCW,
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    CC_OP_ADCL,
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    CC_OP_ADCQ,
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    CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_SUBW,
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    CC_OP_SUBL,
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    CC_OP_SUBQ,
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    CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_SBBW,
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    CC_OP_SBBL,
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    CC_OP_SBBQ,
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    CC_OP_LOGICB, /* modify all flags, CC_DST = res */
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    CC_OP_LOGICW,
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    CC_OP_LOGICL,
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    CC_OP_LOGICQ,
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    CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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    CC_OP_INCW,
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    CC_OP_INCL,
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    CC_OP_INCQ,
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    CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
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    CC_OP_DECW,
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    CC_OP_DECL,
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    CC_OP_DECQ,
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    CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
315
    CC_OP_SHLW,
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    CC_OP_SHLL,
317
    CC_OP_SHLQ,
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    CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
320
    CC_OP_SARW,
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    CC_OP_SARL,
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    CC_OP_SARQ,
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324
    CC_OP_NB,
325
};
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#if (defined(__i386__) || defined(__x86_64__)) && !defined(_BSD)
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#define USE_X86LDOUBLE
329
#endif
330

    
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#ifdef USE_X86LDOUBLE
332
typedef long double CPU86_LDouble;
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#else
334
typedef double CPU86_LDouble;
335
#endif
336

    
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typedef struct SegmentCache {
338
    uint32_t selector;
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    target_ulong base;
340
    uint32_t limit;
341
    uint32_t flags;
342
} SegmentCache;
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typedef union {
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    uint8_t _b[16];
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    uint16_t _w[8];
347
    uint32_t _l[4];
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    uint64_t _q[2];
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    float _s[4];
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    double _d[2];
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} XMMReg;
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typedef union {
354
    uint8_t _b[8];
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    uint16_t _w[2];
356
    uint32_t _l[1];
357
    uint64_t q;
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} MMXReg;
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#ifdef WORDS_BIGENDIAN
361
#define XMM_B(n) _b[15 - (n)]
362
#define XMM_W(n) _w[7 - (n)]
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#define XMM_L(n) _l[3 - (n)]
364
#define XMM_S(n) _s[3 - (n)]
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#define XMM_Q(n) _q[1 - (n)]
366
#define XMM_D(n) _d[1 - (n)]
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368
#define MMX_B(n) _b[7 - (n)]
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#define MMX_W(n) _w[3 - (n)]
370
#define MMX_L(n) _l[1 - (n)]
371
#else
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#define XMM_B(n) _b[n]
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#define XMM_W(n) _w[n]
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#define XMM_L(n) _l[n]
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#define XMM_S(n) _s[n]
376
#define XMM_Q(n) _q[n]
377
#define XMM_D(n) _d[n]
378

    
379
#define MMX_B(n) _b[n]
380
#define MMX_W(n) _w[n]
381
#define MMX_L(n) _l[n]
382
#endif
383
#define MMX_Q(n) q
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385
#ifdef TARGET_X86_64
386
#define CPU_NB_REGS 16
387
#else
388
#define CPU_NB_REGS 8
389
#endif
390

    
391
typedef struct CPUX86State {
392
#if TARGET_LONG_BITS > HOST_LONG_BITS
393
    /* temporaries if we cannot store them in host registers */
394
    target_ulong t0, t1, t2;
395
#endif
396

    
397
    /* standard registers */
398
    target_ulong regs[CPU_NB_REGS];
399
    target_ulong eip;
400
    target_ulong eflags; /* eflags register. During CPU emulation, CC
401
                        flags and DF are set to zero because they are
402
                        stored elsewhere */
403

    
404
    /* emulator internal eflags handling */
405
    target_ulong cc_src;
406
    target_ulong cc_dst;
407
    uint32_t cc_op;
408
    int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
409
    uint32_t hflags; /* hidden flags, see HF_xxx constants */
410

    
411
    /* FPU state */
412
    unsigned int fpstt; /* top of stack index */
413
    unsigned int fpus;
414
    unsigned int fpuc;
415
    uint8_t fptags[8];   /* 0 = valid, 1 = empty */
416
    union {
417
#ifdef USE_X86LDOUBLE
418
        CPU86_LDouble d __attribute__((aligned(16)));
419
#else
420
        CPU86_LDouble d;
421
#endif
422
        MMXReg mmx;
423
    } fpregs[8];
424

    
425
    /* emulator internal variables */
426
    CPU86_LDouble ft0;
427
    union {
428
        float f;
429
        double d;
430
        int i32;
431
        int64_t i64;
432
    } fp_convert;
433
    
434
    /* segments */
435
    SegmentCache segs[6]; /* selector values */
436
    SegmentCache ldt;
437
    SegmentCache tr;
438
    SegmentCache gdt; /* only base and limit are used */
439
    SegmentCache idt; /* only base and limit are used */
440

    
441
    uint32_t mxcsr;
442
    XMMReg xmm_regs[CPU_NB_REGS];
443
    XMMReg xmm_t0;
444
    MMXReg mmx_t0;
445

    
446
    /* sysenter registers */
447
    uint32_t sysenter_cs;
448
    uint32_t sysenter_esp;
449
    uint32_t sysenter_eip;
450
#ifdef TARGET_X86_64
451
    target_ulong efer;
452
    target_ulong star;
453
    target_ulong lstar;
454
    target_ulong cstar;
455
    target_ulong fmask;
456
    target_ulong kernelgsbase;
457
#endif
458

    
459
    /* temporary data for USE_CODE_COPY mode */
460
#ifdef USE_CODE_COPY
461
    uint32_t tmp0;
462
    uint32_t saved_esp;
463
    int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
464
#endif
465
    
466
    /* exception/interrupt handling */
467
    jmp_buf jmp_env;
468
    int exception_index;
469
    int error_code;
470
    int exception_is_int;
471
    target_ulong exception_next_eip;
472
    struct TranslationBlock *current_tb; /* currently executing TB */
473
    target_ulong cr[5]; /* NOTE: cr1 is unused */
474
    target_ulong dr[8]; /* debug registers */
475
    int interrupt_request; 
476
    int user_mode_only; /* user mode only simulation */
477

    
478
    uint32_t a20_mask;
479

    
480
    /* soft mmu support */
481
    /* in order to avoid passing too many arguments to the memory
482
       write helpers, we store some rarely used information in the CPU
483
       context) */
484
    unsigned long mem_write_pc; /* host pc at which the memory was
485
                                   written */
486
    target_ulong mem_write_vaddr; /* target virtual addr at which the
487
                                     memory was written */
488
    /* 0 = kernel, 1 = user */
489
    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
490
    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
491
    
492
    /* from this point: preserved by CPU reset */
493
    /* ice debug support */
494
    target_ulong breakpoints[MAX_BREAKPOINTS];
495
    int nb_breakpoints;
496
    int singlestep_enabled;
497

    
498
    /* processor features (e.g. for CPUID insn) */
499
    uint32_t cpuid_vendor1;
500
    uint32_t cpuid_vendor2;
501
    uint32_t cpuid_vendor3;
502
    uint32_t cpuid_version;
503
    uint32_t cpuid_features;
504

    
505
    /* in order to simplify APIC support, we leave this pointer to the
506
       user */
507
    struct APICState *apic_state;
508
    /* user data */
509
    void *opaque;
510
} CPUX86State;
511

    
512
#ifndef IN_OP_I386
513
void cpu_x86_outb(CPUX86State *env, int addr, int val);
514
void cpu_x86_outw(CPUX86State *env, int addr, int val);
515
void cpu_x86_outl(CPUX86State *env, int addr, int val);
516
int cpu_x86_inb(CPUX86State *env, int addr);
517
int cpu_x86_inw(CPUX86State *env, int addr);
518
int cpu_x86_inl(CPUX86State *env, int addr);
519
#endif
520

    
521
CPUX86State *cpu_x86_init(void);
522
int cpu_x86_exec(CPUX86State *s);
523
void cpu_x86_close(CPUX86State *s);
524
int cpu_get_pic_interrupt(CPUX86State *s);
525
/* MSDOS compatibility mode FPU exception support */
526
void cpu_set_ferr(CPUX86State *s);
527

    
528
/* this function must always be used to load data in the segment
529
   cache: it synchronizes the hflags with the segment cache values */
530
static inline void cpu_x86_load_seg_cache(CPUX86State *env, 
531
                                          int seg_reg, unsigned int selector,
532
                                          uint32_t base, unsigned int limit, 
533
                                          unsigned int flags)
534
{
535
    SegmentCache *sc;
536
    unsigned int new_hflags;
537
    
538
    sc = &env->segs[seg_reg];
539
    sc->selector = selector;
540
    sc->base = base;
541
    sc->limit = limit;
542
    sc->flags = flags;
543

    
544
    /* update the hidden flags */
545
    {
546
        if (seg_reg == R_CS) {
547
#ifdef TARGET_X86_64
548
            if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
549
                /* long mode */
550
                env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
551
                env->hflags &= ~(HF_ADDSEG_MASK);
552
            } else 
553
#endif
554
            {
555
                /* legacy / compatibility case */
556
                new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
557
                    >> (DESC_B_SHIFT - HF_CS32_SHIFT);
558
                env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
559
                    new_hflags;
560
            }
561
        }
562
        new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
563
            >> (DESC_B_SHIFT - HF_SS32_SHIFT);
564
        if (env->hflags & HF_CS64_MASK) {
565
            /* zero base assumed for DS, ES and SS in long mode */
566
        } else if (!(env->cr[0] & CR0_PE_MASK) || 
567
            (env->eflags & VM_MASK) ||
568
            !(new_hflags & HF_CS32_MASK)) {
569
            /* XXX: try to avoid this test. The problem comes from the
570
               fact that is real mode or vm86 mode we only modify the
571
               'base' and 'selector' fields of the segment cache to go
572
               faster. A solution may be to force addseg to one in
573
               translate-i386.c. */
574
            new_hflags |= HF_ADDSEG_MASK;
575
        } else {
576
            new_hflags |= (((unsigned long)env->segs[R_DS].base | 
577
                            (unsigned long)env->segs[R_ES].base |
578
                            (unsigned long)env->segs[R_SS].base) != 0) << 
579
                HF_ADDSEG_SHIFT;
580
        }
581
        env->hflags = (env->hflags & 
582
                       ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
583
    }
584
}
585

    
586
/* wrapper, just in case memory mappings must be changed */
587
static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
588
{
589
#if HF_CPL_MASK == 3
590
    s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
591
#else
592
#error HF_CPL_MASK is hardcoded
593
#endif
594
}
595

    
596
/* used for debug or cpu save/restore */
597
void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
598
CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
599

    
600
/* the following helpers are only usable in user mode simulation as
601
   they can trigger unexpected exceptions */
602
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
603
void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
604
void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
605

    
606
/* you can call this signal handler from your SIGBUS and SIGSEGV
607
   signal handlers to inform the virtual CPU of exceptions. non zero
608
   is returned if the signal was handled by the virtual CPU.  */
609
struct siginfo;
610
int cpu_x86_signal_handler(int host_signum, struct siginfo *info, 
611
                           void *puc);
612
void cpu_x86_set_a20(CPUX86State *env, int a20_state);
613

    
614
uint64_t cpu_get_tsc(CPUX86State *env);
615

    
616
void cpu_set_apic_base(CPUX86State *env, uint64_t val);
617
uint64_t cpu_get_apic_base(CPUX86State *env);
618

    
619
/* will be suppressed */
620
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
621

    
622
/* used to debug */
623
#define X86_DUMP_FPU  0x0001 /* dump FPU state too */
624
#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
625

    
626
#define TARGET_PAGE_BITS 12
627
#include "cpu-all.h"
628

    
629
#endif /* CPU_I386_H */