Revision 68238a9e

b/hw/mips.h
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/* rc4030.c */
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typedef struct rc4030DMAState *rc4030_dma;
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typedef void (*rc4030_dma_function)(void *dma, uint8_t *buf, int len);
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qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
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                      rc4030_dma **dmas,
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                      rc4030_dma_function *dma_read, rc4030_dma_function *dma_write);
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void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
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void rc4030_dma_read(void *dma, uint8_t *buf, int len);
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void rc4030_dma_write(void *dma, uint8_t *buf, int len);
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void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
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                  qemu_irq **irqs, rc4030_dma **dmas);
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36 38
#endif
b/hw/mips_jazz.c
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    CPUState *env;
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    qemu_irq *rc4030, *i8259;
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    rc4030_dma *dmas;
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    rc4030_dma_function dma_read, dma_write;
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    void* rc4030_opaque;
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    void *scsi_hba;
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    int hd;
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    int s_rtc, s_dma_dummy;
......
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    cpu_mips_clock_init(env);
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    /* Chipset */
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    rc4030 = rc4030_init(env->irq[6], env->irq[3],
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                         &dmas, &dma_read, &dma_write);
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    rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
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    s_dma_dummy = cpu_register_io_memory(0, dma_dummy_read, dma_dummy_write, NULL);
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    cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
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......
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    /* SCSI adapter */
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    scsi_hba = esp_init(0x80002000, 0,
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                        dma_read, dma_write, dmas[0],
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                        rc4030_dma_read, rc4030_dma_write, dmas[0],
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                        rc4030[5], &esp_reset);
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    for (n = 0; n < ESP_MAX_DEVS; n++) {
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        hd = drive_get_index(IF_SCSI, 0, n);
b/hw/rc4030.c
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    qemu_put_be32(f, s->itr);
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}
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static void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write)
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void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write)
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{
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    rc4030State *s = opaque;
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    target_phys_addr_t entry_addr;
......
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    int n;
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};
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static void rc4030_dma_read(void *dma, uint8_t *buf, int len)
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void rc4030_dma_read(void *dma, uint8_t *buf, int len)
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{
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    rc4030_dma s = dma;
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    rc4030_do_dma(s->opaque, s->n, buf, len, 0);
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}
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static void rc4030_dma_write(void *dma, uint8_t *buf, int len)
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void rc4030_dma_write(void *dma, uint8_t *buf, int len)
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{
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    rc4030_dma s = dma;
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    rc4030_do_dma(s->opaque, s->n, buf, len, 1);
......
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    return s;
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}
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qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
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                      rc4030_dma **dmas,
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                      rc4030_dma_function *dma_read, rc4030_dma_function *dma_write)
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void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
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                  qemu_irq **irqs, rc4030_dma **dmas)
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{
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    rc4030State *s;
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    int s_chipset, s_jazzio;
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    s = qemu_mallocz(sizeof(rc4030State));
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    *irqs = qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);
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    *dmas = rc4030_allocate_dmas(s, 4);
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    *dma_read = rc4030_dma_read;
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    *dma_write = rc4030_dma_write;
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    s->periodic_timer = qemu_new_timer(vm_clock, rc4030_periodic_timer, s);
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    s->timer_irq = timer;
......
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    s_jazzio = cpu_register_io_memory(0, jazzio_read, jazzio_write, s);
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    cpu_register_physical_memory(0xf0000000, 0x00001000, s_jazzio);
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    return qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);
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    return s;
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}

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