root / hw / smc91c111.c @ 687fa640
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| 1 |
/*
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* SMSC 91C111 Ethernet interface emulation
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*
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* Copyright (c) 2005 CodeSourcery, LLC.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL
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*/
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#include "vl.h" |
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/* For crc32 */
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#include <zlib.h> |
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|
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/* Number of 2k memory pages available. */
|
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#define NUM_PACKETS 4 |
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|
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typedef struct { |
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uint32_t base; |
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VLANClientState *vc; |
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uint16_t tcr; |
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uint16_t rcr; |
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uint16_t cr; |
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uint16_t ctr; |
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uint16_t gpr; |
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uint16_t ptr; |
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uint16_t ercv; |
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void *pic;
|
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int irq;
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int bank;
|
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int packet_num;
|
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int tx_alloc;
|
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/* Bitmask of allocated packets. */
|
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int allocated;
|
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int tx_fifo_len;
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int tx_fifo[NUM_PACKETS];
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int rx_fifo_len;
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int rx_fifo[NUM_PACKETS];
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int tx_fifo_done_len;
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int tx_fifo_done[NUM_PACKETS];
|
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/* Packet buffer memory. */
|
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uint8_t data[NUM_PACKETS][2048];
|
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uint8_t int_level; |
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uint8_t int_mask; |
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uint8_t macaddr[6];
|
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} smc91c111_state; |
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|
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#define RCR_SOFT_RST 0x8000 |
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#define RCR_STRIP_CRC 0x0200 |
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#define RCR_RXEN 0x0100 |
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|
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#define TCR_EPH_LOOP 0x2000 |
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#define TCR_NOCRC 0x0100 |
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#define TCR_PAD_EN 0x0080 |
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#define TCR_FORCOL 0x0004 |
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#define TCR_LOOP 0x0002 |
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#define TCR_TXEN 0x0001 |
| 57 |
|
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#define INT_MD 0x80 |
| 59 |
#define INT_ERCV 0x40 |
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#define INT_EPH 0x20 |
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#define INT_RX_OVRN 0x10 |
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#define INT_ALLOC 0x08 |
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#define INT_TX_EMPTY 0x04 |
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#define INT_TX 0x02 |
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#define INT_RCV 0x01 |
| 66 |
|
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#define CTR_AUTO_RELEASE 0x0800 |
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#define CTR_RELOAD 0x0002 |
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#define CTR_STORE 0x0001 |
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|
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#define RS_ALGNERR 0x8000 |
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#define RS_BRODCAST 0x4000 |
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#define RS_BADCRC 0x2000 |
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#define RS_ODDFRAME 0x1000 |
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#define RS_TOOLONG 0x0800 |
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#define RS_TOOSHORT 0x0400 |
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#define RS_MULTICAST 0x0001 |
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|
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/* Update interrupt status. */
|
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static void smc91c111_update(smc91c111_state *s) |
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{
|
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int level;
|
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|
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if (s->tx_fifo_len == 0) |
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s->int_level |= INT_TX_EMPTY; |
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if (s->tx_fifo_done_len != 0) |
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s->int_level |= INT_TX; |
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level = (s->int_level & s->int_mask) != 0;
|
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pic_set_irq_new(s->pic, s->irq, level); |
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} |
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|
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/* Try to allocate a packet. Returns 0x80 on failure. */
|
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static int smc91c111_allocate_packet(smc91c111_state *s) |
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{
|
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int i;
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if (s->allocated == (1 << NUM_PACKETS) - 1) { |
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return 0x80; |
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} |
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|
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for (i = 0; i < NUM_PACKETS; i++) { |
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if ((s->allocated & (1 << i)) == 0) |
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break;
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} |
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s->allocated |= 1 << i;
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return i;
|
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} |
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|
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|
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/* Process a pending TX allocate. */
|
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static void smc91c111_tx_alloc(smc91c111_state *s) |
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{
|
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s->tx_alloc = smc91c111_allocate_packet(s); |
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if (s->tx_alloc == 0x80) |
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return;
|
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s->int_level |= INT_ALLOC; |
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smc91c111_update(s); |
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} |
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|
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/* Remove and item from the RX FIFO. */
|
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static void smc91c111_pop_rx_fifo(smc91c111_state *s) |
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{
|
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int i;
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|
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s->rx_fifo_len--; |
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if (s->rx_fifo_len) {
|
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for (i = 0; i < s->rx_fifo_len; i++) |
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s->rx_fifo[i] = s->rx_fifo[i + 1];
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s->int_level |= INT_RCV; |
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} else {
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s->int_level &= ~INT_RCV; |
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} |
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smc91c111_update(s); |
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} |
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|
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/* Remove an item from the TX completion FIFO. */
|
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static void smc91c111_pop_tx_fifo_done(smc91c111_state *s) |
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{
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int i;
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|
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if (s->tx_fifo_done_len == 0) |
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return;
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s->tx_fifo_done_len--; |
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for (i = 0; i < s->tx_fifo_done_len; i++) |
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s->tx_fifo_done[i] = s->tx_fifo_done[i + 1];
|
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} |
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|
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/* Release the memory allocated to a packet. */
|
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static void smc91c111_release_packet(smc91c111_state *s, int packet) |
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{
|
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s->allocated &= ~(1 << packet);
|
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if (s->tx_alloc == 0x80) |
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smc91c111_tx_alloc(s); |
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} |
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|
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/* Flush the TX FIFO. */
|
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static void smc91c111_do_tx(smc91c111_state *s) |
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{
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int i;
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int len;
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int control;
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int add_crc;
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int packetnum;
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uint8_t *p; |
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|
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if ((s->tcr & TCR_TXEN) == 0) |
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return;
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if (s->tx_fifo_len == 0) |
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return;
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for (i = 0; i < s->tx_fifo_len; i++) { |
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packetnum = s->tx_fifo[i]; |
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p = &s->data[packetnum][0];
|
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/* Set status word. */
|
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*(p++) = 0x01;
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*(p++) = 0x40;
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len = *(p++); |
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len |= ((int)*(p++)) << 8; |
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len -= 6;
|
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control = p[len + 1];
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if (control & 0x20) |
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len++; |
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/* ??? This overwrites the data following the buffer.
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Don't know what real hardware does. */
|
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if (len < 64 && (s->tcr & TCR_PAD_EN)) { |
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memset(p + len, 0, 64 - len); |
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len = 64;
|
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} |
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#if 0
|
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/* The card is supposed to append the CRC to the frame. However
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none of the other network traffic has the CRC appended.
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Suspect this is low level ethernet detail we don't need to worry
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about. */
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add_crc = (control & 0x10) || (s->tcr & TCR_NOCRC) == 0;
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if (add_crc) {
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uint32_t crc;
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crc = crc32(~0, p, len);
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memcpy(p + len, &crc, 4);
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len += 4;
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}
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#else
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add_crc = 0;
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#endif
|
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if (s->ctr & CTR_AUTO_RELEASE)
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/* Race? */
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smc91c111_release_packet(s, packetnum); |
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else if (s->tx_fifo_done_len < NUM_PACKETS) |
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s->tx_fifo_done[s->tx_fifo_done_len++] = packetnum; |
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qemu_send_packet(s->vc, p, len); |
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} |
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s->tx_fifo_len = 0;
|
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smc91c111_update(s); |
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} |
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|
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/* Add a packet to the TX FIFO. */
|
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static void smc91c111_queue_tx(smc91c111_state *s, int packet) |
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{
|
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if (s->tx_fifo_len == NUM_PACKETS)
|
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return;
|
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s->tx_fifo[s->tx_fifo_len++] = packet; |
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smc91c111_do_tx(s); |
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} |
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|
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static void smc91c111_reset(smc91c111_state *s) |
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{
|
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s->bank = 0;
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s->tx_fifo_len = 0;
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s->tx_fifo_done_len = 0;
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s->rx_fifo_len = 0;
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s->allocated = 0;
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s->packet_num = 0;
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s->tx_alloc = 0;
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s->tcr = 0;
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s->rcr = 0;
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s->cr = 0xa0b1;
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s->ctr = 0x1210;
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s->ptr = 0;
|
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s->ercv = 0x1f;
|
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s->int_level = INT_TX_EMPTY; |
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s->int_mask = 0;
|
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smc91c111_update(s); |
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} |
| 242 |
|
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#define SET_LOW(name, val) s->name = (s->name & 0xff00) | val |
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#define SET_HIGH(name, val) s->name = (s->name & 0xff) | (val << 8) |
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|
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static void smc91c111_writeb(void *opaque, target_phys_addr_t offset, |
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uint32_t value) |
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{
|
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smc91c111_state *s = (smc91c111_state *)opaque; |
| 250 |
|
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offset -= s->base; |
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if (offset == 14) { |
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s->bank = value; |
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return;
|
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} |
| 256 |
if (offset == 15) |
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return;
|
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switch (s->bank) {
|
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case 0: |
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switch (offset) {
|
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case 0: /* TCR */ |
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SET_LOW(tcr, value); |
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return;
|
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case 1: |
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SET_HIGH(tcr, value); |
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return;
|
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case 4: /* RCR */ |
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SET_LOW(rcr, value); |
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return;
|
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case 5: |
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SET_HIGH(rcr, value); |
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if (s->rcr & RCR_SOFT_RST)
|
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smc91c111_reset(s); |
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return;
|
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case 10: case 11: /* RPCR */ |
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/* Ignored */
|
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return;
|
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} |
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break;
|
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|
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case 1: |
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switch (offset) {
|
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case 0: /* CONFIG */ |
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SET_LOW(cr, value); |
| 285 |
return;
|
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case 1: |
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SET_HIGH(cr,value); |
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return;
|
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case 2: case 3: /* BASE */ |
| 290 |
case 4: case 5: case 6: case 7: case 8: case 9: /* IA */ |
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/* Not implemented. */
|
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return;
|
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case 10: /* Genral Purpose */ |
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SET_LOW(gpr, value); |
| 295 |
return;
|
| 296 |
case 11: |
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SET_HIGH(gpr, value); |
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return;
|
| 299 |
case 12: /* Control */ |
| 300 |
if (value & 1) |
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fprintf(stderr, "smc91c111:EEPROM store not implemented\n");
|
| 302 |
if (value & 2) |
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fprintf(stderr, "smc91c111:EEPROM reload not implemented\n");
|
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value &= ~3;
|
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SET_LOW(ctr, value); |
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return;
|
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case 13: |
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SET_HIGH(ctr, value); |
| 309 |
return;
|
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} |
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break;
|
| 312 |
|
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case 2: |
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switch (offset) {
|
| 315 |
case 0: /* MMU Command */ |
| 316 |
switch (value >> 5) { |
| 317 |
case 0: /* no-op */ |
| 318 |
break;
|
| 319 |
case 1: /* Allocate for TX. */ |
| 320 |
s->tx_alloc = 0x80;
|
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s->int_level &= ~INT_ALLOC; |
| 322 |
smc91c111_update(s); |
| 323 |
smc91c111_tx_alloc(s); |
| 324 |
break;
|
| 325 |
case 2: /* Reset MMU. */ |
| 326 |
s->allocated = 0;
|
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s->tx_fifo_len = 0;
|
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s->tx_fifo_done_len = 0;
|
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s->rx_fifo_len = 0;
|
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s->tx_alloc = 0;
|
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break;
|
| 332 |
case 3: /* Remove from RX FIFO. */ |
| 333 |
smc91c111_pop_rx_fifo(s); |
| 334 |
break;
|
| 335 |
case 4: /* Remove from RX FIFO and release. */ |
| 336 |
if (s->rx_fifo_len > 0) { |
| 337 |
smc91c111_release_packet(s, s->rx_fifo[0]);
|
| 338 |
} |
| 339 |
smc91c111_pop_rx_fifo(s); |
| 340 |
break;
|
| 341 |
case 5: /* Release. */ |
| 342 |
smc91c111_release_packet(s, s->packet_num); |
| 343 |
break;
|
| 344 |
case 6: /* Add to TX FIFO. */ |
| 345 |
smc91c111_queue_tx(s, s->packet_num); |
| 346 |
break;
|
| 347 |
case 7: /* Reset TX FIFO. */ |
| 348 |
s->tx_fifo_len = 0;
|
| 349 |
s->tx_fifo_done_len = 0;
|
| 350 |
break;
|
| 351 |
} |
| 352 |
return;
|
| 353 |
case 1: |
| 354 |
/* Ignore. */
|
| 355 |
return;
|
| 356 |
case 2: /* Packet Number Register */ |
| 357 |
s->packet_num = value; |
| 358 |
return;
|
| 359 |
case 3: case 4: case 5: |
| 360 |
/* Should be readonly, but linux writes to them anyway. Ignore. */
|
| 361 |
return;
|
| 362 |
case 6: /* Pointer */ |
| 363 |
SET_LOW(ptr, value); |
| 364 |
return;
|
| 365 |
case 7: |
| 366 |
SET_HIGH(ptr, value); |
| 367 |
return;
|
| 368 |
case 8: case 9: case 10: case 11: /* Data */ |
| 369 |
{
|
| 370 |
int p;
|
| 371 |
int n;
|
| 372 |
|
| 373 |
if (s->ptr & 0x8000) |
| 374 |
n = s->rx_fifo[0];
|
| 375 |
else
|
| 376 |
n = s->packet_num; |
| 377 |
p = s->ptr & 0x07ff;
|
| 378 |
if (s->ptr & 0x4000) { |
| 379 |
s->ptr = (s->ptr & 0xf800) | ((s->ptr + 1) & 0x7ff); |
| 380 |
} else {
|
| 381 |
p += (offset & 3);
|
| 382 |
} |
| 383 |
s->data[n][p] = value; |
| 384 |
} |
| 385 |
return;
|
| 386 |
case 12: /* Interrupt ACK. */ |
| 387 |
s->int_level &= ~(value & 0xd6);
|
| 388 |
if (value & INT_TX)
|
| 389 |
smc91c111_pop_tx_fifo_done(s); |
| 390 |
smc91c111_update(s); |
| 391 |
return;
|
| 392 |
case 13: /* Interrupt mask. */ |
| 393 |
s->int_mask = value; |
| 394 |
smc91c111_update(s); |
| 395 |
return;
|
| 396 |
} |
| 397 |
break;;
|
| 398 |
|
| 399 |
case 3: |
| 400 |
switch (offset) {
|
| 401 |
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: |
| 402 |
/* Multicast table. */
|
| 403 |
/* Not implemented. */
|
| 404 |
return;
|
| 405 |
case 8: case 9: /* Management Interface. */ |
| 406 |
/* Not implemented. */
|
| 407 |
return;
|
| 408 |
case 12: /* Early receive. */ |
| 409 |
s->ercv = value & 0x1f;
|
| 410 |
case 13: |
| 411 |
/* Ignore. */
|
| 412 |
return;
|
| 413 |
} |
| 414 |
break;
|
| 415 |
} |
| 416 |
cpu_abort (cpu_single_env, "smc91c111_write: Bad reg %d:%x\n",
|
| 417 |
s->bank, offset); |
| 418 |
} |
| 419 |
|
| 420 |
static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset) |
| 421 |
{
|
| 422 |
smc91c111_state *s = (smc91c111_state *)opaque; |
| 423 |
|
| 424 |
offset -= s->base; |
| 425 |
if (offset == 14) { |
| 426 |
return s->bank;
|
| 427 |
} |
| 428 |
if (offset == 15) |
| 429 |
return 0x33; |
| 430 |
switch (s->bank) {
|
| 431 |
case 0: |
| 432 |
switch (offset) {
|
| 433 |
case 0: /* TCR */ |
| 434 |
return s->tcr & 0xff; |
| 435 |
case 1: |
| 436 |
return s->tcr >> 8; |
| 437 |
case 2: /* EPH Status */ |
| 438 |
return 0; |
| 439 |
case 3: |
| 440 |
return 0x40; |
| 441 |
case 4: /* RCR */ |
| 442 |
return s->rcr & 0xff; |
| 443 |
case 5: |
| 444 |
return s->rcr >> 8; |
| 445 |
case 6: /* Counter */ |
| 446 |
case 7: |
| 447 |
/* Not implemented. */
|
| 448 |
return 0; |
| 449 |
case 8: /* Memory size. */ |
| 450 |
return NUM_PACKETS;
|
| 451 |
case 9: /* Free memory available. */ |
| 452 |
{
|
| 453 |
int i;
|
| 454 |
int n;
|
| 455 |
n = 0;
|
| 456 |
for (i = 0; i < NUM_PACKETS; i++) { |
| 457 |
if (s->allocated & (1 << i)) |
| 458 |
n++; |
| 459 |
} |
| 460 |
return n;
|
| 461 |
} |
| 462 |
case 10: case 11: /* RPCR */ |
| 463 |
/* Not implemented. */
|
| 464 |
return 0; |
| 465 |
} |
| 466 |
break;
|
| 467 |
|
| 468 |
case 1: |
| 469 |
switch (offset) {
|
| 470 |
case 0: /* CONFIG */ |
| 471 |
return s->cr & 0xff; |
| 472 |
case 1: |
| 473 |
return s->cr >> 8; |
| 474 |
case 2: case 3: /* BASE */ |
| 475 |
/* Not implemented. */
|
| 476 |
return 0; |
| 477 |
case 4: case 5: case 6: case 7: case 8: case 9: /* IA */ |
| 478 |
return s->macaddr[offset - 4]; |
| 479 |
case 10: /* General Purpose */ |
| 480 |
return s->gpr & 0xff; |
| 481 |
case 11: |
| 482 |
return s->gpr >> 8; |
| 483 |
case 12: /* Control */ |
| 484 |
return s->ctr & 0xff; |
| 485 |
case 13: |
| 486 |
return s->ctr >> 8; |
| 487 |
} |
| 488 |
break;
|
| 489 |
|
| 490 |
case 2: |
| 491 |
switch (offset) {
|
| 492 |
case 0: case 1: /* MMUCR Busy bit. */ |
| 493 |
return 0; |
| 494 |
case 2: /* Packet Number. */ |
| 495 |
return s->packet_num;
|
| 496 |
case 3: /* Allocation Result. */ |
| 497 |
return s->tx_alloc;
|
| 498 |
case 4: /* TX FIFO */ |
| 499 |
if (s->tx_fifo_done_len == 0) |
| 500 |
return 0x80; |
| 501 |
else
|
| 502 |
return s->tx_fifo_done[0]; |
| 503 |
case 5: /* RX FIFO */ |
| 504 |
if (s->rx_fifo_len == 0) |
| 505 |
return 0x80; |
| 506 |
else
|
| 507 |
return s->rx_fifo[0]; |
| 508 |
case 6: /* Pointer */ |
| 509 |
return s->ptr & 0xff; |
| 510 |
case 7: |
| 511 |
return (s->ptr >> 8) & 0xf7; |
| 512 |
case 8: case 9: case 10: case 11: /* Data */ |
| 513 |
{
|
| 514 |
int p;
|
| 515 |
int n;
|
| 516 |
|
| 517 |
if (s->ptr & 0x8000) |
| 518 |
n = s->rx_fifo[0];
|
| 519 |
else
|
| 520 |
n = s->packet_num; |
| 521 |
p = s->ptr & 0x07ff;
|
| 522 |
if (s->ptr & 0x4000) { |
| 523 |
s->ptr = (s->ptr & 0xf800) | ((s->ptr + 1) & 0x07ff); |
| 524 |
} else {
|
| 525 |
p += (offset & 3);
|
| 526 |
} |
| 527 |
return s->data[n][p];
|
| 528 |
} |
| 529 |
case 12: /* Interrupt status. */ |
| 530 |
return s->int_level;
|
| 531 |
case 13: /* Interrupt mask. */ |
| 532 |
return s->int_mask;
|
| 533 |
} |
| 534 |
break;
|
| 535 |
|
| 536 |
case 3: |
| 537 |
switch (offset) {
|
| 538 |
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: |
| 539 |
/* Multicast table. */
|
| 540 |
/* Not implemented. */
|
| 541 |
return 0; |
| 542 |
case 8: /* Management Interface. */ |
| 543 |
/* Not implemented. */
|
| 544 |
return 0x30; |
| 545 |
case 9: |
| 546 |
return 0x33; |
| 547 |
case 10: /* Revision. */ |
| 548 |
return 0x91; |
| 549 |
case 11: |
| 550 |
return 0x33; |
| 551 |
case 12: |
| 552 |
return s->ercv;
|
| 553 |
case 13: |
| 554 |
return 0; |
| 555 |
} |
| 556 |
break;
|
| 557 |
} |
| 558 |
cpu_abort (cpu_single_env, "smc91c111_read: Bad reg %d:%x\n",
|
| 559 |
s->bank, offset); |
| 560 |
return 0; |
| 561 |
} |
| 562 |
|
| 563 |
static void smc91c111_writew(void *opaque, target_phys_addr_t offset, |
| 564 |
uint32_t value) |
| 565 |
{
|
| 566 |
smc91c111_writeb(opaque, offset, value & 0xff);
|
| 567 |
smc91c111_writeb(opaque, offset + 1, value >> 8); |
| 568 |
} |
| 569 |
|
| 570 |
static void smc91c111_writel(void *opaque, target_phys_addr_t offset, |
| 571 |
uint32_t value) |
| 572 |
{
|
| 573 |
smc91c111_state *s = (smc91c111_state *)opaque; |
| 574 |
/* 32-bit writes to offset 0xc only actually write to the bank select
|
| 575 |
register (offset 0xe) */
|
| 576 |
if (offset != s->base + 0xc) |
| 577 |
smc91c111_writew(opaque, offset, value & 0xffff);
|
| 578 |
smc91c111_writew(opaque, offset + 2, value >> 16); |
| 579 |
} |
| 580 |
|
| 581 |
static uint32_t smc91c111_readw(void *opaque, target_phys_addr_t offset) |
| 582 |
{
|
| 583 |
uint32_t val; |
| 584 |
val = smc91c111_readb(opaque, offset); |
| 585 |
val |= smc91c111_readb(opaque, offset + 1) << 8; |
| 586 |
return val;
|
| 587 |
} |
| 588 |
|
| 589 |
static uint32_t smc91c111_readl(void *opaque, target_phys_addr_t offset) |
| 590 |
{
|
| 591 |
uint32_t val; |
| 592 |
val = smc91c111_readw(opaque, offset); |
| 593 |
val |= smc91c111_readw(opaque, offset + 2) << 16; |
| 594 |
return val;
|
| 595 |
} |
| 596 |
|
| 597 |
static int smc91c111_can_receive(void *opaque) |
| 598 |
{
|
| 599 |
smc91c111_state *s = (smc91c111_state *)opaque; |
| 600 |
|
| 601 |
if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST)) |
| 602 |
return 1; |
| 603 |
if (s->allocated == (1 << NUM_PACKETS) - 1) |
| 604 |
return 0; |
| 605 |
return 1; |
| 606 |
} |
| 607 |
|
| 608 |
static void smc91c111_receive(void *opaque, const uint8_t *buf, int size) |
| 609 |
{
|
| 610 |
smc91c111_state *s = (smc91c111_state *)opaque; |
| 611 |
int status;
|
| 612 |
int packetsize;
|
| 613 |
uint32_t crc; |
| 614 |
int packetnum;
|
| 615 |
uint8_t *p; |
| 616 |
|
| 617 |
if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST)) |
| 618 |
return;
|
| 619 |
/* Short packets are padded with zeros. Receiving a packet
|
| 620 |
< 64 bytes long is considered an error condition. */
|
| 621 |
if (size < 64) |
| 622 |
packetsize = 64;
|
| 623 |
else
|
| 624 |
packetsize = (size & ~1);
|
| 625 |
packetsize += 6;
|
| 626 |
crc = (s->rcr & RCR_STRIP_CRC) == 0;
|
| 627 |
if (crc)
|
| 628 |
packetsize += 4;
|
| 629 |
/* TODO: Flag overrun and receive errors. */
|
| 630 |
if (packetsize > 2048) |
| 631 |
return;
|
| 632 |
packetnum = smc91c111_allocate_packet(s); |
| 633 |
if (packetnum == 0x80) |
| 634 |
return;
|
| 635 |
s->rx_fifo[s->rx_fifo_len++] = packetnum; |
| 636 |
|
| 637 |
p = &s->data[packetnum][0];
|
| 638 |
/* ??? Multicast packets? */
|
| 639 |
status = 0;
|
| 640 |
if (size > 1518) |
| 641 |
status |= RS_TOOLONG; |
| 642 |
if (size & 1) |
| 643 |
status |= RS_ODDFRAME; |
| 644 |
*(p++) = status & 0xff;
|
| 645 |
*(p++) = status >> 8;
|
| 646 |
*(p++) = packetsize & 0xff;
|
| 647 |
*(p++) = packetsize >> 8;
|
| 648 |
memcpy(p, buf, size & ~1);
|
| 649 |
p += (size & ~1);
|
| 650 |
/* Pad short packets. */
|
| 651 |
if (size < 64) { |
| 652 |
int pad;
|
| 653 |
|
| 654 |
if (size & 1) |
| 655 |
*(p++) = buf[size - 1];
|
| 656 |
pad = 64 - size;
|
| 657 |
memset(p, 0, pad);
|
| 658 |
p += pad; |
| 659 |
size = 64;
|
| 660 |
} |
| 661 |
/* It's not clear if the CRC should go before or after the last byte in
|
| 662 |
odd sized packets. Linux disables the CRC, so that's no help.
|
| 663 |
The pictures in the documentation show the CRC aligned on a 16-bit
|
| 664 |
boundary before the last odd byte, so that's what we do. */
|
| 665 |
if (crc) {
|
| 666 |
crc = crc32(~0, buf, size);
|
| 667 |
*(p++) = crc & 0xff; crc >>= 8; |
| 668 |
*(p++) = crc & 0xff; crc >>= 8; |
| 669 |
*(p++) = crc & 0xff; crc >>= 8; |
| 670 |
*(p++) = crc & 0xff; crc >>= 8; |
| 671 |
} |
| 672 |
if (size & 1) { |
| 673 |
*(p++) = buf[size - 1];
|
| 674 |
*(p++) = 0x60;
|
| 675 |
} else {
|
| 676 |
*(p++) = 0;
|
| 677 |
*(p++) = 0x40;
|
| 678 |
} |
| 679 |
/* TODO: Raise early RX interrupt? */
|
| 680 |
s->int_level |= INT_RCV; |
| 681 |
smc91c111_update(s); |
| 682 |
} |
| 683 |
|
| 684 |
static CPUReadMemoryFunc *smc91c111_readfn[] = {
|
| 685 |
smc91c111_readb, |
| 686 |
smc91c111_readw, |
| 687 |
smc91c111_readl |
| 688 |
}; |
| 689 |
|
| 690 |
static CPUWriteMemoryFunc *smc91c111_writefn[] = {
|
| 691 |
smc91c111_writeb, |
| 692 |
smc91c111_writew, |
| 693 |
smc91c111_writel |
| 694 |
}; |
| 695 |
|
| 696 |
void smc91c111_init(NICInfo *nd, uint32_t base, void *pic, int irq) |
| 697 |
{
|
| 698 |
smc91c111_state *s; |
| 699 |
int iomemtype;
|
| 700 |
|
| 701 |
s = (smc91c111_state *)qemu_mallocz(sizeof(smc91c111_state));
|
| 702 |
iomemtype = cpu_register_io_memory(0, smc91c111_readfn,
|
| 703 |
smc91c111_writefn, s); |
| 704 |
cpu_register_physical_memory(base, 16, iomemtype);
|
| 705 |
s->base = base; |
| 706 |
s->pic = pic; |
| 707 |
s->irq = irq; |
| 708 |
memcpy(s->macaddr, nd->macaddr, 6);
|
| 709 |
|
| 710 |
smc91c111_reset(s); |
| 711 |
|
| 712 |
s->vc = qemu_new_vlan_client(nd->vlan, smc91c111_receive, |
| 713 |
smc91c111_can_receive, s); |
| 714 |
/* ??? Save/restore. */
|
| 715 |
} |