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1
/*
2
 * QEMU Sun4u/Sun4v System Emulator
3
 *
4
 * Copyright (c) 2005 Fabrice Bellard
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
23
 */
24
#include "hw.h"
25
#include "pci.h"
26
#include "apb_pci.h"
27
#include "pc.h"
28
#include "nvram.h"
29
#include "fdc.h"
30
#include "net.h"
31
#include "qemu-timer.h"
32
#include "sysemu.h"
33
#include "boards.h"
34
#include "firmware_abi.h"
35
#include "fw_cfg.h"
36
#include "sysbus.h"
37
#include "ide.h"
38
#include "loader.h"
39
#include "elf.h"
40

    
41
//#define DEBUG_IRQ
42
//#define DEBUG_EBUS
43

    
44
#ifdef DEBUG_IRQ
45
#define CPUIRQ_DPRINTF(fmt, ...)                                \
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    do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
47
#else
48
#define CPUIRQ_DPRINTF(fmt, ...)
49
#endif
50

    
51
#ifdef DEBUG_EBUS
52
#define EBUS_DPRINTF(fmt, ...)                                  \
53
    do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
54
#else
55
#define EBUS_DPRINTF(fmt, ...)
56
#endif
57

    
58
#define KERNEL_LOAD_ADDR     0x00404000
59
#define CMDLINE_ADDR         0x003ff000
60
#define INITRD_LOAD_ADDR     0x00300000
61
#define PROM_SIZE_MAX        (4 * 1024 * 1024)
62
#define PROM_VADDR           0x000ffd00000ULL
63
#define APB_SPECIAL_BASE     0x1fe00000000ULL
64
#define APB_MEM_BASE         0x1ff00000000ULL
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#define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
66
#define PROM_FILENAME        "openbios-sparc64"
67
#define NVRAM_SIZE           0x2000
68
#define MAX_IDE_BUS          2
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#define BIOS_CFG_IOPORT      0x510
70
#define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
71
#define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
72
#define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
73

    
74
#define MAX_PILS 16
75

    
76
#define TICK_MAX             0x7fffffffffffffffULL
77

    
78
struct hwdef {
79
    const char * const default_cpu_model;
80
    uint16_t machine_id;
81
    uint64_t prom_addr;
82
    uint64_t console_serial_base;
83
};
84

    
85
int DMA_get_channel_mode (int nchan)
86
{
87
    return 0;
88
}
89
int DMA_read_memory (int nchan, void *buf, int pos, int size)
90
{
91
    return 0;
92
}
93
int DMA_write_memory (int nchan, void *buf, int pos, int size)
94
{
95
    return 0;
96
}
97
void DMA_hold_DREQ (int nchan) {}
98
void DMA_release_DREQ (int nchan) {}
99
void DMA_schedule(int nchan) {}
100
void DMA_init (int high_page_enable) {}
101
void DMA_register_channel (int nchan,
102
                           DMA_transfer_handler transfer_handler,
103
                           void *opaque)
104
{
105
}
106

    
107
static int fw_cfg_boot_set(void *opaque, const char *boot_device)
108
{
109
    fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
110
    return 0;
111
}
112

    
113
static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
114
                                   const char *arch,
115
                                   ram_addr_t RAM_size,
116
                                   const char *boot_devices,
117
                                   uint32_t kernel_image, uint32_t kernel_size,
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                                   const char *cmdline,
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                                   uint32_t initrd_image, uint32_t initrd_size,
120
                                   uint32_t NVRAM_image,
121
                                   int width, int height, int depth,
122
                                   const uint8_t *macaddr)
123
{
124
    unsigned int i;
125
    uint32_t start, end;
126
    uint8_t image[0x1ff0];
127
    struct OpenBIOS_nvpart_v1 *part_header;
128

    
129
    memset(image, '\0', sizeof(image));
130

    
131
    start = 0;
132

    
133
    // OpenBIOS nvram variables
134
    // Variable partition
135
    part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
136
    part_header->signature = OPENBIOS_PART_SYSTEM;
137
    pstrcpy(part_header->name, sizeof(part_header->name), "system");
138

    
139
    end = start + sizeof(struct OpenBIOS_nvpart_v1);
140
    for (i = 0; i < nb_prom_envs; i++)
141
        end = OpenBIOS_set_var(image, end, prom_envs[i]);
142

    
143
    // End marker
144
    image[end++] = '\0';
145

    
146
    end = start + ((end - start + 15) & ~15);
147
    OpenBIOS_finish_partition(part_header, end - start);
148

    
149
    // free partition
150
    start = end;
151
    part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
152
    part_header->signature = OPENBIOS_PART_FREE;
153
    pstrcpy(part_header->name, sizeof(part_header->name), "free");
154

    
155
    end = 0x1fd0;
156
    OpenBIOS_finish_partition(part_header, end - start);
157

    
158
    Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
159

    
160
    for (i = 0; i < sizeof(image); i++)
161
        m48t59_write(nvram, i, image[i]);
162

    
163
    return 0;
164
}
165
static unsigned long sun4u_load_kernel(const char *kernel_filename,
166
                                       const char *initrd_filename,
167
                                       ram_addr_t RAM_size, long *initrd_size)
168
{
169
    int linux_boot;
170
    unsigned int i;
171
    long kernel_size;
172
    uint8_t *ptr;
173

    
174
    linux_boot = (kernel_filename != NULL);
175

    
176
    kernel_size = 0;
177
    if (linux_boot) {
178
        int bswap_needed;
179

    
180
#ifdef BSWAP_NEEDED
181
        bswap_needed = 1;
182
#else
183
        bswap_needed = 0;
184
#endif
185
        kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL,
186
                               1, ELF_MACHINE, 0);
187
        if (kernel_size < 0)
188
            kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
189
                                    RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
190
                                    TARGET_PAGE_SIZE);
191
        if (kernel_size < 0)
192
            kernel_size = load_image_targphys(kernel_filename,
193
                                              KERNEL_LOAD_ADDR,
194
                                              RAM_size - KERNEL_LOAD_ADDR);
195
        if (kernel_size < 0) {
196
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
197
                    kernel_filename);
198
            exit(1);
199
        }
200

    
201
        /* load initrd */
202
        *initrd_size = 0;
203
        if (initrd_filename) {
204
            *initrd_size = load_image_targphys(initrd_filename,
205
                                               INITRD_LOAD_ADDR,
206
                                               RAM_size - INITRD_LOAD_ADDR);
207
            if (*initrd_size < 0) {
208
                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
209
                        initrd_filename);
210
                exit(1);
211
            }
212
        }
213
        if (*initrd_size > 0) {
214
            for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
215
                ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
216
                if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
217
                    stl_p(ptr + 24, INITRD_LOAD_ADDR + KERNEL_LOAD_ADDR - 0x4000);
218
                    stl_p(ptr + 28, *initrd_size);
219
                    break;
220
                }
221
            }
222
        }
223
    }
224
    return kernel_size;
225
}
226

    
227
void pic_info(Monitor *mon)
228
{
229
}
230

    
231
void irq_info(Monitor *mon)
232
{
233
}
234

    
235
void cpu_check_irqs(CPUState *env)
236
{
237
    uint32_t pil = env->pil_in |
238
                  (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
239

    
240
    /* check if TM or SM in SOFTINT are set
241
       setting these also causes interrupt 14 */
242
    if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
243
        pil |= 1 << 14;
244
    }
245

    
246
    if (!pil) {
247
        if (env->interrupt_request & CPU_INTERRUPT_HARD) {
248
            CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
249
                           env->interrupt_index);
250
            env->interrupt_index = 0;
251
            cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
252
        }
253
        return;
254
    }
255

    
256
    if (cpu_interrupts_enabled(env)) {
257

    
258
        unsigned int i;
259

    
260
        for (i = 15; i > env->psrpil; i--) {
261
            if (pil & (1 << i)) {
262
                int old_interrupt = env->interrupt_index;
263
                int new_interrupt = TT_EXTINT | i;
264

    
265
                if (env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt) {
266
                    CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
267
                                   "current %x >= pending %x\n",
268
                                   env->tl, cpu_tsptr(env)->tt, new_interrupt);
269
                } else if (old_interrupt != new_interrupt) {
270
                    env->interrupt_index = new_interrupt;
271
                    CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
272
                                   old_interrupt, new_interrupt);
273
                    cpu_interrupt(env, CPU_INTERRUPT_HARD);
274
                }
275
                break;
276
            }
277
        }
278
    } else {
279
        CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
280
                       "current interrupt %x\n",
281
                       pil, env->pil_in, env->softint, env->interrupt_index);
282
    }
283
}
284

    
285
static void cpu_set_irq(void *opaque, int irq, int level)
286
{
287
    CPUState *env = opaque;
288

    
289
    if (level) {
290
        CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq);
291
        env->halted = 0;
292
        env->pil_in |= 1 << irq;
293
        cpu_check_irqs(env);
294
    } else {
295
        CPUIRQ_DPRINTF("Lower CPU IRQ %d\n", irq);
296
        env->pil_in &= ~(1 << irq);
297
        cpu_check_irqs(env);
298
    }
299
}
300

    
301
typedef struct ResetData {
302
    CPUState *env;
303
    uint64_t prom_addr;
304
} ResetData;
305

    
306
static void main_cpu_reset(void *opaque)
307
{
308
    ResetData *s = (ResetData *)opaque;
309
    CPUState *env = s->env;
310
    static unsigned int nr_resets;
311

    
312
    cpu_reset(env);
313
    env->tick_cmpr = TICK_INT_DIS | 0;
314
    ptimer_set_limit(env->tick, TICK_MAX, 1);
315
    ptimer_run(env->tick, 1);
316
    env->stick_cmpr = TICK_INT_DIS | 0;
317
    ptimer_set_limit(env->stick, TICK_MAX, 1);
318
    ptimer_run(env->stick, 1);
319
    env->hstick_cmpr = TICK_INT_DIS | 0;
320
    ptimer_set_limit(env->hstick, TICK_MAX, 1);
321
    ptimer_run(env->hstick, 1);
322
    env->gregs[1] = 0; // Memory start
323
    env->gregs[2] = ram_size; // Memory size
324
    env->gregs[3] = 0; // Machine description XXX
325
    if (nr_resets++ == 0) {
326
        /* Power on reset */
327
        env->pc = s->prom_addr + 0x20ULL;
328
    } else {
329
        env->pc = s->prom_addr + 0x40ULL;
330
    }
331
    env->npc = env->pc + 4;
332
}
333

    
334
static void tick_irq(void *opaque)
335
{
336
    CPUState *env = opaque;
337

    
338
    if (!(env->tick_cmpr & TICK_INT_DIS)) {
339
        env->softint |= SOFTINT_TIMER;
340
        cpu_interrupt(env, CPU_INTERRUPT_TIMER);
341
    }
342
}
343

    
344
static void stick_irq(void *opaque)
345
{
346
    CPUState *env = opaque;
347

    
348
    if (!(env->stick_cmpr & TICK_INT_DIS)) {
349
        env->softint |= SOFTINT_STIMER;
350
        cpu_interrupt(env, CPU_INTERRUPT_TIMER);
351
    }
352
}
353

    
354
static void hstick_irq(void *opaque)
355
{
356
    CPUState *env = opaque;
357

    
358
    if (!(env->hstick_cmpr & TICK_INT_DIS)) {
359
        cpu_interrupt(env, CPU_INTERRUPT_TIMER);
360
    }
361
}
362

    
363
void cpu_tick_set_count(void *opaque, uint64_t count)
364
{
365
    ptimer_set_count(opaque, -count);
366
}
367

    
368
uint64_t cpu_tick_get_count(void *opaque)
369
{
370
    return -ptimer_get_count(opaque);
371
}
372

    
373
void cpu_tick_set_limit(void *opaque, uint64_t limit)
374
{
375
    ptimer_set_limit(opaque, -limit, 0);
376
}
377

    
378
static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
379
                              pcibus_t addr, pcibus_t size, int type)
380
{
381
    EBUS_DPRINTF("Mapping region %d registers at %" FMT_PCIBUS "\n",
382
                 region_num, addr);
383
    switch (region_num) {
384
    case 0:
385
        isa_mmio_init(addr, 0x1000000);
386
        break;
387
    case 1:
388
        isa_mmio_init(addr, 0x800000);
389
        break;
390
    }
391
}
392

    
393
static void dummy_isa_irq_handler(void *opaque, int n, int level)
394
{
395
}
396

    
397
/* EBUS (Eight bit bus) bridge */
398
static void
399
pci_ebus_init(PCIBus *bus, int devfn)
400
{
401
    qemu_irq *isa_irq;
402

    
403
    pci_create_simple(bus, devfn, "ebus");
404
    isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16);
405
    isa_bus_irqs(isa_irq);
406
}
407

    
408
static int
409
pci_ebus_init1(PCIDevice *s)
410
{
411
    isa_bus_new(&s->qdev);
412

    
413
    pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN);
414
    pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS);
415
    s->config[0x04] = 0x06; // command = bus master, pci mem
416
    s->config[0x05] = 0x00;
417
    s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
418
    s->config[0x07] = 0x03; // status = medium devsel
419
    s->config[0x08] = 0x01; // revision
420
    s->config[0x09] = 0x00; // programming i/f
421
    pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
422
    s->config[0x0D] = 0x0a; // latency_timer
423
    s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
424

    
425
    pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_MEMORY,
426
                           ebus_mmio_mapfunc);
427
    pci_register_bar(s, 1, 0x800000,  PCI_BASE_ADDRESS_SPACE_MEMORY,
428
                           ebus_mmio_mapfunc);
429
    return 0;
430
}
431

    
432
static PCIDeviceInfo ebus_info = {
433
    .qdev.name = "ebus",
434
    .qdev.size = sizeof(PCIDevice),
435
    .init = pci_ebus_init1,
436
};
437

    
438
static void pci_ebus_register(void)
439
{
440
    pci_qdev_register(&ebus_info);
441
}
442

    
443
device_init(pci_ebus_register);
444

    
445
/* Boot PROM (OpenBIOS) */
446
static void prom_init(target_phys_addr_t addr, const char *bios_name)
447
{
448
    DeviceState *dev;
449
    SysBusDevice *s;
450
    char *filename;
451
    int ret;
452

    
453
    dev = qdev_create(NULL, "openprom");
454
    qdev_init_nofail(dev);
455
    s = sysbus_from_qdev(dev);
456

    
457
    sysbus_mmio_map(s, 0, addr);
458

    
459
    /* load boot prom */
460
    if (bios_name == NULL) {
461
        bios_name = PROM_FILENAME;
462
    }
463
    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
464
    if (filename) {
465
        ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL,
466
                       1, ELF_MACHINE, 0);
467
        if (ret < 0 || ret > PROM_SIZE_MAX) {
468
            ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
469
        }
470
        qemu_free(filename);
471
    } else {
472
        ret = -1;
473
    }
474
    if (ret < 0 || ret > PROM_SIZE_MAX) {
475
        fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
476
        exit(1);
477
    }
478
}
479

    
480
static int prom_init1(SysBusDevice *dev)
481
{
482
    ram_addr_t prom_offset;
483

    
484
    prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
485
    sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
486
    return 0;
487
}
488

    
489
static SysBusDeviceInfo prom_info = {
490
    .init = prom_init1,
491
    .qdev.name  = "openprom",
492
    .qdev.size  = sizeof(SysBusDevice),
493
    .qdev.props = (Property[]) {
494
        {/* end of property list */}
495
    }
496
};
497

    
498
static void prom_register_devices(void)
499
{
500
    sysbus_register_withprop(&prom_info);
501
}
502

    
503
device_init(prom_register_devices);
504

    
505

    
506
typedef struct RamDevice
507
{
508
    SysBusDevice busdev;
509
    uint64_t size;
510
} RamDevice;
511

    
512
/* System RAM */
513
static int ram_init1(SysBusDevice *dev)
514
{
515
    ram_addr_t RAM_size, ram_offset;
516
    RamDevice *d = FROM_SYSBUS(RamDevice, dev);
517

    
518
    RAM_size = d->size;
519

    
520
    ram_offset = qemu_ram_alloc(RAM_size);
521
    sysbus_init_mmio(dev, RAM_size, ram_offset);
522
    return 0;
523
}
524

    
525
static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
526
{
527
    DeviceState *dev;
528
    SysBusDevice *s;
529
    RamDevice *d;
530

    
531
    /* allocate RAM */
532
    dev = qdev_create(NULL, "memory");
533
    s = sysbus_from_qdev(dev);
534

    
535
    d = FROM_SYSBUS(RamDevice, s);
536
    d->size = RAM_size;
537
    qdev_init_nofail(dev);
538

    
539
    sysbus_mmio_map(s, 0, addr);
540
}
541

    
542
static SysBusDeviceInfo ram_info = {
543
    .init = ram_init1,
544
    .qdev.name  = "memory",
545
    .qdev.size  = sizeof(RamDevice),
546
    .qdev.props = (Property[]) {
547
        DEFINE_PROP_UINT64("size", RamDevice, size, 0),
548
        DEFINE_PROP_END_OF_LIST(),
549
    }
550
};
551

    
552
static void ram_register_devices(void)
553
{
554
    sysbus_register_withprop(&ram_info);
555
}
556

    
557
device_init(ram_register_devices);
558

    
559
static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
560
{
561
    CPUState *env;
562
    QEMUBH *bh;
563
    ResetData *reset_info;
564

    
565
    if (!cpu_model)
566
        cpu_model = hwdef->default_cpu_model;
567
    env = cpu_init(cpu_model);
568
    if (!env) {
569
        fprintf(stderr, "Unable to find Sparc CPU definition\n");
570
        exit(1);
571
    }
572
    bh = qemu_bh_new(tick_irq, env);
573
    env->tick = ptimer_init(bh);
574
    ptimer_set_period(env->tick, 1ULL);
575

    
576
    bh = qemu_bh_new(stick_irq, env);
577
    env->stick = ptimer_init(bh);
578
    ptimer_set_period(env->stick, 1ULL);
579

    
580
    bh = qemu_bh_new(hstick_irq, env);
581
    env->hstick = ptimer_init(bh);
582
    ptimer_set_period(env->hstick, 1ULL);
583

    
584
    reset_info = qemu_mallocz(sizeof(ResetData));
585
    reset_info->env = env;
586
    reset_info->prom_addr = hwdef->prom_addr;
587
    qemu_register_reset(main_cpu_reset, reset_info);
588

    
589
    return env;
590
}
591

    
592
static void sun4uv_init(ram_addr_t RAM_size,
593
                        const char *boot_devices,
594
                        const char *kernel_filename, const char *kernel_cmdline,
595
                        const char *initrd_filename, const char *cpu_model,
596
                        const struct hwdef *hwdef)
597
{
598
    CPUState *env;
599
    m48t59_t *nvram;
600
    unsigned int i;
601
    long initrd_size, kernel_size;
602
    PCIBus *pci_bus, *pci_bus2, *pci_bus3;
603
    qemu_irq *irq;
604
    DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
605
    DriveInfo *fd[MAX_FD];
606
    void *fw_cfg;
607

    
608
    /* init CPUs */
609
    env = cpu_devinit(cpu_model, hwdef);
610

    
611
    /* set up devices */
612
    ram_init(0, RAM_size);
613

    
614
    prom_init(hwdef->prom_addr, bios_name);
615

    
616

    
617
    irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
618
    pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2,
619
                           &pci_bus3);
620
    isa_mem_base = VGA_BASE;
621
    pci_vga_init(pci_bus, 0, 0);
622

    
623
    // XXX Should be pci_bus3
624
    pci_ebus_init(pci_bus, -1);
625

    
626
    i = 0;
627
    if (hwdef->console_serial_base) {
628
        serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
629
                       serial_hds[i], 1);
630
        i++;
631
    }
632
    for(; i < MAX_SERIAL_PORTS; i++) {
633
        if (serial_hds[i]) {
634
            serial_isa_init(i, serial_hds[i]);
635
        }
636
    }
637

    
638
    for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
639
        if (parallel_hds[i]) {
640
            parallel_init(i, parallel_hds[i]);
641
        }
642
    }
643

    
644
    for(i = 0; i < nb_nics; i++)
645
        pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
646

    
647
    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
648
        fprintf(stderr, "qemu: too many IDE bus\n");
649
        exit(1);
650
    }
651
    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
652
        hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS,
653
                          i % MAX_IDE_DEVS);
654
    }
655

    
656
    pci_cmd646_ide_init(pci_bus, hd, 1);
657

    
658
    isa_create_simple("i8042");
659
    for(i = 0; i < MAX_FD; i++) {
660
        fd[i] = drive_get(IF_FLOPPY, 0, i);
661
    }
662
    fdctrl_init_isa(fd);
663
    nvram = m48t59_init_isa(0x0074, NVRAM_SIZE, 59);
664

    
665
    initrd_size = 0;
666
    kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
667
                                    ram_size, &initrd_size);
668

    
669
    sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
670
                           KERNEL_LOAD_ADDR, kernel_size,
671
                           kernel_cmdline,
672
                           INITRD_LOAD_ADDR, initrd_size,
673
                           /* XXX: need an option to load a NVRAM image */
674
                           0,
675
                           graphic_width, graphic_height, graphic_depth,
676
                           (uint8_t *)&nd_table[0].macaddr);
677

    
678
    fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
679
    fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
680
    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
681
    fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
682
    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
683
    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
684
    if (kernel_cmdline) {
685
        fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
686
                       strlen(kernel_cmdline) + 1);
687
        fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
688
                         (uint8_t*)strdup(kernel_cmdline),
689
                         strlen(kernel_cmdline) + 1);
690
    } else {
691
        fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
692
    }
693
    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
694
    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
695
    fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
696

    
697
    fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
698
    fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
699
    fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
700

    
701
    qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
702
}
703

    
704
enum {
705
    sun4u_id = 0,
706
    sun4v_id = 64,
707
    niagara_id,
708
};
709

    
710
static const struct hwdef hwdefs[] = {
711
    /* Sun4u generic PC-like machine */
712
    {
713
        .default_cpu_model = "TI UltraSparc II",
714
        .machine_id = sun4u_id,
715
        .prom_addr = 0x1fff0000000ULL,
716
        .console_serial_base = 0,
717
    },
718
    /* Sun4v generic PC-like machine */
719
    {
720
        .default_cpu_model = "Sun UltraSparc T1",
721
        .machine_id = sun4v_id,
722
        .prom_addr = 0x1fff0000000ULL,
723
        .console_serial_base = 0,
724
    },
725
    /* Sun4v generic Niagara machine */
726
    {
727
        .default_cpu_model = "Sun UltraSparc T1",
728
        .machine_id = niagara_id,
729
        .prom_addr = 0xfff0000000ULL,
730
        .console_serial_base = 0xfff0c2c000ULL,
731
    },
732
};
733

    
734
/* Sun4u hardware initialisation */
735
static void sun4u_init(ram_addr_t RAM_size,
736
                       const char *boot_devices,
737
                       const char *kernel_filename, const char *kernel_cmdline,
738
                       const char *initrd_filename, const char *cpu_model)
739
{
740
    sun4uv_init(RAM_size, boot_devices, kernel_filename,
741
                kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
742
}
743

    
744
/* Sun4v hardware initialisation */
745
static void sun4v_init(ram_addr_t RAM_size,
746
                       const char *boot_devices,
747
                       const char *kernel_filename, const char *kernel_cmdline,
748
                       const char *initrd_filename, const char *cpu_model)
749
{
750
    sun4uv_init(RAM_size, boot_devices, kernel_filename,
751
                kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
752
}
753

    
754
/* Niagara hardware initialisation */
755
static void niagara_init(ram_addr_t RAM_size,
756
                         const char *boot_devices,
757
                         const char *kernel_filename, const char *kernel_cmdline,
758
                         const char *initrd_filename, const char *cpu_model)
759
{
760
    sun4uv_init(RAM_size, boot_devices, kernel_filename,
761
                kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
762
}
763

    
764
static QEMUMachine sun4u_machine = {
765
    .name = "sun4u",
766
    .desc = "Sun4u platform",
767
    .init = sun4u_init,
768
    .max_cpus = 1, // XXX for now
769
    .is_default = 1,
770
};
771

    
772
static QEMUMachine sun4v_machine = {
773
    .name = "sun4v",
774
    .desc = "Sun4v platform",
775
    .init = sun4v_init,
776
    .max_cpus = 1, // XXX for now
777
};
778

    
779
static QEMUMachine niagara_machine = {
780
    .name = "Niagara",
781
    .desc = "Sun4v platform, Niagara",
782
    .init = niagara_init,
783
    .max_cpus = 1, // XXX for now
784
};
785

    
786
static void sun4u_machine_init(void)
787
{
788
    qemu_register_machine(&sun4u_machine);
789
    qemu_register_machine(&sun4v_machine);
790
    qemu_register_machine(&niagara_machine);
791
}
792

    
793
machine_init(sun4u_machine_init);