Revision 69d6275b target-sh4/translate.c
| b/target-sh4/translate.c | ||
|---|---|---|
| 337 | 337 |
tcg_gen_ori_i32(cpu_flags, cpu_flags, flags); |
| 338 | 338 |
} |
| 339 | 339 |
|
| 340 |
static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1) |
|
| 341 |
{
|
|
| 342 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I32); |
|
| 343 |
|
|
| 344 |
p0 &= 0x1f; |
|
| 345 |
p1 &= 0x1f; |
|
| 346 |
|
|
| 347 |
tcg_gen_andi_i32(tmp, t1, (1 << p1)); |
|
| 348 |
tcg_gen_andi_i32(t0, t0, ~(1 << p0)); |
|
| 349 |
if (p0 < p1) |
|
| 350 |
tcg_gen_shri_i32(tmp, tmp, p1 - p0); |
|
| 351 |
else if (p0 > p1) |
|
| 352 |
tcg_gen_shli_i32(tmp, tmp, p0 - p1); |
|
| 353 |
tcg_gen_or_i32(t0, t0, tmp); |
|
| 354 |
|
|
| 355 |
tcg_temp_free(tmp); |
|
| 356 |
} |
|
| 357 |
|
|
| 340 | 358 |
#define B3_0 (ctx->opcode & 0xf) |
| 341 | 359 |
#define B6_4 ((ctx->opcode >> 4) & 0x7) |
| 342 | 360 |
#define B7_4 ((ctx->opcode >> 4) & 0xf) |
| ... | ... | |
| 643 | 661 |
gen_cmp(TCG_COND_GEU, cpu_T[0], cpu_T[1]); |
| 644 | 662 |
return; |
| 645 | 663 |
case 0x200c: /* cmp/str Rm,Rn */ |
| 646 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 647 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
| 648 |
gen_op_cmp_str_T0_T1(); |
|
| 664 |
{
|
|
| 665 |
int label1 = gen_new_label(); |
|
| 666 |
int label2 = gen_new_label(); |
|
| 667 |
tcg_gen_xor_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(B11_8)]); |
|
| 668 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0xff000000); |
|
| 669 |
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_T[0], 0, label1); |
|
| 670 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0x00ff0000); |
|
| 671 |
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_T[0], 0, label1); |
|
| 672 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0x0000ff00); |
|
| 673 |
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_T[0], 0, label1); |
|
| 674 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0x000000ff); |
|
| 675 |
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_T[0], 0, label1); |
|
| 676 |
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); |
|
| 677 |
tcg_gen_br(label2); |
|
| 678 |
gen_set_label(label1); |
|
| 679 |
tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T); |
|
| 680 |
gen_set_label(label2); |
|
| 681 |
} |
|
| 649 | 682 |
return; |
| 650 | 683 |
case 0x2007: /* div0s Rm,Rn */ |
| 651 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 652 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
| 653 |
gen_op_div0s_T0_T1(); |
|
| 684 |
gen_copy_bit_i32(cpu_sr, 8, cpu_gregs[REG(B11_8)], 31); /* SR_Q */ |
|
| 685 |
gen_copy_bit_i32(cpu_sr, 9, cpu_gregs[REG(B7_4)], 31); /* SR_M */ |
|
| 686 |
tcg_gen_xor_i32(cpu_T[0], cpu_gregs[REG(B7_4)], cpu_gregs[REG(B11_8)]); |
|
| 687 |
gen_copy_bit_i32(cpu_sr, 0, cpu_T[0], 31); /* SR_T */ |
|
| 654 | 688 |
return; |
| 655 | 689 |
case 0x3004: /* div1 Rm,Rn */ |
| 656 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 657 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
| 658 |
gen_op_div1_T0_T1(); |
|
| 659 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]); |
|
| 690 |
tcg_gen_helper_1_2(helper_div1, cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)], cpu_gregs[REG(B11_8)]); |
|
| 660 | 691 |
return; |
| 661 | 692 |
case 0x300d: /* dmuls.l Rm,Rn */ |
| 662 | 693 |
{
|
| ... | ... | |
| 758 | 789 |
tcg_gen_or_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); |
| 759 | 790 |
return; |
| 760 | 791 |
case 0x400c: /* shad Rm,Rn */ |
| 761 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 762 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
| 763 |
gen_op_shad_T0_T1(); |
|
| 764 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]); |
|
| 792 |
{
|
|
| 793 |
int label1 = gen_new_label(); |
|
| 794 |
int label2 = gen_new_label(); |
|
| 795 |
int label3 = gen_new_label(); |
|
| 796 |
int label4 = gen_new_label(); |
|
| 797 |
tcg_gen_brcondi_i32(TCG_COND_LT, cpu_gregs[REG(B7_4)], 0, label1); |
|
| 798 |
/* Rm positive, shift to the left */ |
|
| 799 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0x1f); |
|
| 800 |
tcg_gen_shl_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 801 |
tcg_gen_br(label4); |
|
| 802 |
/* Rm negative, shift to the right */ |
|
| 803 |
gen_set_label(label1); |
|
| 804 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0x1f); |
|
| 805 |
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_T[0], 0, label2); |
|
| 806 |
tcg_gen_not_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 807 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0x1f); |
|
| 808 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], 1); |
|
| 809 |
tcg_gen_sar_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 810 |
tcg_gen_br(label4); |
|
| 811 |
/* Rm = -32 */ |
|
| 812 |
gen_set_label(label2); |
|
| 813 |
tcg_gen_brcondi_i32(TCG_COND_LT, cpu_gregs[REG(B11_8)], 0, label3); |
|
| 814 |
tcg_gen_movi_i32(cpu_gregs[REG(B11_8)], 0); |
|
| 815 |
tcg_gen_br(label4); |
|
| 816 |
gen_set_label(label3); |
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| 817 |
tcg_gen_movi_i32(cpu_gregs[REG(B11_8)], 0xffffffff); |
|
| 818 |
gen_set_label(label4); |
|
| 819 |
} |
|
| 765 | 820 |
return; |
| 766 | 821 |
case 0x400d: /* shld Rm,Rn */ |
| 767 |
tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 768 |
tcg_gen_mov_i32(cpu_T[1], cpu_gregs[REG(B11_8)]); |
|
| 769 |
gen_op_shld_T0_T1(); |
|
| 770 |
tcg_gen_mov_i32(cpu_gregs[REG(B11_8)], cpu_T[1]); |
|
| 822 |
{
|
|
| 823 |
int label1 = gen_new_label(); |
|
| 824 |
int label2 = gen_new_label(); |
|
| 825 |
int label3 = gen_new_label(); |
|
| 826 |
tcg_gen_brcondi_i32(TCG_COND_LT, cpu_gregs[REG(B7_4)], 0, label1); |
|
| 827 |
/* Rm positive, shift to the left */ |
|
| 828 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0x1f); |
|
| 829 |
tcg_gen_shl_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 830 |
tcg_gen_br(label3); |
|
| 831 |
/* Rm negative, shift to the right */ |
|
| 832 |
gen_set_label(label1); |
|
| 833 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B7_4)], 0x1f); |
|
| 834 |
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_T[0], 0, label2); |
|
| 835 |
tcg_gen_not_i32(cpu_T[0], cpu_gregs[REG(B7_4)]); |
|
| 836 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], 0x1f); |
|
| 837 |
tcg_gen_addi_i32(cpu_T[0], cpu_T[0], 1); |
|
| 838 |
tcg_gen_shr_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_T[0]); |
|
| 839 |
tcg_gen_br(label3); |
|
| 840 |
/* Rm = -32 */ |
|
| 841 |
gen_set_label(label2); |
|
| 842 |
tcg_gen_movi_i32(cpu_gregs[REG(B11_8)], 0); |
|
| 843 |
gen_set_label(label3); |
|
| 844 |
} |
|
| 771 | 845 |
return; |
| 772 | 846 |
case 0x3008: /* sub Rm,Rn */ |
| 773 | 847 |
tcg_gen_sub_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], cpu_gregs[REG(B7_4)]); |
| ... | ... | |
| 1213 | 1287 |
case 0x0083: /* pref @Rn */ |
| 1214 | 1288 |
return; |
| 1215 | 1289 |
case 0x4024: /* rotcl Rn */ |
| 1216 |
gen_op_rotcl_Rn(REG(B11_8)); |
|
| 1290 |
tcg_gen_mov_i32(cpu_T[0], cpu_sr); |
|
| 1291 |
gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 31); |
|
| 1292 |
tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); |
|
| 1293 |
gen_copy_bit_i32(cpu_gregs[REG(B11_8)], 0, cpu_T[0], 0); |
|
| 1217 | 1294 |
return; |
| 1218 | 1295 |
case 0x4025: /* rotcr Rn */ |
| 1219 |
gen_op_rotcr_Rn(REG(B11_8)); |
|
| 1296 |
tcg_gen_mov_i32(cpu_T[0], cpu_sr); |
|
| 1297 |
gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 0); |
|
| 1298 |
tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); |
|
| 1299 |
gen_copy_bit_i32(cpu_gregs[REG(B11_8)], 31, cpu_T[0], 0); |
|
| 1220 | 1300 |
return; |
| 1221 | 1301 |
case 0x4004: /* rotl Rn */ |
| 1222 |
gen_op_rotl_Rn(REG(B11_8)); |
|
| 1302 |
gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 31); |
|
| 1303 |
tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); |
|
| 1304 |
gen_copy_bit_i32(cpu_gregs[REG(B11_8)], 0, cpu_sr, 0); |
|
| 1223 | 1305 |
return; |
| 1224 | 1306 |
case 0x4005: /* rotr Rn */ |
| 1225 |
gen_op_rotr_Rn(REG(B11_8)); |
|
| 1307 |
gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 0); |
|
| 1308 |
tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); |
|
| 1309 |
gen_copy_bit_i32(cpu_gregs[REG(B11_8)], 31, cpu_sr, 0); |
|
| 1226 | 1310 |
return; |
| 1227 | 1311 |
case 0x4000: /* shll Rn */ |
| 1228 | 1312 |
case 0x4020: /* shal Rn */ |
| 1229 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 0x80000000); |
|
| 1230 |
gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0); |
|
| 1313 |
gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 31); |
|
| 1231 | 1314 |
tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); |
| 1232 | 1315 |
return; |
| 1233 | 1316 |
case 0x4021: /* shar Rn */ |
| 1234 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 1); |
|
| 1235 |
gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0); |
|
| 1317 |
gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 0); |
|
| 1236 | 1318 |
tcg_gen_sari_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); |
| 1237 | 1319 |
return; |
| 1238 | 1320 |
case 0x4001: /* shlr Rn */ |
| 1239 |
tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 1); |
|
| 1240 |
gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0); |
|
| 1321 |
gen_copy_bit_i32(cpu_sr, 0, cpu_gregs[REG(B11_8)], 0); |
|
| 1241 | 1322 |
tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); |
| 1242 | 1323 |
return; |
| 1243 | 1324 |
case 0x4008: /* shll2 Rn */ |
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