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1 | 8977f3c1 | bellard | /*
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2 | 8977f3c1 | bellard | * QEMU Floppy disk emulator
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3 | 8977f3c1 | bellard | *
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4 | 8977f3c1 | bellard | * Copyright (c) 2003 Jocelyn Mayer
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5 | 8977f3c1 | bellard | *
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6 | 8977f3c1 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 8977f3c1 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 8977f3c1 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 8977f3c1 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 8977f3c1 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 8977f3c1 | bellard | * furnished to do so, subject to the following conditions:
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12 | 8977f3c1 | bellard | *
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13 | 8977f3c1 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 8977f3c1 | bellard | * all copies or substantial portions of the Software.
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15 | 8977f3c1 | bellard | *
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16 | 8977f3c1 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 8977f3c1 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 8977f3c1 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 8977f3c1 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 8977f3c1 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 8977f3c1 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 8977f3c1 | bellard | * THE SOFTWARE.
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23 | 8977f3c1 | bellard | */
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24 | 8977f3c1 | bellard | #include <stdio.h> |
25 | 8977f3c1 | bellard | #include <stdlib.h> |
26 | 8977f3c1 | bellard | #include <string.h> |
27 | 8977f3c1 | bellard | #include <inttypes.h> |
28 | 8977f3c1 | bellard | |
29 | 8977f3c1 | bellard | #include "cpu.h" |
30 | 8977f3c1 | bellard | #include "vl.h" |
31 | 8977f3c1 | bellard | |
32 | 8977f3c1 | bellard | /********************************************************/
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33 | 8977f3c1 | bellard | /* debug Floppy devices */
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34 | 8977f3c1 | bellard | //#define DEBUG_FLOPPY
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35 | 8977f3c1 | bellard | |
36 | 8977f3c1 | bellard | #ifdef DEBUG_FLOPPY
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37 | 8977f3c1 | bellard | #define FLOPPY_DPRINTF(fmt, args...) \
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38 | 8977f3c1 | bellard | do { printf("FLOPPY: " fmt , ##args); } while (0) |
39 | 8977f3c1 | bellard | #else
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40 | 8977f3c1 | bellard | #define FLOPPY_DPRINTF(fmt, args...)
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41 | 8977f3c1 | bellard | #endif
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42 | 8977f3c1 | bellard | |
43 | 8977f3c1 | bellard | #define FLOPPY_ERROR(fmt, args...) \
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44 | 8977f3c1 | bellard | do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ##args); } while (0) |
45 | 8977f3c1 | bellard | |
46 | 8977f3c1 | bellard | /********************************************************/
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47 | 8977f3c1 | bellard | /* Floppy drive emulation */
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48 | 8977f3c1 | bellard | |
49 | 8977f3c1 | bellard | /* Will always be a fixed parameter for us */
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50 | 8977f3c1 | bellard | #define FD_SECTOR_LEN 512 |
51 | 8977f3c1 | bellard | #define FD_SECTOR_SC 2 /* Sector size code */ |
52 | 8977f3c1 | bellard | |
53 | 8977f3c1 | bellard | /* Floppy disk drive emulation */
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54 | 8977f3c1 | bellard | typedef enum fdisk_type_t { |
55 | 8977f3c1 | bellard | FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */ |
56 | 8977f3c1 | bellard | FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */ |
57 | 8977f3c1 | bellard | FDRIVE_DISK_720 = 0x03, /* 720 kB disk */ |
58 | 8977f3c1 | bellard | FDRIVE_DISK_NONE = 0x04, /* No disk */ |
59 | 8977f3c1 | bellard | } fdisk_type_t; |
60 | 8977f3c1 | bellard | |
61 | 8977f3c1 | bellard | typedef enum fdrive_type_t { |
62 | 8977f3c1 | bellard | FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */ |
63 | 8977f3c1 | bellard | FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */ |
64 | 8977f3c1 | bellard | FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */ |
65 | 8977f3c1 | bellard | FDRIVE_DRV_NONE = 0x03, /* No drive connected */ |
66 | 8977f3c1 | bellard | } fdrive_type_t; |
67 | 8977f3c1 | bellard | |
68 | 8977f3c1 | bellard | typedef struct fdrive_t { |
69 | 8977f3c1 | bellard | BlockDriverState *bs; |
70 | 8977f3c1 | bellard | /* Drive status */
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71 | 8977f3c1 | bellard | fdrive_type_t drive; |
72 | 8977f3c1 | bellard | uint8_t motor; /* on/off */
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73 | 8977f3c1 | bellard | uint8_t perpendicular; /* 2.88 MB access mode */
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74 | 8977f3c1 | bellard | uint8_t rv; /* Revalidated */
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75 | 8977f3c1 | bellard | /* Position */
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76 | 8977f3c1 | bellard | uint8_t head; |
77 | 8977f3c1 | bellard | uint8_t track; |
78 | 8977f3c1 | bellard | uint8_t sect; |
79 | 8977f3c1 | bellard | /* Last operation status */
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80 | 8977f3c1 | bellard | uint8_t dir; /* Direction */
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81 | 8977f3c1 | bellard | uint8_t rw; /* Read/write */
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82 | 8977f3c1 | bellard | /* Media */
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83 | 8977f3c1 | bellard | fdisk_type_t disk; /* Disk type */
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84 | 8977f3c1 | bellard | uint8_t last_sect; /* Nb sector per track */
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85 | 8977f3c1 | bellard | uint8_t max_track; /* Nb of tracks */
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86 | 8977f3c1 | bellard | uint8_t ro; /* Is read-only */
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87 | 8977f3c1 | bellard | } fdrive_t; |
88 | 8977f3c1 | bellard | |
89 | 8977f3c1 | bellard | static void fd_init (fdrive_t *drv) |
90 | 8977f3c1 | bellard | { |
91 | 8977f3c1 | bellard | /* Drive */
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92 | 8977f3c1 | bellard | drv->bs = NULL;
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93 | 8977f3c1 | bellard | // drv->drive = FDRIVE_DRV_288;
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94 | 8977f3c1 | bellard | drv->drive = FDRIVE_DRV_144; |
95 | 8977f3c1 | bellard | drv->motor = 0;
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96 | 8977f3c1 | bellard | drv->perpendicular = 0;
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97 | 8977f3c1 | bellard | drv->rv = 0;
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98 | 8977f3c1 | bellard | /* Disk */
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99 | 8977f3c1 | bellard | drv->disk = FDRIVE_DISK_NONE; |
100 | 8977f3c1 | bellard | drv->last_sect = 1;
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101 | 8977f3c1 | bellard | drv->max_track = 0;
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102 | 8977f3c1 | bellard | } |
103 | 8977f3c1 | bellard | |
104 | 8977f3c1 | bellard | static int _fd_sector (uint8_t head, uint8_t track, |
105 | 8977f3c1 | bellard | uint8_t sect, uint8_t last_sect) |
106 | 8977f3c1 | bellard | { |
107 | 8977f3c1 | bellard | return (((track * 2) + head) * last_sect) + sect - 1; |
108 | 8977f3c1 | bellard | } |
109 | 8977f3c1 | bellard | |
110 | 8977f3c1 | bellard | /* Returns current position, in sectors, for given drive */
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111 | 8977f3c1 | bellard | static int fd_sector (fdrive_t *drv) |
112 | 8977f3c1 | bellard | { |
113 | 8977f3c1 | bellard | return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
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114 | 8977f3c1 | bellard | } |
115 | 8977f3c1 | bellard | |
116 | 8977f3c1 | bellard | static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect, |
117 | 8977f3c1 | bellard | int enable_seek)
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118 | 8977f3c1 | bellard | { |
119 | 8977f3c1 | bellard | uint32_t sector; |
120 | 8977f3c1 | bellard | |
121 | 8977f3c1 | bellard | if (track > drv->max_track) {
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122 | 8977f3c1 | bellard | FLOPPY_ERROR("try to read %d %02x %02x (max=%d %02x %02x)\n",
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123 | 8977f3c1 | bellard | head, track, sect, 1, drv->max_track, drv->last_sect);
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124 | 8977f3c1 | bellard | return 2; |
125 | 8977f3c1 | bellard | } |
126 | 8977f3c1 | bellard | if (sect > drv->last_sect) {
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127 | 8977f3c1 | bellard | FLOPPY_ERROR("try to read %d %02x %02x (max=%d %02x %02x)\n",
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128 | 8977f3c1 | bellard | head, track, sect, 1, drv->max_track, drv->last_sect);
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129 | 8977f3c1 | bellard | return 3; |
130 | 8977f3c1 | bellard | } |
131 | 8977f3c1 | bellard | sector = _fd_sector(head, track, sect, drv->last_sect); |
132 | 8977f3c1 | bellard | if (sector != fd_sector(drv)) {
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133 | 8977f3c1 | bellard | #if 0
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134 | 8977f3c1 | bellard | if (!enable_seek) {
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135 | 8977f3c1 | bellard | FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
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136 | 8977f3c1 | bellard | head, track, sect, 1, drv->max_track, drv->last_sect);
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137 | 8977f3c1 | bellard | return 4;
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138 | 8977f3c1 | bellard | }
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139 | 8977f3c1 | bellard | #endif
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140 | 8977f3c1 | bellard | drv->head = head; |
141 | 8977f3c1 | bellard | drv->track = track; |
142 | 8977f3c1 | bellard | drv->sect = sect; |
143 | 8977f3c1 | bellard | return 1; |
144 | 8977f3c1 | bellard | } |
145 | 8977f3c1 | bellard | |
146 | 8977f3c1 | bellard | return 0; |
147 | 8977f3c1 | bellard | } |
148 | 8977f3c1 | bellard | |
149 | 8977f3c1 | bellard | /* Set drive back to track 0 */
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150 | 8977f3c1 | bellard | static void fd_recalibrate (fdrive_t *drv) |
151 | 8977f3c1 | bellard | { |
152 | 8977f3c1 | bellard | FLOPPY_DPRINTF("recalibrate\n");
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153 | 8977f3c1 | bellard | drv->head = 0;
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154 | 8977f3c1 | bellard | drv->track = 0;
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155 | 8977f3c1 | bellard | drv->sect = 1;
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156 | 8977f3c1 | bellard | drv->dir = 1;
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157 | 8977f3c1 | bellard | drv->rw = 0;
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158 | 8977f3c1 | bellard | } |
159 | 8977f3c1 | bellard | |
160 | 8977f3c1 | bellard | /* Revalidate a disk drive after a disk change */
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161 | 8977f3c1 | bellard | static void fd_revalidate (fdrive_t *drv, int ro) |
162 | 8977f3c1 | bellard | { |
163 | 8977f3c1 | bellard | int64_t nb_sectors; |
164 | 8977f3c1 | bellard | |
165 | 8977f3c1 | bellard | FLOPPY_DPRINTF("revalidate\n");
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166 | 8977f3c1 | bellard | drv->rv = 0;
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167 | 8977f3c1 | bellard | if (drv->bs != NULL) { |
168 | 8977f3c1 | bellard | bdrv_get_geometry(drv->bs, &nb_sectors); |
169 | 8977f3c1 | bellard | #if 1 |
170 | 8977f3c1 | bellard | if (nb_sectors > 2880) |
171 | 8977f3c1 | bellard | #endif
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172 | 8977f3c1 | bellard | { |
173 | 8977f3c1 | bellard | /* Pretend we have a 2.88 MB disk */
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174 | 8977f3c1 | bellard | drv->disk = FDRIVE_DISK_288; |
175 | 8977f3c1 | bellard | drv->last_sect = 36;
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176 | 8977f3c1 | bellard | drv->max_track = 80;
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177 | 8977f3c1 | bellard | #if 1 |
178 | 8977f3c1 | bellard | } else if (nb_sectors > 1440) { |
179 | 8977f3c1 | bellard | /* Pretend we have a 1.44 MB disk */
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180 | 8977f3c1 | bellard | drv->disk = FDRIVE_DISK_144; |
181 | 8977f3c1 | bellard | drv->last_sect = 18;
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182 | 8977f3c1 | bellard | drv->max_track = 80;
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183 | 8977f3c1 | bellard | } else {
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184 | 8977f3c1 | bellard | /* Pretend we have a 720 kB disk */
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185 | 8977f3c1 | bellard | drv->disk = FDRIVE_DISK_720; |
186 | 8977f3c1 | bellard | drv->last_sect = 9;
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187 | 8977f3c1 | bellard | drv->max_track = 80;
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188 | 8977f3c1 | bellard | #endif
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189 | 8977f3c1 | bellard | } |
190 | 8977f3c1 | bellard | } else {
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191 | 8977f3c1 | bellard | drv->disk = FDRIVE_DISK_NONE; |
192 | 8977f3c1 | bellard | drv->last_sect = 1; /* Avoid eventual divide by 0 bugs */ |
193 | 8977f3c1 | bellard | } |
194 | 8977f3c1 | bellard | drv->ro = ro; |
195 | 8977f3c1 | bellard | drv->rv = 1;
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196 | 8977f3c1 | bellard | } |
197 | 8977f3c1 | bellard | |
198 | 8977f3c1 | bellard | /* Motor control */
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199 | 8977f3c1 | bellard | static void fd_start (fdrive_t *drv) |
200 | 8977f3c1 | bellard | { |
201 | 8977f3c1 | bellard | drv->motor = 1;
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202 | 8977f3c1 | bellard | } |
203 | 8977f3c1 | bellard | |
204 | 8977f3c1 | bellard | static void fd_stop (fdrive_t *drv) |
205 | 8977f3c1 | bellard | { |
206 | 8977f3c1 | bellard | drv->motor = 0;
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207 | 8977f3c1 | bellard | } |
208 | 8977f3c1 | bellard | |
209 | 8977f3c1 | bellard | /* Re-initialise a drives (motor off, repositioned) */
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210 | 8977f3c1 | bellard | static void fd_reset (fdrive_t *drv) |
211 | 8977f3c1 | bellard | { |
212 | 8977f3c1 | bellard | fd_stop(drv); |
213 | 8977f3c1 | bellard | fd_recalibrate(drv); |
214 | 8977f3c1 | bellard | } |
215 | 8977f3c1 | bellard | |
216 | 8977f3c1 | bellard | /********************************************************/
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217 | 8977f3c1 | bellard | /* Intel 82078 floppy disk controler emulation */
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218 | 8977f3c1 | bellard | |
219 | 8977f3c1 | bellard | static void fdctrl_reset (int do_irq); |
220 | 8977f3c1 | bellard | static void fdctrl_reset_fifo (void); |
221 | 8977f3c1 | bellard | static int fdctrl_transfer_handler (uint32_t addr, int size, int *irq); |
222 | 8977f3c1 | bellard | static int fdctrl_misc_handler (int duknwo); |
223 | 8977f3c1 | bellard | static void fdctrl_raise_irq (uint8_t status); |
224 | 8977f3c1 | bellard | |
225 | 8977f3c1 | bellard | static uint32_t fdctrl_read_statusB (CPUState *env, uint32_t reg);
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226 | 8977f3c1 | bellard | static uint32_t fdctrl_read_dor (CPUState *env, uint32_t reg);
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227 | 8977f3c1 | bellard | static void fdctrl_write_dor (CPUState *env, uint32_t reg, uint32_t value); |
228 | 8977f3c1 | bellard | static uint32_t fdctrl_read_tape (CPUState *env, uint32_t reg);
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229 | 8977f3c1 | bellard | static void fdctrl_write_tape (CPUState *env, uint32_t reg, uint32_t value); |
230 | 8977f3c1 | bellard | static uint32_t fdctrl_read_main_status (CPUState *env, uint32_t reg);
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231 | 8977f3c1 | bellard | static void fdctrl_write_rate (CPUState *env, uint32_t reg, uint32_t value); |
232 | 8977f3c1 | bellard | static uint32_t fdctrl_read_data (CPUState *env, uint32_t reg);
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233 | 8977f3c1 | bellard | static void fdctrl_write_data (CPUState *env, uint32_t reg, uint32_t value); |
234 | 8977f3c1 | bellard | static uint32_t fdctrl_read_dir (CPUState *env, uint32_t reg);
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235 | 8977f3c1 | bellard | |
236 | 8977f3c1 | bellard | enum {
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237 | 8977f3c1 | bellard | FD_CTRL_ACTIVE = 0x01,
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238 | 8977f3c1 | bellard | FD_CTRL_RESET = 0x02,
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239 | 8977f3c1 | bellard | FD_CTRL_SLEEP = 0x04,
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240 | 8977f3c1 | bellard | FD_CTRL_BUSY = 0x08,
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241 | 8977f3c1 | bellard | FD_CTRL_INTR = 0x10,
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242 | 8977f3c1 | bellard | }; |
243 | 8977f3c1 | bellard | |
244 | 8977f3c1 | bellard | enum {
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245 | 8977f3c1 | bellard | FD_DIR_WRITE = 0,
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246 | 8977f3c1 | bellard | FD_DIR_READ = 1,
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247 | 8977f3c1 | bellard | FD_DIR_SCANE = 2,
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248 | 8977f3c1 | bellard | FD_DIR_SCANL = 3,
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249 | 8977f3c1 | bellard | FD_DIR_SCANH = 4,
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250 | 8977f3c1 | bellard | }; |
251 | 8977f3c1 | bellard | |
252 | 8977f3c1 | bellard | enum {
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253 | 8977f3c1 | bellard | FD_STATE_CMD = 0x00,
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254 | 8977f3c1 | bellard | FD_STATE_STATUS = 0x01,
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255 | 8977f3c1 | bellard | FD_STATE_DATA = 0x02,
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256 | 8977f3c1 | bellard | FD_STATE_STATE = 0x03,
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257 | 8977f3c1 | bellard | FD_STATE_MULTI = 0x10,
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258 | 8977f3c1 | bellard | FD_STATE_SEEK = 0x20,
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259 | 8977f3c1 | bellard | }; |
260 | 8977f3c1 | bellard | |
261 | 8977f3c1 | bellard | #define FD_STATE(state) ((state) & FD_STATE_STATE)
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262 | 8977f3c1 | bellard | #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
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263 | 8977f3c1 | bellard | #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
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264 | 8977f3c1 | bellard | |
265 | 8977f3c1 | bellard | typedef struct fdctrl_t { |
266 | 8977f3c1 | bellard | /* Controler's identification */
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267 | 8977f3c1 | bellard | uint8_t version; |
268 | 8977f3c1 | bellard | /* HW */
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269 | 8977f3c1 | bellard | int irq_lvl;
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270 | 8977f3c1 | bellard | int dma_chann;
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271 | 8977f3c1 | bellard | /* Controler state */
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272 | 8977f3c1 | bellard | uint8_t state; |
273 | 8977f3c1 | bellard | uint8_t dma_en; |
274 | 8977f3c1 | bellard | uint8_t cur_drv; |
275 | 8977f3c1 | bellard | uint8_t bootsel; |
276 | 8977f3c1 | bellard | /* Command FIFO */
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277 | 8977f3c1 | bellard | uint8_t fifo[FD_SECTOR_LEN]; |
278 | 8977f3c1 | bellard | uint32_t data_pos; |
279 | 8977f3c1 | bellard | uint32_t data_len; |
280 | 8977f3c1 | bellard | uint8_t data_state; |
281 | 8977f3c1 | bellard | uint8_t data_dir; |
282 | 8977f3c1 | bellard | uint8_t int_status; |
283 | 8977f3c1 | bellard | /* States kept only to be returned back */
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284 | 8977f3c1 | bellard | /* Timers state */
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285 | 8977f3c1 | bellard | uint8_t timer0; |
286 | 8977f3c1 | bellard | uint8_t timer1; |
287 | 8977f3c1 | bellard | /* precompensation */
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288 | 8977f3c1 | bellard | uint8_t precomp_trk; |
289 | 8977f3c1 | bellard | uint8_t config; |
290 | 8977f3c1 | bellard | uint8_t lock; |
291 | 8977f3c1 | bellard | /* Power down config (also with status regB access mode */
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292 | 8977f3c1 | bellard | uint8_t pwrd; |
293 | 8977f3c1 | bellard | /* Floppy drives */
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294 | 8977f3c1 | bellard | fdrive_t drives[2];
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295 | 8977f3c1 | bellard | } fdctrl_t; |
296 | 8977f3c1 | bellard | |
297 | 8977f3c1 | bellard | static fdctrl_t fdctrl;
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298 | 8977f3c1 | bellard | |
299 | 8977f3c1 | bellard | void fdctrl_init (int irq_lvl, int dma_chann, int mem_mapped, uint32_t base, |
300 | 8977f3c1 | bellard | char boot_device)
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301 | 8977f3c1 | bellard | { |
302 | 8977f3c1 | bellard | // int io_mem;
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303 | 8977f3c1 | bellard | int i;
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304 | 8977f3c1 | bellard | |
305 | 8977f3c1 | bellard | FLOPPY_DPRINTF("init controler\n");
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306 | 8977f3c1 | bellard | memset(&fdctrl, 0, sizeof(fdctrl)); |
307 | 8977f3c1 | bellard | fdctrl.version = 0x90; /* Intel 82078 controler */ |
308 | 8977f3c1 | bellard | fdctrl.irq_lvl = irq_lvl; |
309 | 8977f3c1 | bellard | fdctrl.dma_chann = dma_chann; |
310 | 8977f3c1 | bellard | fdctrl.config = 0x40; /* Implicit seek, polling & FIFO enabled */ |
311 | 8977f3c1 | bellard | if (fdctrl.dma_chann != -1) { |
312 | 8977f3c1 | bellard | fdctrl.dma_en = 1;
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313 | 8977f3c1 | bellard | DMA_register_channel(dma_chann, &fdctrl_transfer_handler, |
314 | 8977f3c1 | bellard | &fdctrl_misc_handler); |
315 | 8977f3c1 | bellard | } else {
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316 | 8977f3c1 | bellard | fdctrl.dma_en = 0;
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317 | 8977f3c1 | bellard | } |
318 | 8977f3c1 | bellard | for (i = 0; i < MAX_FD; i++) |
319 | 8977f3c1 | bellard | fd_init(&fdctrl.drives[i]); |
320 | 8977f3c1 | bellard | fdctrl_reset(0);
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321 | 8977f3c1 | bellard | fdctrl.state = FD_CTRL_ACTIVE; |
322 | 8977f3c1 | bellard | if (mem_mapped) {
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323 | 8977f3c1 | bellard | FLOPPY_ERROR("memory mapped floppy not supported by now !\n");
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324 | 8977f3c1 | bellard | #if 0
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325 | 8977f3c1 | bellard | io_mem = cpu_register_io_memory(0, fdctrl_mem_read, fdctrl_mem_write);
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326 | 8977f3c1 | bellard | cpu_register_physical_memory(base, 0x08, io_mem);
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327 | 8977f3c1 | bellard | #endif
|
328 | 8977f3c1 | bellard | } else {
|
329 | 8977f3c1 | bellard | register_ioport_read(base + 0x01, 1, fdctrl_read_statusB, 1); |
330 | 8977f3c1 | bellard | register_ioport_read(base + 0x02, 1, fdctrl_read_dor, 1); |
331 | 8977f3c1 | bellard | register_ioport_write(base + 0x02, 1, fdctrl_write_dor, 1); |
332 | 8977f3c1 | bellard | register_ioport_read(base + 0x03, 1, fdctrl_read_tape, 1); |
333 | 8977f3c1 | bellard | register_ioport_write(base + 0x03, 1, fdctrl_write_tape, 1); |
334 | 8977f3c1 | bellard | register_ioport_read(base + 0x04, 1, fdctrl_read_main_status, 1); |
335 | 8977f3c1 | bellard | register_ioport_write(base + 0x04, 1, fdctrl_write_rate, 1); |
336 | 8977f3c1 | bellard | register_ioport_read(base + 0x05, 1, fdctrl_read_data, 1); |
337 | 8977f3c1 | bellard | register_ioport_write(base + 0x05, 1, fdctrl_write_data, 1); |
338 | 8977f3c1 | bellard | register_ioport_read(base + 0x07, 1, fdctrl_read_dir, 1); |
339 | 8977f3c1 | bellard | } |
340 | 8977f3c1 | bellard | if (boot_device == 'b') |
341 | 8977f3c1 | bellard | fdctrl.bootsel = 1;
|
342 | 8977f3c1 | bellard | else
|
343 | 8977f3c1 | bellard | fdctrl.bootsel = 0;
|
344 | 8977f3c1 | bellard | #if defined (TARGET_I386)
|
345 | 8977f3c1 | bellard | cmos_register_fd(fdctrl.drives[0].drive, fdctrl.drives[1].drive); |
346 | 8977f3c1 | bellard | #endif
|
347 | 8977f3c1 | bellard | } |
348 | 8977f3c1 | bellard | |
349 | 8977f3c1 | bellard | int fdctrl_disk_change (int idx, const unsigned char *filename, int ro) |
350 | 8977f3c1 | bellard | { |
351 | 8977f3c1 | bellard | fdrive_t *drv; |
352 | 8977f3c1 | bellard | |
353 | 8977f3c1 | bellard | if (idx < 0 || idx > 1) |
354 | 8977f3c1 | bellard | return -1; |
355 | 8977f3c1 | bellard | FLOPPY_DPRINTF("disk %d change: %s (%s)\n", idx, filename,
|
356 | 8977f3c1 | bellard | ro == 0 ? "rw" : "ro"); |
357 | 8977f3c1 | bellard | drv = &fdctrl.drives[idx]; |
358 | 8977f3c1 | bellard | if (fd_table[idx] != NULL) { |
359 | 8977f3c1 | bellard | bdrv_close(fd_table[idx]); |
360 | 8977f3c1 | bellard | fd_table[idx] = NULL;
|
361 | 8977f3c1 | bellard | } |
362 | 8977f3c1 | bellard | fd_table[idx] = bdrv_open(filename, ro); |
363 | 8977f3c1 | bellard | drv->bs = fd_table[idx]; |
364 | 8977f3c1 | bellard | if (fd_table[idx] == NULL) |
365 | 8977f3c1 | bellard | return -1; |
366 | 8977f3c1 | bellard | fd_revalidate(drv, ro); |
367 | 8977f3c1 | bellard | #if 0
|
368 | 8977f3c1 | bellard | fd_recalibrate(drv);
|
369 | 8977f3c1 | bellard | fdctrl_reset_fifo();
|
370 | 8977f3c1 | bellard | fdctrl_raise_irq(0x20);
|
371 | 8977f3c1 | bellard | #endif
|
372 | 8977f3c1 | bellard | |
373 | 8977f3c1 | bellard | return 0; |
374 | 8977f3c1 | bellard | } |
375 | 8977f3c1 | bellard | |
376 | 8977f3c1 | bellard | /* Change IRQ state */
|
377 | 8977f3c1 | bellard | static void fdctrl_reset_irq (void) |
378 | 8977f3c1 | bellard | { |
379 | 8977f3c1 | bellard | if (fdctrl.state & FD_CTRL_INTR) {
|
380 | 8977f3c1 | bellard | pic_set_irq(fdctrl.irq_lvl, 0);
|
381 | 8977f3c1 | bellard | fdctrl.state &= ~(FD_CTRL_INTR | FD_CTRL_SLEEP | FD_CTRL_BUSY); |
382 | 8977f3c1 | bellard | } |
383 | 8977f3c1 | bellard | } |
384 | 8977f3c1 | bellard | |
385 | 8977f3c1 | bellard | static void fdctrl_raise_irq (uint8_t status) |
386 | 8977f3c1 | bellard | { |
387 | 8977f3c1 | bellard | if (~(fdctrl.state & FD_CTRL_INTR)) {
|
388 | 8977f3c1 | bellard | pic_set_irq(fdctrl.irq_lvl, 1);
|
389 | 8977f3c1 | bellard | fdctrl.state |= FD_CTRL_INTR; |
390 | 8977f3c1 | bellard | } |
391 | 8977f3c1 | bellard | FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", status);
|
392 | 8977f3c1 | bellard | fdctrl.int_status = status; |
393 | 8977f3c1 | bellard | } |
394 | 8977f3c1 | bellard | |
395 | 8977f3c1 | bellard | /* Reset controler */
|
396 | 8977f3c1 | bellard | static void fdctrl_reset (int do_irq) |
397 | 8977f3c1 | bellard | { |
398 | 8977f3c1 | bellard | int i;
|
399 | 8977f3c1 | bellard | |
400 | 8977f3c1 | bellard | FLOPPY_DPRINTF("reset controler\n");
|
401 | 8977f3c1 | bellard | fdctrl_reset_irq(); |
402 | 8977f3c1 | bellard | /* Initialise controler */
|
403 | 8977f3c1 | bellard | fdctrl.cur_drv = 0;
|
404 | 8977f3c1 | bellard | /* FIFO state */
|
405 | 8977f3c1 | bellard | fdctrl.data_pos = 0;
|
406 | 8977f3c1 | bellard | fdctrl.data_len = 0;
|
407 | 8977f3c1 | bellard | fdctrl.data_state = FD_STATE_CMD; |
408 | 8977f3c1 | bellard | fdctrl.data_dir = FD_DIR_WRITE; |
409 | 8977f3c1 | bellard | for (i = 0; i < MAX_FD; i++) |
410 | 8977f3c1 | bellard | fd_reset(&fdctrl.drives[i]); |
411 | 8977f3c1 | bellard | fdctrl_reset_fifo(); |
412 | 8977f3c1 | bellard | if (do_irq)
|
413 | 8977f3c1 | bellard | fdctrl_raise_irq(0x20);
|
414 | 8977f3c1 | bellard | } |
415 | 8977f3c1 | bellard | |
416 | 8977f3c1 | bellard | /* Status B register : 0x01 (read-only) */
|
417 | 8977f3c1 | bellard | static uint32_t fdctrl_read_statusB (CPUState *env, uint32_t reg)
|
418 | 8977f3c1 | bellard | { |
419 | 8977f3c1 | bellard | fdctrl_reset_irq(); |
420 | 8977f3c1 | bellard | FLOPPY_DPRINTF("status register: 0x00\n");
|
421 | 8977f3c1 | bellard | |
422 | 8977f3c1 | bellard | return 0; |
423 | 8977f3c1 | bellard | } |
424 | 8977f3c1 | bellard | |
425 | 8977f3c1 | bellard | /* Digital output register : 0x02 */
|
426 | 8977f3c1 | bellard | static uint32_t fdctrl_read_dor (CPUState *env, uint32_t reg)
|
427 | 8977f3c1 | bellard | { |
428 | 8977f3c1 | bellard | fdrive_t *cur_drv, *drv0, *drv1; |
429 | 8977f3c1 | bellard | uint32_t retval = 0;
|
430 | 8977f3c1 | bellard | |
431 | 8977f3c1 | bellard | drv0 = &fdctrl.drives[fdctrl.bootsel]; |
432 | 8977f3c1 | bellard | drv1 = &fdctrl.drives[1 - fdctrl.bootsel];
|
433 | 8977f3c1 | bellard | cur_drv = fdctrl.cur_drv == 0 ? drv0 : drv1;
|
434 | 8977f3c1 | bellard | /* Drive motors state indicators */
|
435 | 8977f3c1 | bellard | retval |= drv1->motor << 5;
|
436 | 8977f3c1 | bellard | retval |= drv0->motor << 4;
|
437 | 8977f3c1 | bellard | /* DMA enable */
|
438 | 8977f3c1 | bellard | retval |= fdctrl.dma_en << 3;
|
439 | 8977f3c1 | bellard | /* Reset indicator */
|
440 | 8977f3c1 | bellard | retval |= (fdctrl.state & FD_CTRL_RESET) == 0 ? 0x04 : 0; |
441 | 8977f3c1 | bellard | /* Selected drive */
|
442 | 8977f3c1 | bellard | retval |= fdctrl.cur_drv; |
443 | 8977f3c1 | bellard | FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
|
444 | 8977f3c1 | bellard | |
445 | 8977f3c1 | bellard | return retval;
|
446 | 8977f3c1 | bellard | } |
447 | 8977f3c1 | bellard | |
448 | 8977f3c1 | bellard | static void fdctrl_write_dor (CPUState *env, uint32_t reg, uint32_t value) |
449 | 8977f3c1 | bellard | { |
450 | 8977f3c1 | bellard | fdrive_t *drv0, *drv1; |
451 | 8977f3c1 | bellard | |
452 | 8977f3c1 | bellard | fdctrl_reset_irq(); |
453 | 8977f3c1 | bellard | drv0 = &fdctrl.drives[fdctrl.bootsel]; |
454 | 8977f3c1 | bellard | drv1 = &fdctrl.drives[1 - fdctrl.bootsel];
|
455 | 8977f3c1 | bellard | /* Reset mode */
|
456 | 8977f3c1 | bellard | if (fdctrl.state & FD_CTRL_RESET) {
|
457 | 8977f3c1 | bellard | if (!(value & 0x04)) { |
458 | 8977f3c1 | bellard | FLOPPY_DPRINTF("Floppy controler in RESET state !\n");
|
459 | 8977f3c1 | bellard | return;
|
460 | 8977f3c1 | bellard | } |
461 | 8977f3c1 | bellard | } |
462 | 8977f3c1 | bellard | FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
|
463 | 8977f3c1 | bellard | /* Drive motors state indicators */
|
464 | 8977f3c1 | bellard | if (value & 0x20) |
465 | 8977f3c1 | bellard | fd_start(drv1); |
466 | 8977f3c1 | bellard | else
|
467 | 8977f3c1 | bellard | fd_stop(drv1); |
468 | 8977f3c1 | bellard | if (value & 0x10) |
469 | 8977f3c1 | bellard | fd_start(drv0); |
470 | 8977f3c1 | bellard | else
|
471 | 8977f3c1 | bellard | fd_stop(drv0); |
472 | 8977f3c1 | bellard | /* DMA enable */
|
473 | 8977f3c1 | bellard | #if 0
|
474 | 8977f3c1 | bellard | if (fdctrl.dma_chann != -1)
|
475 | 8977f3c1 | bellard | fdctrl.dma_en = 1 - ((value >> 3) & 1);
|
476 | 8977f3c1 | bellard | #endif
|
477 | 8977f3c1 | bellard | /* Reset */
|
478 | 8977f3c1 | bellard | if (!(value & 0x04)) { |
479 | 8977f3c1 | bellard | if (!(fdctrl.state & FD_CTRL_RESET)) {
|
480 | 8977f3c1 | bellard | FLOPPY_DPRINTF("controler enter RESET state\n");
|
481 | 8977f3c1 | bellard | fdctrl.state |= FD_CTRL_RESET; |
482 | 8977f3c1 | bellard | fdctrl_reset(1);
|
483 | 8977f3c1 | bellard | } |
484 | 8977f3c1 | bellard | } else {
|
485 | 8977f3c1 | bellard | if (fdctrl.state & FD_CTRL_RESET) {
|
486 | 8977f3c1 | bellard | FLOPPY_DPRINTF("controler out of RESET state\n");
|
487 | 8977f3c1 | bellard | fdctrl.state &= ~(FD_CTRL_RESET | FD_CTRL_SLEEP); |
488 | 8977f3c1 | bellard | } |
489 | 8977f3c1 | bellard | } |
490 | 8977f3c1 | bellard | /* Selected drive */
|
491 | 8977f3c1 | bellard | fdctrl.cur_drv = value & 1;
|
492 | 8977f3c1 | bellard | } |
493 | 8977f3c1 | bellard | |
494 | 8977f3c1 | bellard | /* Tape drive register : 0x03 */
|
495 | 8977f3c1 | bellard | static uint32_t fdctrl_read_tape (CPUState *env, uint32_t reg)
|
496 | 8977f3c1 | bellard | { |
497 | 8977f3c1 | bellard | uint32_t retval = 0;
|
498 | 8977f3c1 | bellard | |
499 | 8977f3c1 | bellard | fdctrl_reset_irq(); |
500 | 8977f3c1 | bellard | /* Disk boot selection indicator */
|
501 | 8977f3c1 | bellard | retval |= fdctrl.bootsel << 2;
|
502 | 8977f3c1 | bellard | /* Tape indicators: never allowed */
|
503 | 8977f3c1 | bellard | FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
|
504 | 8977f3c1 | bellard | |
505 | 8977f3c1 | bellard | return retval;
|
506 | 8977f3c1 | bellard | } |
507 | 8977f3c1 | bellard | |
508 | 8977f3c1 | bellard | static void fdctrl_write_tape (CPUState *env, uint32_t reg, uint32_t value) |
509 | 8977f3c1 | bellard | { |
510 | 8977f3c1 | bellard | fdctrl_reset_irq(); |
511 | 8977f3c1 | bellard | /* Reset mode */
|
512 | 8977f3c1 | bellard | if (fdctrl.state & FD_CTRL_RESET) {
|
513 | 8977f3c1 | bellard | FLOPPY_DPRINTF("Floppy controler in RESET state !\n");
|
514 | 8977f3c1 | bellard | return;
|
515 | 8977f3c1 | bellard | } |
516 | 8977f3c1 | bellard | FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
|
517 | 8977f3c1 | bellard | /* Disk boot selection indicator */
|
518 | 8977f3c1 | bellard | fdctrl.bootsel = (value >> 2) & 1; |
519 | 8977f3c1 | bellard | /* Tape indicators: never allow */
|
520 | 8977f3c1 | bellard | } |
521 | 8977f3c1 | bellard | |
522 | 8977f3c1 | bellard | /* Main status register : 0x04 (read) */
|
523 | 8977f3c1 | bellard | static uint32_t fdctrl_read_main_status (CPUState *env, uint32_t reg)
|
524 | 8977f3c1 | bellard | { |
525 | 8977f3c1 | bellard | uint32_t retval = 0;
|
526 | 8977f3c1 | bellard | |
527 | 8977f3c1 | bellard | fdctrl_reset_irq(); |
528 | 8977f3c1 | bellard | fdctrl.state &= ~(FD_CTRL_SLEEP | FD_CTRL_RESET); |
529 | 8977f3c1 | bellard | if (!(fdctrl.state & FD_CTRL_BUSY)) {
|
530 | 8977f3c1 | bellard | /* Data transfer allowed */
|
531 | 8977f3c1 | bellard | retval |= 0x80;
|
532 | 8977f3c1 | bellard | /* Data transfer direction indicator */
|
533 | 8977f3c1 | bellard | if (fdctrl.data_dir == FD_DIR_READ)
|
534 | 8977f3c1 | bellard | retval |= 0x40;
|
535 | 8977f3c1 | bellard | } |
536 | 8977f3c1 | bellard | /* Should handle 0x20 for SPECIFY command */
|
537 | 8977f3c1 | bellard | /* Command busy indicator */
|
538 | 8977f3c1 | bellard | if (FD_STATE(fdctrl.data_state) == FD_STATE_DATA ||
|
539 | 8977f3c1 | bellard | FD_STATE(fdctrl.data_state) == FD_STATE_STATUS) |
540 | 8977f3c1 | bellard | retval |= 0x10;
|
541 | 8977f3c1 | bellard | FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
|
542 | 8977f3c1 | bellard | |
543 | 8977f3c1 | bellard | return retval;
|
544 | 8977f3c1 | bellard | } |
545 | 8977f3c1 | bellard | |
546 | 8977f3c1 | bellard | /* Data select rate register : 0x04 (write) */
|
547 | 8977f3c1 | bellard | static void fdctrl_write_rate (CPUState *env, uint32_t reg, uint32_t value) |
548 | 8977f3c1 | bellard | { |
549 | 8977f3c1 | bellard | fdctrl_reset_irq(); |
550 | 8977f3c1 | bellard | /* Reset mode */
|
551 | 8977f3c1 | bellard | if (fdctrl.state & FD_CTRL_RESET) {
|
552 | 8977f3c1 | bellard | if (reg != 0x2 || !(value & 0x04)) { |
553 | 8977f3c1 | bellard | FLOPPY_DPRINTF("Floppy controler in RESET state !\n");
|
554 | 8977f3c1 | bellard | return;
|
555 | 8977f3c1 | bellard | } |
556 | 8977f3c1 | bellard | } |
557 | 8977f3c1 | bellard | FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
|
558 | 8977f3c1 | bellard | /* Reset: autoclear */
|
559 | 8977f3c1 | bellard | if (value & 0x80) { |
560 | 8977f3c1 | bellard | fdctrl.state |= FD_CTRL_RESET; |
561 | 8977f3c1 | bellard | fdctrl_reset(1);
|
562 | 8977f3c1 | bellard | fdctrl.state &= ~FD_CTRL_RESET; |
563 | 8977f3c1 | bellard | } |
564 | 8977f3c1 | bellard | if (value & 0x40) { |
565 | 8977f3c1 | bellard | fdctrl.state |= FD_CTRL_SLEEP; |
566 | 8977f3c1 | bellard | fdctrl_reset(1);
|
567 | 8977f3c1 | bellard | } |
568 | 8977f3c1 | bellard | // fdctrl.precomp = (value >> 2) & 0x07;
|
569 | 8977f3c1 | bellard | } |
570 | 8977f3c1 | bellard | |
571 | 8977f3c1 | bellard | /* Digital input register : 0x07 (read-only) */
|
572 | 8977f3c1 | bellard | static uint32_t fdctrl_read_dir (CPUState *env, uint32_t reg)
|
573 | 8977f3c1 | bellard | { |
574 | 8977f3c1 | bellard | fdrive_t *drv0, *drv1; |
575 | 8977f3c1 | bellard | uint32_t retval = 0;
|
576 | 8977f3c1 | bellard | |
577 | 8977f3c1 | bellard | fdctrl_reset_irq(); |
578 | 8977f3c1 | bellard | drv0 = &fdctrl.drives[fdctrl.bootsel]; |
579 | 8977f3c1 | bellard | drv1 = &fdctrl.drives[1 - fdctrl.bootsel];
|
580 | 8977f3c1 | bellard | if (drv0->rv || drv1->rv)
|
581 | 8977f3c1 | bellard | retval |= 0x80;
|
582 | 8977f3c1 | bellard | if (retval != 0) |
583 | 8977f3c1 | bellard | FLOPPY_ERROR("Floppy digital input register: 0x%02x\n", retval);
|
584 | 8977f3c1 | bellard | drv0->rv = 0;
|
585 | 8977f3c1 | bellard | drv1->rv = 0;
|
586 | 8977f3c1 | bellard | |
587 | 8977f3c1 | bellard | return retval;
|
588 | 8977f3c1 | bellard | } |
589 | 8977f3c1 | bellard | |
590 | 8977f3c1 | bellard | /* FIFO state control */
|
591 | 8977f3c1 | bellard | static void fdctrl_reset_fifo (void) |
592 | 8977f3c1 | bellard | { |
593 | 8977f3c1 | bellard | fdctrl.data_dir = FD_DIR_WRITE; |
594 | 8977f3c1 | bellard | fdctrl.data_pos = 0;
|
595 | 8977f3c1 | bellard | fdctrl.data_state = FD_STATE_CMD; |
596 | 8977f3c1 | bellard | } |
597 | 8977f3c1 | bellard | |
598 | 8977f3c1 | bellard | /* Set FIFO status for the host to read */
|
599 | 8977f3c1 | bellard | static void fdctrl_set_fifo (int fifo_len, int do_irq) |
600 | 8977f3c1 | bellard | { |
601 | 8977f3c1 | bellard | fdctrl.data_dir = FD_DIR_READ; |
602 | 8977f3c1 | bellard | fdctrl.data_len = fifo_len; |
603 | 8977f3c1 | bellard | fdctrl.data_pos = 0;
|
604 | 8977f3c1 | bellard | fdctrl.data_state = FD_STATE_STATUS; |
605 | 8977f3c1 | bellard | if (do_irq)
|
606 | 8977f3c1 | bellard | fdctrl_raise_irq(0x00);
|
607 | 8977f3c1 | bellard | } |
608 | 8977f3c1 | bellard | |
609 | 8977f3c1 | bellard | /* Set an error: unimplemented/unknown command */
|
610 | 8977f3c1 | bellard | static void fdctrl_unimplemented (void) |
611 | 8977f3c1 | bellard | { |
612 | 8977f3c1 | bellard | #if 0
|
613 | 8977f3c1 | bellard | fdrive_t *cur_drv, *drv0, *drv1;
|
614 | 8977f3c1 | bellard | |
615 | 8977f3c1 | bellard | drv0 = &fdctrl.drives[fdctrl.bootsel];
|
616 | 8977f3c1 | bellard | drv1 = &fdctrl.drives[1 - fdctrl.bootsel];
|
617 | 8977f3c1 | bellard | cur_drv = fdctrl.cur_drv == 0 ? drv0 : drv1;
|
618 | 8977f3c1 | bellard | fdctrl.fifo[0] = 0x60 | (cur_drv->head << 1) | fdctrl.cur_drv;
|
619 | 8977f3c1 | bellard | fdctrl.fifo[1] = 0x00;
|
620 | 8977f3c1 | bellard | fdctrl.fifo[2] = 0x00;
|
621 | 8977f3c1 | bellard | fdctrl_set_fifo(3, 1);
|
622 | 8977f3c1 | bellard | #else
|
623 | 8977f3c1 | bellard | fdctrl_reset_fifo(); |
624 | 8977f3c1 | bellard | #endif
|
625 | 8977f3c1 | bellard | } |
626 | 8977f3c1 | bellard | |
627 | 8977f3c1 | bellard | /* Callback for transfer end (stop or abort) */
|
628 | 8977f3c1 | bellard | static void fdctrl_stop_transfer (uint8_t status0, uint8_t status1, |
629 | 8977f3c1 | bellard | uint8_t status2) |
630 | 8977f3c1 | bellard | { |
631 | 8977f3c1 | bellard | fdrive_t *cur_drv, *drv0, *drv1; |
632 | 8977f3c1 | bellard | |
633 | 8977f3c1 | bellard | drv0 = &fdctrl.drives[fdctrl.bootsel]; |
634 | 8977f3c1 | bellard | drv1 = &fdctrl.drives[1 - fdctrl.bootsel];
|
635 | 8977f3c1 | bellard | cur_drv = fdctrl.cur_drv == 0 ? drv0 : drv1;
|
636 | 8977f3c1 | bellard | FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
|
637 | 8977f3c1 | bellard | status0, status1, status2, |
638 | 8977f3c1 | bellard | status0 | (cur_drv->head << 1) | fdctrl.cur_drv);
|
639 | 8977f3c1 | bellard | fdctrl.fifo[0] = status0 | (cur_drv->head << 1) | fdctrl.cur_drv; |
640 | 8977f3c1 | bellard | fdctrl.fifo[1] = status1;
|
641 | 8977f3c1 | bellard | fdctrl.fifo[2] = status2;
|
642 | 8977f3c1 | bellard | fdctrl.fifo[3] = cur_drv->track;
|
643 | 8977f3c1 | bellard | fdctrl.fifo[4] = cur_drv->head;
|
644 | 8977f3c1 | bellard | fdctrl.fifo[5] = cur_drv->sect;
|
645 | 8977f3c1 | bellard | fdctrl.fifo[6] = FD_SECTOR_SC;
|
646 | 8977f3c1 | bellard | fdctrl.data_dir = FD_DIR_READ; |
647 | 8977f3c1 | bellard | if (fdctrl.state & FD_CTRL_BUSY)
|
648 | 8977f3c1 | bellard | DMA_release_DREQ(fdctrl.dma_chann); |
649 | 8977f3c1 | bellard | fdctrl_set_fifo(7, 1); |
650 | 8977f3c1 | bellard | } |
651 | 8977f3c1 | bellard | |
652 | 8977f3c1 | bellard | /* Prepare a data transfer (either DMA or FIFO) */
|
653 | 8977f3c1 | bellard | static void fdctrl_start_transfer (int direction) |
654 | 8977f3c1 | bellard | { |
655 | 8977f3c1 | bellard | fdrive_t *cur_drv, *drv0, *drv1; |
656 | 8977f3c1 | bellard | uint8_t kh, kt, ks; |
657 | 8977f3c1 | bellard | int did_seek;
|
658 | 8977f3c1 | bellard | |
659 | 8977f3c1 | bellard | drv0 = &fdctrl.drives[fdctrl.bootsel]; |
660 | 8977f3c1 | bellard | drv1 = &fdctrl.drives[1 - fdctrl.bootsel];
|
661 | 8977f3c1 | bellard | fdctrl.cur_drv = fdctrl.fifo[1] & 1; |
662 | 8977f3c1 | bellard | cur_drv = fdctrl.cur_drv == 0 ? drv0 : drv1;
|
663 | 8977f3c1 | bellard | kt = fdctrl.fifo[2];
|
664 | 8977f3c1 | bellard | kh = fdctrl.fifo[3];
|
665 | 8977f3c1 | bellard | ks = fdctrl.fifo[4];
|
666 | 8977f3c1 | bellard | FLOPPY_DPRINTF("Start tranfert at %d %d %02x %02x (%d)\n",
|
667 | 8977f3c1 | bellard | fdctrl.cur_drv, kh, kt, ks, |
668 | 8977f3c1 | bellard | _fd_sector(kh, kt, ks, cur_drv->last_sect)); |
669 | 8977f3c1 | bellard | did_seek = 0;
|
670 | 8977f3c1 | bellard | switch (fd_seek(cur_drv, kh, kt, ks, fdctrl.config & 0x40)) { |
671 | 8977f3c1 | bellard | case 2: |
672 | 8977f3c1 | bellard | /* sect too big */
|
673 | 8977f3c1 | bellard | fdctrl_stop_transfer(0x40, 0x00, 0x00); |
674 | 8977f3c1 | bellard | fdctrl.fifo[3] = kt;
|
675 | 8977f3c1 | bellard | fdctrl.fifo[4] = kh;
|
676 | 8977f3c1 | bellard | fdctrl.fifo[5] = ks;
|
677 | 8977f3c1 | bellard | return;
|
678 | 8977f3c1 | bellard | case 3: |
679 | 8977f3c1 | bellard | /* track too big */
|
680 | 8977f3c1 | bellard | fdctrl_stop_transfer(0x40, 0x80, 0x00); |
681 | 8977f3c1 | bellard | fdctrl.fifo[3] = kt;
|
682 | 8977f3c1 | bellard | fdctrl.fifo[4] = kh;
|
683 | 8977f3c1 | bellard | fdctrl.fifo[5] = ks;
|
684 | 8977f3c1 | bellard | return;
|
685 | 8977f3c1 | bellard | case 4: |
686 | 8977f3c1 | bellard | /* No seek enabled */
|
687 | 8977f3c1 | bellard | fdctrl_stop_transfer(0x40, 0x00, 0x00); |
688 | 8977f3c1 | bellard | fdctrl.fifo[3] = kt;
|
689 | 8977f3c1 | bellard | fdctrl.fifo[4] = kh;
|
690 | 8977f3c1 | bellard | fdctrl.fifo[5] = ks;
|
691 | 8977f3c1 | bellard | return;
|
692 | 8977f3c1 | bellard | case 1: |
693 | 8977f3c1 | bellard | did_seek = 1;
|
694 | 8977f3c1 | bellard | break;
|
695 | 8977f3c1 | bellard | default:
|
696 | 8977f3c1 | bellard | break;
|
697 | 8977f3c1 | bellard | } |
698 | 8977f3c1 | bellard | /* Set the FIFO state */
|
699 | 8977f3c1 | bellard | fdctrl.data_dir = direction; |
700 | 8977f3c1 | bellard | fdctrl.data_pos = 0;
|
701 | 8977f3c1 | bellard | fdctrl.data_state = FD_STATE_DATA; /* FIFO ready for data */
|
702 | 8977f3c1 | bellard | if (fdctrl.fifo[0] & 0x80) |
703 | 8977f3c1 | bellard | fdctrl.data_state |= FD_STATE_MULTI; |
704 | 8977f3c1 | bellard | if (did_seek)
|
705 | 8977f3c1 | bellard | fdctrl.data_state |= FD_STATE_SEEK; |
706 | 8977f3c1 | bellard | if (fdctrl.dma_en) {
|
707 | 8977f3c1 | bellard | int dma_mode;
|
708 | 8977f3c1 | bellard | /* DMA transfer are enabled. Check if DMA channel is well programmed */
|
709 | 8977f3c1 | bellard | dma_mode = DMA_get_channel_mode(fdctrl.dma_chann); |
710 | 8977f3c1 | bellard | dma_mode = (dma_mode >> 2) & 3; |
711 | 8977f3c1 | bellard | FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d)\n", dma_mode, direction,
|
712 | 8977f3c1 | bellard | (128 << fdctrl.fifo[5]) * |
713 | 8977f3c1 | bellard | (cur_drv->last_sect - ks + 1));
|
714 | 8977f3c1 | bellard | if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
|
715 | 8977f3c1 | bellard | direction == FD_DIR_SCANH) && dma_mode == 0) ||
|
716 | 8977f3c1 | bellard | (direction == FD_DIR_WRITE && dma_mode == 2) ||
|
717 | 8977f3c1 | bellard | (direction == FD_DIR_READ && dma_mode == 1)) {
|
718 | 8977f3c1 | bellard | /* No access is allowed until DMA transfer has completed */
|
719 | 8977f3c1 | bellard | fdctrl.state |= FD_CTRL_BUSY; |
720 | 8977f3c1 | bellard | /* Now, we just have to wait for the DMA controler to
|
721 | 8977f3c1 | bellard | * recall us...
|
722 | 8977f3c1 | bellard | */
|
723 | 8977f3c1 | bellard | DMA_hold_DREQ(fdctrl.dma_chann); |
724 | 8977f3c1 | bellard | return;
|
725 | 8977f3c1 | bellard | } |
726 | 8977f3c1 | bellard | } |
727 | 8977f3c1 | bellard | FLOPPY_DPRINTF("start non-DMA transfer\n");
|
728 | 8977f3c1 | bellard | /* IO based transfer: calculate len */
|
729 | 8977f3c1 | bellard | if (fdctrl.fifo[5] == 00) { |
730 | 8977f3c1 | bellard | fdctrl.data_len = fdctrl.fifo[8];
|
731 | 8977f3c1 | bellard | } else {
|
732 | 8977f3c1 | bellard | fdctrl.data_len = 128 << fdctrl.fifo[5]; |
733 | 8977f3c1 | bellard | fdctrl.data_len *= (cur_drv->last_sect - ks + 1);
|
734 | 8977f3c1 | bellard | if (fdctrl.fifo[0] & 0x80) |
735 | 8977f3c1 | bellard | fdctrl.data_len *= 2;
|
736 | 8977f3c1 | bellard | } |
737 | 8977f3c1 | bellard | fdctrl_raise_irq(0x00);
|
738 | 8977f3c1 | bellard | |
739 | 8977f3c1 | bellard | return;
|
740 | 8977f3c1 | bellard | } |
741 | 8977f3c1 | bellard | |
742 | 8977f3c1 | bellard | /* Prepare a transfer of deleted data */
|
743 | 8977f3c1 | bellard | static void fdctrl_start_transfer_del (int direction) |
744 | 8977f3c1 | bellard | { |
745 | 8977f3c1 | bellard | /* We don't handle deleted data,
|
746 | 8977f3c1 | bellard | * so we don't return *ANYTHING*
|
747 | 8977f3c1 | bellard | */
|
748 | 8977f3c1 | bellard | fdctrl_stop_transfer(0x60, 0x00, 0x00); |
749 | 8977f3c1 | bellard | } |
750 | 8977f3c1 | bellard | |
751 | 8977f3c1 | bellard | /* handlers for DMA transfers */
|
752 | 8977f3c1 | bellard | static int fdctrl_transfer_handler (uint32_t addr, int size, int *irq) |
753 | 8977f3c1 | bellard | { |
754 | 8977f3c1 | bellard | fdrive_t *cur_drv, *drv0, *drv1; |
755 | 8977f3c1 | bellard | void *orig;
|
756 | 8977f3c1 | bellard | int len;
|
757 | 8977f3c1 | bellard | uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00; |
758 | 8977f3c1 | bellard | |
759 | 8977f3c1 | bellard | fdctrl_reset_irq(); |
760 | 8977f3c1 | bellard | if (!(fdctrl.state & FD_CTRL_BUSY)) {
|
761 | 8977f3c1 | bellard | FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
|
762 | 8977f3c1 | bellard | return 0; |
763 | 8977f3c1 | bellard | } |
764 | 8977f3c1 | bellard | drv0 = &fdctrl.drives[fdctrl.bootsel]; |
765 | 8977f3c1 | bellard | drv1 = &fdctrl.drives[1 - fdctrl.bootsel];
|
766 | 8977f3c1 | bellard | cur_drv = fdctrl.cur_drv == 0 ? drv0 : drv1;
|
767 | 8977f3c1 | bellard | // *irq = fdctrl.irq_lvl;
|
768 | 8977f3c1 | bellard | *irq = -1;
|
769 | 8977f3c1 | bellard | if (fdctrl.data_dir == FD_DIR_SCANE || fdctrl.data_dir == FD_DIR_SCANL ||
|
770 | 8977f3c1 | bellard | fdctrl.data_dir == FD_DIR_SCANH) |
771 | 8977f3c1 | bellard | status2 = 0x04;
|
772 | 8977f3c1 | bellard | for (fdctrl.data_len = size; fdctrl.data_pos < fdctrl.data_len;
|
773 | 8977f3c1 | bellard | fdctrl.data_pos += len) { |
774 | 8977f3c1 | bellard | len = size - fdctrl.data_pos; |
775 | 8977f3c1 | bellard | if (len > FD_SECTOR_LEN)
|
776 | 8977f3c1 | bellard | len = FD_SECTOR_LEN; |
777 | 8977f3c1 | bellard | FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x %02x "
|
778 | 8977f3c1 | bellard | "(%d-0x%08x)\n", len, size, fdctrl.data_pos,
|
779 | 8977f3c1 | bellard | fdctrl.data_len, fdctrl.cur_drv, cur_drv->head, |
780 | 8977f3c1 | bellard | cur_drv->track, cur_drv->sect, fd_sector(cur_drv), |
781 | 8977f3c1 | bellard | fd_sector(cur_drv) * 512);
|
782 | 8977f3c1 | bellard | if (len < FD_SECTOR_LEN) {
|
783 | 8977f3c1 | bellard | memset(&fdctrl.fifo[FD_SECTOR_LEN - len], 0,
|
784 | 8977f3c1 | bellard | FD_SECTOR_LEN - len - 1);
|
785 | 8977f3c1 | bellard | orig = fdctrl.fifo; |
786 | 8977f3c1 | bellard | } else {
|
787 | 8977f3c1 | bellard | orig = (void *)(addr + fdctrl.data_pos);
|
788 | 8977f3c1 | bellard | } |
789 | 8977f3c1 | bellard | if (fdctrl.data_dir != FD_DIR_WRITE) {
|
790 | 8977f3c1 | bellard | /* READ & SCAN commands */
|
791 | 69e5bc90 | bellard | if (cur_drv->bs == NULL) { |
792 | 69e5bc90 | bellard | fdctrl_stop_transfer(0x40, 0x00, 0x00); |
793 | 69e5bc90 | bellard | goto transfer_error;
|
794 | 69e5bc90 | bellard | } |
795 | 69e5bc90 | bellard | |
796 | 69e5bc90 | bellard | if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), orig, 1) < 0) { |
797 | 8977f3c1 | bellard | FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
|
798 | 8977f3c1 | bellard | fd_sector(cur_drv)); |
799 | 8977f3c1 | bellard | /* Sure, image size is too small... */
|
800 | 8977f3c1 | bellard | memset((void *)(addr + fdctrl.data_pos), 0, FD_SECTOR_LEN); |
801 | 8977f3c1 | bellard | } |
802 | 8977f3c1 | bellard | if (fdctrl.data_dir == FD_DIR_READ) {
|
803 | 8977f3c1 | bellard | if (len < FD_SECTOR_LEN) {
|
804 | 8977f3c1 | bellard | memcpy((void *)(addr + fdctrl.data_pos),
|
805 | 8977f3c1 | bellard | fdctrl.fifo, FD_SECTOR_LEN); |
806 | 8977f3c1 | bellard | } |
807 | 8977f3c1 | bellard | } else {
|
808 | 8977f3c1 | bellard | int ret;
|
809 | 8977f3c1 | bellard | ret = memcmp((void *)(addr + fdctrl.data_pos),
|
810 | 8977f3c1 | bellard | fdctrl.fifo, FD_SECTOR_LEN); |
811 | 8977f3c1 | bellard | if (ret == 0) { |
812 | 8977f3c1 | bellard | status2 = 0x08;
|
813 | 8977f3c1 | bellard | goto end_transfer;
|
814 | 8977f3c1 | bellard | } |
815 | 8977f3c1 | bellard | if ((ret < 0 && fdctrl.data_dir == FD_DIR_SCANL) || |
816 | 8977f3c1 | bellard | (ret > 0 && fdctrl.data_dir == FD_DIR_SCANH)) {
|
817 | 8977f3c1 | bellard | status2 = 0x00;
|
818 | 8977f3c1 | bellard | goto end_transfer;
|
819 | 8977f3c1 | bellard | } |
820 | 8977f3c1 | bellard | } |
821 | 8977f3c1 | bellard | } else {
|
822 | 8977f3c1 | bellard | /* WRITE commands */
|
823 | 8977f3c1 | bellard | if (cur_drv->bs == NULL || |
824 | 8977f3c1 | bellard | bdrv_write(cur_drv->bs, fd_sector(cur_drv), orig, 1) < 0) { |
825 | 8977f3c1 | bellard | FLOPPY_ERROR("writting sector %d\n", fd_sector(cur_drv));
|
826 | 8977f3c1 | bellard | fdctrl_stop_transfer(0x60, 0x00, 0x00); |
827 | 8977f3c1 | bellard | goto transfer_error;
|
828 | 8977f3c1 | bellard | } |
829 | 8977f3c1 | bellard | } |
830 | 8977f3c1 | bellard | if (len == FD_SECTOR_LEN) {
|
831 | 8977f3c1 | bellard | /* Seek to next sector */
|
832 | 8977f3c1 | bellard | if (cur_drv->sect == cur_drv->last_sect) {
|
833 | 8977f3c1 | bellard | if (cur_drv->head == 0) { |
834 | 8977f3c1 | bellard | cur_drv->head = 1;
|
835 | 8977f3c1 | bellard | } else {
|
836 | 8977f3c1 | bellard | cur_drv->track++; |
837 | 8977f3c1 | bellard | cur_drv->head = 0;
|
838 | 8977f3c1 | bellard | } |
839 | 8977f3c1 | bellard | cur_drv->sect = 1;
|
840 | 8977f3c1 | bellard | FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
|
841 | 8977f3c1 | bellard | cur_drv->head, cur_drv->track, cur_drv->sect, |
842 | 8977f3c1 | bellard | fd_sector(cur_drv)); |
843 | 8977f3c1 | bellard | if (cur_drv->head == 0) { |
844 | 8977f3c1 | bellard | FLOPPY_DPRINTF("end transfer\n");
|
845 | 8977f3c1 | bellard | goto end_transfer;
|
846 | 8977f3c1 | bellard | } |
847 | 8977f3c1 | bellard | if (!FD_MULTI_TRACK(fdctrl.data_state)) {
|
848 | 8977f3c1 | bellard | /* Single track read */
|
849 | 8977f3c1 | bellard | FLOPPY_DPRINTF("single track transfert: end transfer\n");
|
850 | 8977f3c1 | bellard | // status1 |= 0x80;
|
851 | 8977f3c1 | bellard | goto end_transfer;
|
852 | 8977f3c1 | bellard | } |
853 | 8977f3c1 | bellard | } else {
|
854 | 8977f3c1 | bellard | cur_drv->sect++; |
855 | 8977f3c1 | bellard | FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
|
856 | 8977f3c1 | bellard | cur_drv->head, cur_drv->track, cur_drv->sect, |
857 | 8977f3c1 | bellard | fd_sector(cur_drv)); |
858 | 8977f3c1 | bellard | } |
859 | 8977f3c1 | bellard | } |
860 | 8977f3c1 | bellard | } |
861 | 8977f3c1 | bellard | end_transfer:
|
862 | 8977f3c1 | bellard | if (fdctrl.data_dir == FD_DIR_SCANE ||
|
863 | 8977f3c1 | bellard | fdctrl.data_dir == FD_DIR_SCANL || |
864 | 8977f3c1 | bellard | fdctrl.data_dir == FD_DIR_SCANH) |
865 | 8977f3c1 | bellard | status2 = 0x08;
|
866 | 8977f3c1 | bellard | if (FD_DID_SEEK(fdctrl.data_state))
|
867 | 8977f3c1 | bellard | status0 |= 0x20;
|
868 | 8977f3c1 | bellard | fdctrl_stop_transfer(status0, status1, status2); |
869 | 8977f3c1 | bellard | transfer_error:
|
870 | 8977f3c1 | bellard | |
871 | 8977f3c1 | bellard | return fdctrl.data_pos;
|
872 | 8977f3c1 | bellard | } |
873 | 8977f3c1 | bellard | |
874 | 8977f3c1 | bellard | /* Unused... */
|
875 | 8977f3c1 | bellard | static int fdctrl_misc_handler (int duknwo) |
876 | 8977f3c1 | bellard | { |
877 | 8977f3c1 | bellard | return -1; |
878 | 8977f3c1 | bellard | } |
879 | 8977f3c1 | bellard | |
880 | 8977f3c1 | bellard | /* Data register : 0x05 */
|
881 | 8977f3c1 | bellard | static uint32_t fdctrl_read_data (CPUState *env, uint32_t reg)
|
882 | 8977f3c1 | bellard | { |
883 | 8977f3c1 | bellard | fdrive_t *cur_drv, *drv0, *drv1; |
884 | 8977f3c1 | bellard | uint32_t retval = 0;
|
885 | 8977f3c1 | bellard | int pos, len;
|
886 | 8977f3c1 | bellard | |
887 | 8977f3c1 | bellard | fdctrl_reset_irq(); |
888 | 8977f3c1 | bellard | drv0 = &fdctrl.drives[fdctrl.bootsel]; |
889 | 8977f3c1 | bellard | drv1 = &fdctrl.drives[1 - fdctrl.bootsel];
|
890 | 8977f3c1 | bellard | cur_drv = fdctrl.cur_drv == 0 ? drv0 : drv1;
|
891 | 8977f3c1 | bellard | fdctrl.state &= ~FD_CTRL_SLEEP; |
892 | 8977f3c1 | bellard | if (FD_STATE(fdctrl.data_state) == FD_STATE_CMD) {
|
893 | 8977f3c1 | bellard | FLOPPY_ERROR("can't read data in CMD state\n");
|
894 | 8977f3c1 | bellard | return 0; |
895 | 8977f3c1 | bellard | } |
896 | 8977f3c1 | bellard | pos = fdctrl.data_pos; |
897 | 8977f3c1 | bellard | if (FD_STATE(fdctrl.data_state) == FD_STATE_DATA) {
|
898 | 8977f3c1 | bellard | pos %= FD_SECTOR_LEN; |
899 | 8977f3c1 | bellard | if (pos == 0) { |
900 | 8977f3c1 | bellard | len = fdctrl.data_len - fdctrl.data_pos; |
901 | 8977f3c1 | bellard | if (len > FD_SECTOR_LEN)
|
902 | 8977f3c1 | bellard | len = FD_SECTOR_LEN; |
903 | 8977f3c1 | bellard | bdrv_read(cur_drv->bs, fd_sector(cur_drv), |
904 | 8977f3c1 | bellard | fdctrl.fifo, len); |
905 | 8977f3c1 | bellard | } |
906 | 8977f3c1 | bellard | } |
907 | 8977f3c1 | bellard | retval = fdctrl.fifo[pos]; |
908 | 8977f3c1 | bellard | if (++fdctrl.data_pos == fdctrl.data_len) {
|
909 | 8977f3c1 | bellard | fdctrl.data_pos = 0;
|
910 | 8977f3c1 | bellard | /* Switch from transfert mode to status mode
|
911 | 8977f3c1 | bellard | * then from status mode to command mode
|
912 | 8977f3c1 | bellard | */
|
913 | 8977f3c1 | bellard | if (FD_STATE(fdctrl.data_state) == FD_STATE_DATA)
|
914 | 8977f3c1 | bellard | fdctrl_stop_transfer(0x20, 0x00, 0x00); |
915 | 8977f3c1 | bellard | else
|
916 | 8977f3c1 | bellard | fdctrl_reset_fifo(); |
917 | 8977f3c1 | bellard | } |
918 | 8977f3c1 | bellard | FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
|
919 | 8977f3c1 | bellard | |
920 | 8977f3c1 | bellard | return retval;
|
921 | 8977f3c1 | bellard | } |
922 | 8977f3c1 | bellard | |
923 | 8977f3c1 | bellard | static void fdctrl_write_data (CPUState *env, uint32_t reg, uint32_t value) |
924 | 8977f3c1 | bellard | { |
925 | 8977f3c1 | bellard | fdrive_t *cur_drv, *drv0, *drv1; |
926 | 8977f3c1 | bellard | |
927 | 8977f3c1 | bellard | fdctrl_reset_irq(); |
928 | 8977f3c1 | bellard | drv0 = &fdctrl.drives[fdctrl.bootsel]; |
929 | 8977f3c1 | bellard | drv1 = &fdctrl.drives[1 - fdctrl.bootsel];
|
930 | 8977f3c1 | bellard | cur_drv = fdctrl.cur_drv == 0 ? drv0 : drv1;
|
931 | 8977f3c1 | bellard | /* Reset mode */
|
932 | 8977f3c1 | bellard | if (fdctrl.state & FD_CTRL_RESET) {
|
933 | 8977f3c1 | bellard | FLOPPY_DPRINTF("Floppy controler in RESET state !\n");
|
934 | 8977f3c1 | bellard | return;
|
935 | 8977f3c1 | bellard | } |
936 | 8977f3c1 | bellard | fdctrl.state &= ~FD_CTRL_SLEEP; |
937 | 8977f3c1 | bellard | if ((fdctrl.data_state & FD_STATE_STATE) == FD_STATE_STATUS) {
|
938 | 8977f3c1 | bellard | FLOPPY_ERROR("can't write data in status mode\n");
|
939 | 8977f3c1 | bellard | return;
|
940 | 8977f3c1 | bellard | } |
941 | 8977f3c1 | bellard | /* Is it write command time ? */
|
942 | 8977f3c1 | bellard | if (FD_STATE(fdctrl.data_state) == FD_STATE_DATA) {
|
943 | 8977f3c1 | bellard | /* FIFO data write */
|
944 | 8977f3c1 | bellard | fdctrl.fifo[fdctrl.data_pos++] = value; |
945 | 8977f3c1 | bellard | if (fdctrl.data_pos % FD_SECTOR_LEN == (FD_SECTOR_LEN - 1) || |
946 | 8977f3c1 | bellard | fdctrl.data_pos == fdctrl.data_len) { |
947 | 8977f3c1 | bellard | bdrv_write(cur_drv->bs, fd_sector(cur_drv), |
948 | 8977f3c1 | bellard | fdctrl.fifo, FD_SECTOR_LEN); |
949 | 8977f3c1 | bellard | } |
950 | 8977f3c1 | bellard | /* Switch from transfert mode to status mode
|
951 | 8977f3c1 | bellard | * then from status mode to command mode
|
952 | 8977f3c1 | bellard | */
|
953 | 8977f3c1 | bellard | if (FD_STATE(fdctrl.data_state) == FD_STATE_DATA)
|
954 | 8977f3c1 | bellard | fdctrl_stop_transfer(0x20, 0x00, 0x00); |
955 | 8977f3c1 | bellard | return;
|
956 | 8977f3c1 | bellard | } |
957 | 8977f3c1 | bellard | if (fdctrl.data_pos == 0) { |
958 | 8977f3c1 | bellard | /* Command */
|
959 | 8977f3c1 | bellard | switch (value & 0x5F) { |
960 | 8977f3c1 | bellard | case 0x46: |
961 | 8977f3c1 | bellard | /* READ variants */
|
962 | 8977f3c1 | bellard | FLOPPY_DPRINTF("READ command\n");
|
963 | 8977f3c1 | bellard | /* 8 parameters cmd */
|
964 | 8977f3c1 | bellard | fdctrl.data_len = 9;
|
965 | 8977f3c1 | bellard | goto enqueue;
|
966 | 8977f3c1 | bellard | case 0x4C: |
967 | 8977f3c1 | bellard | /* READ_DELETED variants */
|
968 | 8977f3c1 | bellard | FLOPPY_DPRINTF("READ_DELETED command\n");
|
969 | 8977f3c1 | bellard | /* 8 parameters cmd */
|
970 | 8977f3c1 | bellard | fdctrl.data_len = 9;
|
971 | 8977f3c1 | bellard | goto enqueue;
|
972 | 8977f3c1 | bellard | case 0x50: |
973 | 8977f3c1 | bellard | /* SCAN_EQUAL variants */
|
974 | 8977f3c1 | bellard | FLOPPY_DPRINTF("SCAN_EQUAL command\n");
|
975 | 8977f3c1 | bellard | /* 8 parameters cmd */
|
976 | 8977f3c1 | bellard | fdctrl.data_len = 9;
|
977 | 8977f3c1 | bellard | goto enqueue;
|
978 | 8977f3c1 | bellard | case 0x56: |
979 | 8977f3c1 | bellard | /* VERIFY variants */
|
980 | 8977f3c1 | bellard | FLOPPY_DPRINTF("VERIFY command\n");
|
981 | 8977f3c1 | bellard | /* 8 parameters cmd */
|
982 | 8977f3c1 | bellard | fdctrl.data_len = 9;
|
983 | 8977f3c1 | bellard | goto enqueue;
|
984 | 8977f3c1 | bellard | case 0x59: |
985 | 8977f3c1 | bellard | /* SCAN_LOW_OR_EQUAL variants */
|
986 | 8977f3c1 | bellard | FLOPPY_DPRINTF("SCAN_LOW_OR_EQUAL command\n");
|
987 | 8977f3c1 | bellard | /* 8 parameters cmd */
|
988 | 8977f3c1 | bellard | fdctrl.data_len = 9;
|
989 | 8977f3c1 | bellard | goto enqueue;
|
990 | 8977f3c1 | bellard | case 0x5D: |
991 | 8977f3c1 | bellard | /* SCAN_HIGH_OR_EQUAL variants */
|
992 | 8977f3c1 | bellard | FLOPPY_DPRINTF("SCAN_HIGH_OR_EQUAL command\n");
|
993 | 8977f3c1 | bellard | /* 8 parameters cmd */
|
994 | 8977f3c1 | bellard | fdctrl.data_len = 9;
|
995 | 8977f3c1 | bellard | goto enqueue;
|
996 | 8977f3c1 | bellard | default:
|
997 | 8977f3c1 | bellard | break;
|
998 | 8977f3c1 | bellard | } |
999 | 8977f3c1 | bellard | switch (value & 0x7F) { |
1000 | 8977f3c1 | bellard | case 0x45: |
1001 | 8977f3c1 | bellard | /* WRITE variants */
|
1002 | 8977f3c1 | bellard | FLOPPY_DPRINTF("WRITE command\n");
|
1003 | 8977f3c1 | bellard | /* 8 parameters cmd */
|
1004 | 8977f3c1 | bellard | fdctrl.data_len = 9;
|
1005 | 8977f3c1 | bellard | goto enqueue;
|
1006 | 8977f3c1 | bellard | case 0x49: |
1007 | 8977f3c1 | bellard | /* WRITE_DELETED variants */
|
1008 | 8977f3c1 | bellard | FLOPPY_DPRINTF("WRITE_DELETED command\n");
|
1009 | 8977f3c1 | bellard | /* 8 parameters cmd */
|
1010 | 8977f3c1 | bellard | fdctrl.data_len = 9;
|
1011 | 8977f3c1 | bellard | goto enqueue;
|
1012 | 8977f3c1 | bellard | default:
|
1013 | 8977f3c1 | bellard | break;
|
1014 | 8977f3c1 | bellard | } |
1015 | 8977f3c1 | bellard | switch (value) {
|
1016 | 8977f3c1 | bellard | case 0x03: |
1017 | 8977f3c1 | bellard | /* SPECIFY */
|
1018 | 8977f3c1 | bellard | FLOPPY_DPRINTF("SPECIFY command\n");
|
1019 | 8977f3c1 | bellard | /* 1 parameter cmd */
|
1020 | 8977f3c1 | bellard | fdctrl.data_len = 3;
|
1021 | 8977f3c1 | bellard | goto enqueue;
|
1022 | 8977f3c1 | bellard | case 0x04: |
1023 | 8977f3c1 | bellard | /* SENSE_DRIVE_STATUS */
|
1024 | 8977f3c1 | bellard | FLOPPY_DPRINTF("SENSE_DRIVE_STATUS command\n");
|
1025 | 8977f3c1 | bellard | /* 1 parameter cmd */
|
1026 | 8977f3c1 | bellard | fdctrl.data_len = 2;
|
1027 | 8977f3c1 | bellard | goto enqueue;
|
1028 | 8977f3c1 | bellard | case 0x07: |
1029 | 8977f3c1 | bellard | /* RECALIBRATE */
|
1030 | 8977f3c1 | bellard | FLOPPY_DPRINTF("RECALIBRATE command\n");
|
1031 | 8977f3c1 | bellard | /* 1 parameter cmd */
|
1032 | 8977f3c1 | bellard | fdctrl.data_len = 2;
|
1033 | 8977f3c1 | bellard | goto enqueue;
|
1034 | 8977f3c1 | bellard | case 0x08: |
1035 | 8977f3c1 | bellard | /* SENSE_INTERRUPT_STATUS */
|
1036 | 8977f3c1 | bellard | FLOPPY_DPRINTF("SENSE_INTERRUPT_STATUS command (%02x)\n",
|
1037 | 8977f3c1 | bellard | fdctrl.int_status); |
1038 | 8977f3c1 | bellard | /* No parameters cmd: returns status if no interrupt */
|
1039 | 8977f3c1 | bellard | fdctrl.fifo[0] =
|
1040 | 8977f3c1 | bellard | fdctrl.int_status | (cur_drv->head << 2) | fdctrl.cur_drv;
|
1041 | 8977f3c1 | bellard | fdctrl.fifo[1] = cur_drv->track;
|
1042 | 8977f3c1 | bellard | fdctrl_set_fifo(2, 0); |
1043 | 8977f3c1 | bellard | return;
|
1044 | 8977f3c1 | bellard | case 0x0E: |
1045 | 8977f3c1 | bellard | /* DUMPREG */
|
1046 | 8977f3c1 | bellard | FLOPPY_DPRINTF("DUMPREG command\n");
|
1047 | 8977f3c1 | bellard | /* Drives position */
|
1048 | 8977f3c1 | bellard | fdctrl.fifo[0] = drv0->track;
|
1049 | 8977f3c1 | bellard | fdctrl.fifo[1] = drv1->track;
|
1050 | 8977f3c1 | bellard | fdctrl.fifo[2] = 0; |
1051 | 8977f3c1 | bellard | fdctrl.fifo[3] = 0; |
1052 | 8977f3c1 | bellard | /* timers */
|
1053 | 8977f3c1 | bellard | fdctrl.fifo[4] = fdctrl.timer0;
|
1054 | 8977f3c1 | bellard | fdctrl.fifo[5] = (fdctrl.timer1 << 1) | fdctrl.dma_en; |
1055 | 8977f3c1 | bellard | fdctrl.fifo[6] = cur_drv->last_sect;
|
1056 | 8977f3c1 | bellard | fdctrl.fifo[7] = (fdctrl.lock << 7) | |
1057 | 8977f3c1 | bellard | (cur_drv->perpendicular << 2);
|
1058 | 8977f3c1 | bellard | fdctrl.fifo[8] = fdctrl.config;
|
1059 | 8977f3c1 | bellard | fdctrl.fifo[9] = fdctrl.precomp_trk;
|
1060 | 8977f3c1 | bellard | fdctrl_set_fifo(10, 0); |
1061 | 8977f3c1 | bellard | return;
|
1062 | 8977f3c1 | bellard | case 0x0F: |
1063 | 8977f3c1 | bellard | /* SEEK */
|
1064 | 8977f3c1 | bellard | FLOPPY_DPRINTF("SEEK command\n");
|
1065 | 8977f3c1 | bellard | /* 2 parameters cmd */
|
1066 | 8977f3c1 | bellard | fdctrl.data_len = 3;
|
1067 | 8977f3c1 | bellard | goto enqueue;
|
1068 | 8977f3c1 | bellard | case 0x10: |
1069 | 8977f3c1 | bellard | /* VERSION */
|
1070 | 8977f3c1 | bellard | FLOPPY_DPRINTF("VERSION command\n");
|
1071 | 8977f3c1 | bellard | /* No parameters cmd */
|
1072 | 8977f3c1 | bellard | /* Controler's version */
|
1073 | 8977f3c1 | bellard | fdctrl.fifo[0] = fdctrl.version;
|
1074 | 8977f3c1 | bellard | fdctrl_set_fifo(1, 1); |
1075 | 8977f3c1 | bellard | return;
|
1076 | 8977f3c1 | bellard | case 0x12: |
1077 | 8977f3c1 | bellard | /* PERPENDICULAR_MODE */
|
1078 | 8977f3c1 | bellard | FLOPPY_DPRINTF("PERPENDICULAR_MODE command\n");
|
1079 | 8977f3c1 | bellard | /* 1 parameter cmd */
|
1080 | 8977f3c1 | bellard | fdctrl.data_len = 2;
|
1081 | 8977f3c1 | bellard | goto enqueue;
|
1082 | 8977f3c1 | bellard | case 0x13: |
1083 | 8977f3c1 | bellard | /* CONFIGURE */
|
1084 | 8977f3c1 | bellard | FLOPPY_DPRINTF("CONFIGURE command\n");
|
1085 | 8977f3c1 | bellard | /* 3 parameters cmd */
|
1086 | 8977f3c1 | bellard | fdctrl.data_len = 4;
|
1087 | 8977f3c1 | bellard | goto enqueue;
|
1088 | 8977f3c1 | bellard | case 0x14: |
1089 | 8977f3c1 | bellard | /* UNLOCK */
|
1090 | 8977f3c1 | bellard | FLOPPY_DPRINTF("UNLOCK command\n");
|
1091 | 8977f3c1 | bellard | /* No parameters cmd */
|
1092 | 8977f3c1 | bellard | fdctrl.lock = 0;
|
1093 | 8977f3c1 | bellard | fdctrl.fifo[0] = 0; |
1094 | 8977f3c1 | bellard | fdctrl_set_fifo(1, 0); |
1095 | 8977f3c1 | bellard | return;
|
1096 | 8977f3c1 | bellard | case 0x17: |
1097 | 8977f3c1 | bellard | /* POWERDOWN_MODE */
|
1098 | 8977f3c1 | bellard | FLOPPY_DPRINTF("POWERDOWN_MODE command\n");
|
1099 | 8977f3c1 | bellard | /* 2 parameters cmd */
|
1100 | 8977f3c1 | bellard | fdctrl.data_len = 3;
|
1101 | 8977f3c1 | bellard | goto enqueue;
|
1102 | 8977f3c1 | bellard | case 0x18: |
1103 | 8977f3c1 | bellard | /* PART_ID */
|
1104 | 8977f3c1 | bellard | FLOPPY_DPRINTF("PART_ID command\n");
|
1105 | 8977f3c1 | bellard | /* No parameters cmd */
|
1106 | 8977f3c1 | bellard | fdctrl.fifo[0] = 0x41; /* Stepping 1 */ |
1107 | 8977f3c1 | bellard | fdctrl_set_fifo(1, 0); |
1108 | 8977f3c1 | bellard | return;
|
1109 | 8977f3c1 | bellard | case 0x2C: |
1110 | 8977f3c1 | bellard | /* SAVE */
|
1111 | 8977f3c1 | bellard | FLOPPY_DPRINTF("SAVE command\n");
|
1112 | 8977f3c1 | bellard | /* No parameters cmd */
|
1113 | 8977f3c1 | bellard | fdctrl.fifo[0] = 0; |
1114 | 8977f3c1 | bellard | fdctrl.fifo[1] = 0; |
1115 | 8977f3c1 | bellard | /* Drives position */
|
1116 | 8977f3c1 | bellard | fdctrl.fifo[2] = drv0->track;
|
1117 | 8977f3c1 | bellard | fdctrl.fifo[3] = drv1->track;
|
1118 | 8977f3c1 | bellard | fdctrl.fifo[4] = 0; |
1119 | 8977f3c1 | bellard | fdctrl.fifo[5] = 0; |
1120 | 8977f3c1 | bellard | /* timers */
|
1121 | 8977f3c1 | bellard | fdctrl.fifo[6] = fdctrl.timer0;
|
1122 | 8977f3c1 | bellard | fdctrl.fifo[7] = fdctrl.timer1;
|
1123 | 8977f3c1 | bellard | fdctrl.fifo[8] = cur_drv->last_sect;
|
1124 | 8977f3c1 | bellard | fdctrl.fifo[9] = (fdctrl.lock << 7) | |
1125 | 8977f3c1 | bellard | (cur_drv->perpendicular << 2);
|
1126 | 8977f3c1 | bellard | fdctrl.fifo[10] = fdctrl.config;
|
1127 | 8977f3c1 | bellard | fdctrl.fifo[11] = fdctrl.precomp_trk;
|
1128 | 8977f3c1 | bellard | fdctrl.fifo[12] = fdctrl.pwrd;
|
1129 | 8977f3c1 | bellard | fdctrl.fifo[13] = 0; |
1130 | 8977f3c1 | bellard | fdctrl.fifo[14] = 0; |
1131 | 8977f3c1 | bellard | fdctrl_set_fifo(15, 1); |
1132 | 8977f3c1 | bellard | return;
|
1133 | 8977f3c1 | bellard | case 0x33: |
1134 | 8977f3c1 | bellard | /* OPTION */
|
1135 | 8977f3c1 | bellard | FLOPPY_DPRINTF("OPTION command\n");
|
1136 | 8977f3c1 | bellard | /* 1 parameter cmd */
|
1137 | 8977f3c1 | bellard | fdctrl.data_len = 2;
|
1138 | 8977f3c1 | bellard | goto enqueue;
|
1139 | 8977f3c1 | bellard | case 0x42: |
1140 | 8977f3c1 | bellard | /* READ_TRACK */
|
1141 | 8977f3c1 | bellard | FLOPPY_DPRINTF("READ_TRACK command\n");
|
1142 | 8977f3c1 | bellard | /* 8 parameters cmd */
|
1143 | 8977f3c1 | bellard | fdctrl.data_len = 9;
|
1144 | 8977f3c1 | bellard | goto enqueue;
|
1145 | 8977f3c1 | bellard | case 0x4A: |
1146 | 8977f3c1 | bellard | /* READ_ID */
|
1147 | 8977f3c1 | bellard | FLOPPY_DPRINTF("READ_ID command\n");
|
1148 | 8977f3c1 | bellard | /* 1 parameter cmd */
|
1149 | 8977f3c1 | bellard | fdctrl.data_len = 2;
|
1150 | 8977f3c1 | bellard | goto enqueue;
|
1151 | 8977f3c1 | bellard | case 0x4C: |
1152 | 8977f3c1 | bellard | /* RESTORE */
|
1153 | 8977f3c1 | bellard | FLOPPY_DPRINTF("RESTORE command\n");
|
1154 | 8977f3c1 | bellard | /* 17 parameters cmd */
|
1155 | 8977f3c1 | bellard | fdctrl.data_len = 18;
|
1156 | 8977f3c1 | bellard | goto enqueue;
|
1157 | 8977f3c1 | bellard | case 0x4D: |
1158 | 8977f3c1 | bellard | /* FORMAT_TRACK */
|
1159 | 8977f3c1 | bellard | FLOPPY_DPRINTF("FORMAT_TRACK command\n");
|
1160 | 8977f3c1 | bellard | /* 5 parameters cmd */
|
1161 | 8977f3c1 | bellard | fdctrl.data_len = 9;
|
1162 | 8977f3c1 | bellard | goto enqueue;
|
1163 | 8977f3c1 | bellard | case 0x8E: |
1164 | 8977f3c1 | bellard | /* DRIVE_SPECIFICATION_COMMAND */
|
1165 | 8977f3c1 | bellard | FLOPPY_DPRINTF("DRIVE_SPECIFICATION_COMMAND command\n");
|
1166 | 8977f3c1 | bellard | /* 5 parameters cmd */
|
1167 | 8977f3c1 | bellard | fdctrl.data_len = 6;
|
1168 | 8977f3c1 | bellard | goto enqueue;
|
1169 | 8977f3c1 | bellard | case 0x8F: |
1170 | 8977f3c1 | bellard | /* RELATIVE_SEEK_OUT */
|
1171 | 8977f3c1 | bellard | FLOPPY_DPRINTF("RELATIVE_SEEK_OUT command\n");
|
1172 | 8977f3c1 | bellard | /* 2 parameters cmd */
|
1173 | 8977f3c1 | bellard | fdctrl.data_len = 3;
|
1174 | 8977f3c1 | bellard | goto enqueue;
|
1175 | 8977f3c1 | bellard | case 0x94: |
1176 | 8977f3c1 | bellard | /* LOCK */
|
1177 | 8977f3c1 | bellard | FLOPPY_DPRINTF("LOCK command\n");
|
1178 | 8977f3c1 | bellard | /* No parameters cmd */
|
1179 | 8977f3c1 | bellard | fdctrl.lock = 1;
|
1180 | 8977f3c1 | bellard | fdctrl.fifo[0] = 0x10; |
1181 | 8977f3c1 | bellard | fdctrl_set_fifo(1, 1); |
1182 | 8977f3c1 | bellard | return;
|
1183 | 8977f3c1 | bellard | case 0xCD: |
1184 | 8977f3c1 | bellard | /* FORMAT_AND_WRITE */
|
1185 | 8977f3c1 | bellard | FLOPPY_DPRINTF("FORMAT_AND_WRITE command\n");
|
1186 | 8977f3c1 | bellard | /* 10 parameters cmd */
|
1187 | 8977f3c1 | bellard | fdctrl.data_len = 11;
|
1188 | 8977f3c1 | bellard | goto enqueue;
|
1189 | 8977f3c1 | bellard | case 0xCF: |
1190 | 8977f3c1 | bellard | /* RELATIVE_SEEK_IN */
|
1191 | 8977f3c1 | bellard | FLOPPY_DPRINTF("RELATIVE_SEEK_IN command\n");
|
1192 | 8977f3c1 | bellard | /* 2 parameters cmd */
|
1193 | 8977f3c1 | bellard | fdctrl.data_len = 3;
|
1194 | 8977f3c1 | bellard | goto enqueue;
|
1195 | 8977f3c1 | bellard | default:
|
1196 | 8977f3c1 | bellard | /* Unknown command */
|
1197 | 8977f3c1 | bellard | FLOPPY_ERROR("unknown command: 0x%02x\n", value);
|
1198 | 8977f3c1 | bellard | fdctrl_unimplemented(); |
1199 | 8977f3c1 | bellard | return;
|
1200 | 8977f3c1 | bellard | } |
1201 | 8977f3c1 | bellard | } |
1202 | 8977f3c1 | bellard | enqueue:
|
1203 | 8977f3c1 | bellard | fdctrl.fifo[fdctrl.data_pos] = value; |
1204 | 8977f3c1 | bellard | if (++fdctrl.data_pos == fdctrl.data_len) {
|
1205 | 8977f3c1 | bellard | /* We now have all parameters
|
1206 | 8977f3c1 | bellard | * and will be able to treat the command
|
1207 | 8977f3c1 | bellard | */
|
1208 | 8977f3c1 | bellard | switch (fdctrl.fifo[0] & 0x1F) { |
1209 | 8977f3c1 | bellard | case 0x06: |
1210 | 8977f3c1 | bellard | { |
1211 | 8977f3c1 | bellard | /* READ variants */
|
1212 | 8977f3c1 | bellard | FLOPPY_DPRINTF("treat READ command\n");
|
1213 | 8977f3c1 | bellard | fdctrl_start_transfer(FD_DIR_READ); |
1214 | 8977f3c1 | bellard | return;
|
1215 | 8977f3c1 | bellard | } |
1216 | 8977f3c1 | bellard | case 0x0C: |
1217 | 8977f3c1 | bellard | /* READ_DELETED variants */
|
1218 | 8977f3c1 | bellard | // FLOPPY_DPRINTF("treat READ_DELETED command\n");
|
1219 | 8977f3c1 | bellard | FLOPPY_ERROR("treat READ_DELETED command\n");
|
1220 | 8977f3c1 | bellard | fdctrl_start_transfer_del(1);
|
1221 | 8977f3c1 | bellard | return;
|
1222 | 8977f3c1 | bellard | case 0x16: |
1223 | 8977f3c1 | bellard | /* VERIFY variants */
|
1224 | 8977f3c1 | bellard | // FLOPPY_DPRINTF("treat VERIFY command\n");
|
1225 | 8977f3c1 | bellard | FLOPPY_ERROR("treat VERIFY command\n");
|
1226 | 8977f3c1 | bellard | fdctrl_stop_transfer(0x20, 0x00, 0x00); |
1227 | 8977f3c1 | bellard | return;
|
1228 | 8977f3c1 | bellard | case 0x10: |
1229 | 8977f3c1 | bellard | /* SCAN_EQUAL variants */
|
1230 | 8977f3c1 | bellard | // FLOPPY_DPRINTF("treat SCAN_EQUAL command\n");
|
1231 | 8977f3c1 | bellard | FLOPPY_ERROR("treat SCAN_EQUAL command\n");
|
1232 | 8977f3c1 | bellard | fdctrl_start_transfer(FD_DIR_SCANE); |
1233 | 8977f3c1 | bellard | return;
|
1234 | 8977f3c1 | bellard | case 0x19: |
1235 | 8977f3c1 | bellard | /* SCAN_LOW_OR_EQUAL variants */
|
1236 | 8977f3c1 | bellard | // FLOPPY_DPRINTF("treat SCAN_LOW_OR_EQUAL command\n");
|
1237 | 8977f3c1 | bellard | FLOPPY_ERROR("treat SCAN_LOW_OR_EQUAL command\n");
|
1238 | 8977f3c1 | bellard | fdctrl_start_transfer(FD_DIR_SCANL); |
1239 | 8977f3c1 | bellard | return;
|
1240 | 8977f3c1 | bellard | case 0x1D: |
1241 | 8977f3c1 | bellard | /* SCAN_HIGH_OR_EQUAL variants */
|
1242 | 8977f3c1 | bellard | // FLOPPY_DPRINTF("treat SCAN_HIGH_OR_EQUAL command\n");
|
1243 | 8977f3c1 | bellard | FLOPPY_ERROR("treat SCAN_HIGH_OR_EQUAL command\n");
|
1244 | 8977f3c1 | bellard | fdctrl_start_transfer(FD_DIR_SCANH); |
1245 | 8977f3c1 | bellard | return;
|
1246 | 8977f3c1 | bellard | default:
|
1247 | 8977f3c1 | bellard | break;
|
1248 | 8977f3c1 | bellard | } |
1249 | 8977f3c1 | bellard | switch (fdctrl.fifo[0] & 0x3F) { |
1250 | 8977f3c1 | bellard | case 0x05: |
1251 | 8977f3c1 | bellard | /* WRITE variants */
|
1252 | 8977f3c1 | bellard | FLOPPY_DPRINTF("treat WRITE command (%02x)\n", fdctrl.fifo[0]); |
1253 | 8977f3c1 | bellard | fdctrl_start_transfer(FD_DIR_WRITE); |
1254 | 8977f3c1 | bellard | return;
|
1255 | 8977f3c1 | bellard | case 0x09: |
1256 | 8977f3c1 | bellard | /* WRITE_DELETED variants */
|
1257 | 8977f3c1 | bellard | // FLOPPY_DPRINTF("treat WRITE_DELETED command\n");
|
1258 | 8977f3c1 | bellard | FLOPPY_ERROR("treat WRITE_DELETED command\n");
|
1259 | 8977f3c1 | bellard | fdctrl_start_transfer_del(FD_DIR_WRITE); |
1260 | 8977f3c1 | bellard | return;
|
1261 | 8977f3c1 | bellard | default:
|
1262 | 8977f3c1 | bellard | break;
|
1263 | 8977f3c1 | bellard | } |
1264 | 8977f3c1 | bellard | switch (fdctrl.fifo[0]) { |
1265 | 8977f3c1 | bellard | case 0x03: |
1266 | 8977f3c1 | bellard | /* SPECIFY */
|
1267 | 8977f3c1 | bellard | FLOPPY_DPRINTF("treat SPECIFY command\n");
|
1268 | 8977f3c1 | bellard | fdctrl.timer0 = (fdctrl.fifo[1] >> 4) & 0xF; |
1269 | 8977f3c1 | bellard | fdctrl.timer1 = fdctrl.fifo[1] >> 1; |
1270 | 8977f3c1 | bellard | /* No result back */
|
1271 | 8977f3c1 | bellard | fdctrl_reset_fifo(); |
1272 | 8977f3c1 | bellard | break;
|
1273 | 8977f3c1 | bellard | case 0x04: |
1274 | 8977f3c1 | bellard | /* SENSE_DRIVE_STATUS */
|
1275 | 8977f3c1 | bellard | FLOPPY_DPRINTF("treat SENSE_DRIVE_STATUS command\n");
|
1276 | 8977f3c1 | bellard | fdctrl.cur_drv = fdctrl.fifo[1] & 1; |
1277 | 8977f3c1 | bellard | cur_drv = fdctrl.cur_drv == 0 ? drv0 : drv1;
|
1278 | 8977f3c1 | bellard | cur_drv->head = (fdctrl.fifo[1] >> 2) & 1; |
1279 | 8977f3c1 | bellard | /* 1 Byte status back */
|
1280 | 8977f3c1 | bellard | fdctrl.fifo[0] = (cur_drv->ro << 6) | |
1281 | 8977f3c1 | bellard | (cur_drv->track == 0 ? 0x10 : 0x00) | |
1282 | 8977f3c1 | bellard | fdctrl.cur_drv; |
1283 | 8977f3c1 | bellard | fdctrl_set_fifo(1, 0); |
1284 | 8977f3c1 | bellard | break;
|
1285 | 8977f3c1 | bellard | case 0x07: |
1286 | 8977f3c1 | bellard | /* RECALIBRATE */
|
1287 | 8977f3c1 | bellard | FLOPPY_DPRINTF("treat RECALIBRATE command\n");
|
1288 | 8977f3c1 | bellard | fdctrl.cur_drv = fdctrl.fifo[1] & 1; |
1289 | 8977f3c1 | bellard | cur_drv = fdctrl.cur_drv == 0 ? drv0 : drv1;
|
1290 | 8977f3c1 | bellard | fd_recalibrate(cur_drv); |
1291 | 8977f3c1 | bellard | fdctrl_reset_fifo(); |
1292 | 8977f3c1 | bellard | /* Raise Interrupt */
|
1293 | 8977f3c1 | bellard | fdctrl_raise_irq(0x20);
|
1294 | 8977f3c1 | bellard | break;
|
1295 | 8977f3c1 | bellard | case 0x0F: |
1296 | 8977f3c1 | bellard | /* SEEK */
|
1297 | 8977f3c1 | bellard | FLOPPY_DPRINTF("treat SEEK command\n");
|
1298 | 8977f3c1 | bellard | fdctrl.cur_drv = fdctrl.fifo[1] & 1; |
1299 | 8977f3c1 | bellard | cur_drv = fdctrl.cur_drv == 0 ? drv0 : drv1;
|
1300 | 8977f3c1 | bellard | if (fdctrl.fifo[2] <= cur_drv->track) |
1301 | 8977f3c1 | bellard | cur_drv->dir = 1;
|
1302 | 8977f3c1 | bellard | else
|
1303 | 8977f3c1 | bellard | cur_drv->dir = 0;
|
1304 | 8977f3c1 | bellard | cur_drv->head = (fdctrl.fifo[1] >> 2) & 1; |
1305 | 8977f3c1 | bellard | if (fdctrl.fifo[2] > cur_drv->max_track) { |
1306 | 8977f3c1 | bellard | fdctrl_raise_irq(0x60);
|
1307 | 8977f3c1 | bellard | } else {
|
1308 | 8977f3c1 | bellard | cur_drv->track = fdctrl.fifo[2];
|
1309 | 8977f3c1 | bellard | fdctrl_reset_fifo(); |
1310 | 8977f3c1 | bellard | /* Raise Interrupt */
|
1311 | 8977f3c1 | bellard | fdctrl_raise_irq(0x20);
|
1312 | 8977f3c1 | bellard | } |
1313 | 8977f3c1 | bellard | break;
|
1314 | 8977f3c1 | bellard | case 0x12: |
1315 | 8977f3c1 | bellard | /* PERPENDICULAR_MODE */
|
1316 | 8977f3c1 | bellard | FLOPPY_DPRINTF("treat PERPENDICULAR_MODE command\n");
|
1317 | 8977f3c1 | bellard | if (fdctrl.fifo[1] & 0x80) |
1318 | 8977f3c1 | bellard | cur_drv->perpendicular = fdctrl.fifo[1] & 0x7; |
1319 | 8977f3c1 | bellard | /* No result back */
|
1320 | 8977f3c1 | bellard | fdctrl_reset_fifo(); |
1321 | 8977f3c1 | bellard | break;
|
1322 | 8977f3c1 | bellard | case 0x13: |
1323 | 8977f3c1 | bellard | /* CONFIGURE */
|
1324 | 8977f3c1 | bellard | FLOPPY_DPRINTF("treat CONFIGURE command\n");
|
1325 | 8977f3c1 | bellard | fdctrl.config = fdctrl.fifo[2];
|
1326 | 8977f3c1 | bellard | fdctrl.precomp_trk = fdctrl.fifo[3];
|
1327 | 8977f3c1 | bellard | /* No result back */
|
1328 | 8977f3c1 | bellard | fdctrl_reset_fifo(); |
1329 | 8977f3c1 | bellard | break;
|
1330 | 8977f3c1 | bellard | case 0x17: |
1331 | 8977f3c1 | bellard | /* POWERDOWN_MODE */
|
1332 | 8977f3c1 | bellard | FLOPPY_DPRINTF("treat POWERDOWN_MODE command\n");
|
1333 | 8977f3c1 | bellard | fdctrl.pwrd = fdctrl.fifo[1];
|
1334 | 8977f3c1 | bellard | fdctrl.fifo[0] = fdctrl.fifo[1]; |
1335 | 8977f3c1 | bellard | fdctrl_set_fifo(1, 1); |
1336 | 8977f3c1 | bellard | break;
|
1337 | 8977f3c1 | bellard | case 0x33: |
1338 | 8977f3c1 | bellard | /* OPTION */
|
1339 | 8977f3c1 | bellard | FLOPPY_DPRINTF("treat OPTION command\n");
|
1340 | 8977f3c1 | bellard | /* No result back */
|
1341 | 8977f3c1 | bellard | fdctrl_reset_fifo(); |
1342 | 8977f3c1 | bellard | break;
|
1343 | 8977f3c1 | bellard | case 0x42: |
1344 | 8977f3c1 | bellard | /* READ_TRACK */
|
1345 | 8977f3c1 | bellard | // FLOPPY_DPRINTF("treat READ_TRACK command\n");
|
1346 | 8977f3c1 | bellard | FLOPPY_ERROR("treat READ_TRACK command\n");
|
1347 | 8977f3c1 | bellard | fdctrl_unimplemented(); |
1348 | 8977f3c1 | bellard | break;
|
1349 | 8977f3c1 | bellard | case 0x4A: |
1350 | 8977f3c1 | bellard | /* READ_ID */
|
1351 | 8977f3c1 | bellard | // FLOPPY_DPRINTF("treat READ_ID command\n");
|
1352 | 8977f3c1 | bellard | FLOPPY_ERROR("treat READ_ID command\n");
|
1353 | 8977f3c1 | bellard | fdctrl_stop_transfer(0x00, 0x00, 0x00); |
1354 | 8977f3c1 | bellard | break;
|
1355 | 8977f3c1 | bellard | case 0x4C: |
1356 | 8977f3c1 | bellard | /* RESTORE */
|
1357 | 8977f3c1 | bellard | FLOPPY_DPRINTF("treat RESTORE command\n");
|
1358 | 8977f3c1 | bellard | /* Drives position */
|
1359 | 8977f3c1 | bellard | drv0->track = fdctrl.fifo[3];
|
1360 | 8977f3c1 | bellard | drv1->track = fdctrl.fifo[4];
|
1361 | 8977f3c1 | bellard | /* timers */
|
1362 | 8977f3c1 | bellard | fdctrl.timer0 = fdctrl.fifo[7];
|
1363 | 8977f3c1 | bellard | fdctrl.timer1 = fdctrl.fifo[8];
|
1364 | 8977f3c1 | bellard | cur_drv->last_sect = fdctrl.fifo[9];
|
1365 | 8977f3c1 | bellard | fdctrl.lock = fdctrl.fifo[10] >> 7; |
1366 | 8977f3c1 | bellard | cur_drv->perpendicular = (fdctrl.fifo[10] >> 2) & 0xF; |
1367 | 8977f3c1 | bellard | fdctrl.config = fdctrl.fifo[11];
|
1368 | 8977f3c1 | bellard | fdctrl.precomp_trk = fdctrl.fifo[12];
|
1369 | 8977f3c1 | bellard | fdctrl.pwrd = fdctrl.fifo[13];
|
1370 | 8977f3c1 | bellard | fdctrl_reset_fifo(); |
1371 | 8977f3c1 | bellard | break;
|
1372 | 8977f3c1 | bellard | case 0x4D: |
1373 | 8977f3c1 | bellard | /* FORMAT_TRACK */
|
1374 | 8977f3c1 | bellard | // FLOPPY_DPRINTF("treat FORMAT_TRACK command\n");
|
1375 | 8977f3c1 | bellard | FLOPPY_ERROR("treat FORMAT_TRACK command\n");
|
1376 | 8977f3c1 | bellard | fdctrl_unimplemented(); |
1377 | 8977f3c1 | bellard | break;
|
1378 | 8977f3c1 | bellard | case 0x8E: |
1379 | 8977f3c1 | bellard | /* DRIVE_SPECIFICATION_COMMAND */
|
1380 | 8977f3c1 | bellard | FLOPPY_DPRINTF("treat DRIVE_SPECIFICATION_COMMAND command\n");
|
1381 | 8977f3c1 | bellard | if (fdctrl.fifo[fdctrl.data_pos - 1] & 0x80) { |
1382 | 8977f3c1 | bellard | /* Command parameters done */
|
1383 | 8977f3c1 | bellard | if (fdctrl.fifo[fdctrl.data_pos - 1] & 0x40) { |
1384 | 8977f3c1 | bellard | fdctrl.fifo[0] = fdctrl.fifo[1]; |
1385 | 8977f3c1 | bellard | fdctrl.fifo[2] = 0; |
1386 | 8977f3c1 | bellard | fdctrl.fifo[3] = 0; |
1387 | 8977f3c1 | bellard | fdctrl_set_fifo(4, 1); |
1388 | 8977f3c1 | bellard | } else {
|
1389 | 8977f3c1 | bellard | fdctrl_reset_fifo(); |
1390 | 8977f3c1 | bellard | } |
1391 | 8977f3c1 | bellard | } else if (fdctrl.data_len > 7) { |
1392 | 8977f3c1 | bellard | /* ERROR */
|
1393 | 8977f3c1 | bellard | fdctrl.fifo[0] = 0x80 | |
1394 | 8977f3c1 | bellard | (cur_drv->head << 2) | fdctrl.cur_drv;
|
1395 | 8977f3c1 | bellard | fdctrl_set_fifo(1, 1); |
1396 | 8977f3c1 | bellard | } |
1397 | 8977f3c1 | bellard | break;
|
1398 | 8977f3c1 | bellard | case 0x8F: |
1399 | 8977f3c1 | bellard | /* RELATIVE_SEEK_OUT */
|
1400 | 8977f3c1 | bellard | FLOPPY_DPRINTF("treat RELATIVE_SEEK_OUT command\n");
|
1401 | 8977f3c1 | bellard | fdctrl.cur_drv = fdctrl.fifo[1] & 1; |
1402 | 8977f3c1 | bellard | cur_drv = fdctrl.cur_drv == 0 ? drv0 : drv1;
|
1403 | 8977f3c1 | bellard | cur_drv->head = (fdctrl.fifo[1] >> 2) & 1; |
1404 | 8977f3c1 | bellard | if (fdctrl.fifo[2] + cur_drv->track > cur_drv->max_track) { |
1405 | 8977f3c1 | bellard | /* ERROR */
|
1406 | 8977f3c1 | bellard | fdctrl_raise_irq(0x70);
|
1407 | 8977f3c1 | bellard | } else {
|
1408 | 8977f3c1 | bellard | cur_drv->track += fdctrl.fifo[2];
|
1409 | 8977f3c1 | bellard | cur_drv->dir = 0;
|
1410 | 8977f3c1 | bellard | fdctrl_reset_fifo(); |
1411 | 8977f3c1 | bellard | fdctrl_raise_irq(0x20);
|
1412 | 8977f3c1 | bellard | } |
1413 | 8977f3c1 | bellard | break;
|
1414 | 8977f3c1 | bellard | case 0xCD: |
1415 | 8977f3c1 | bellard | /* FORMAT_AND_WRITE */
|
1416 | 8977f3c1 | bellard | // FLOPPY_DPRINTF("treat FORMAT_AND_WRITE command\n");
|
1417 | 8977f3c1 | bellard | FLOPPY_ERROR("treat FORMAT_AND_WRITE command\n");
|
1418 | 8977f3c1 | bellard | fdctrl_unimplemented(); |
1419 | 8977f3c1 | bellard | break;
|
1420 | 8977f3c1 | bellard | case 0xCF: |
1421 | 8977f3c1 | bellard | /* RELATIVE_SEEK_IN */
|
1422 | 8977f3c1 | bellard | FLOPPY_DPRINTF("treat RELATIVE_SEEK_IN command\n");
|
1423 | 8977f3c1 | bellard | fdctrl.cur_drv = fdctrl.fifo[1] & 1; |
1424 | 8977f3c1 | bellard | cur_drv = fdctrl.cur_drv == 0 ? drv0 : drv1;
|
1425 | 8977f3c1 | bellard | cur_drv->head = (fdctrl.fifo[1] >> 2) & 1; |
1426 | 8977f3c1 | bellard | if (fdctrl.fifo[2] > cur_drv->track) { |
1427 | 8977f3c1 | bellard | /* ERROR */
|
1428 | 8977f3c1 | bellard | fdctrl_raise_irq(0x60);
|
1429 | 8977f3c1 | bellard | } else {
|
1430 | 8977f3c1 | bellard | fdctrl_reset_fifo(); |
1431 | 8977f3c1 | bellard | cur_drv->track -= fdctrl.fifo[2];
|
1432 | 8977f3c1 | bellard | cur_drv->dir = 1;
|
1433 | 8977f3c1 | bellard | /* Raise Interrupt */
|
1434 | 8977f3c1 | bellard | fdctrl_raise_irq(0x20);
|
1435 | 8977f3c1 | bellard | } |
1436 | 8977f3c1 | bellard | break;
|
1437 | 8977f3c1 | bellard | } |
1438 | 8977f3c1 | bellard | } |
1439 | 8977f3c1 | bellard | } |