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/*
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 * Copyright (C) 2010 Red Hat, Inc.
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 *
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 * written by Gerd Hoffmann <kraxel@redhat.com>
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 or
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 * (at your option) version 3 of the License.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include "hw.h"
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#include "pci.h"
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#include "qemu-timer.h"
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#include "audiodev.h"
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#include "intel-hda.h"
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#include "intel-hda-defs.h"
26

    
27
/* --------------------------------------------------------------------- */
28
/* hda bus                                                               */
29

    
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static struct BusInfo hda_codec_bus_info = {
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    .name      = "HDA",
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    .size      = sizeof(HDACodecBus),
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    .props     = (Property[]) {
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        DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
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        DEFINE_PROP_END_OF_LIST()
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    }
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};
38

    
39
void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus,
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                        hda_codec_response_func response,
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                        hda_codec_xfer_func xfer)
42
{
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    qbus_create_inplace(&bus->qbus, &hda_codec_bus_info, dev, NULL);
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    bus->response = response;
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    bus->xfer = xfer;
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}
47

    
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static int hda_codec_dev_init(DeviceState *qdev, DeviceInfo *base)
49
{
50
    HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus);
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    HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
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    HDACodecDeviceInfo *info = DO_UPCAST(HDACodecDeviceInfo, qdev, base);
53

    
54
    dev->info = info;
55
    if (dev->cad == -1) {
56
        dev->cad = bus->next_cad;
57
    }
58
    if (dev->cad > 15)
59
        return -1;
60
    bus->next_cad = dev->cad + 1;
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    return info->init(dev);
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}
63

    
64
static int hda_codec_dev_exit(DeviceState *qdev)
65
{
66
    HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
67

    
68
    if (dev->info->exit) {
69
        dev->info->exit(dev);
70
    }
71
    return 0;
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}
73

    
74
void hda_codec_register(HDACodecDeviceInfo *info)
75
{
76
    info->qdev.init = hda_codec_dev_init;
77
    info->qdev.exit = hda_codec_dev_exit;
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    info->qdev.bus_info = &hda_codec_bus_info;
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    qdev_register(&info->qdev);
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}
81

    
82
HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
83
{
84
    DeviceState *qdev;
85
    HDACodecDevice *cdev;
86

    
87
    QLIST_FOREACH(qdev, &bus->qbus.children, sibling) {
88
        cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
89
        if (cdev->cad == cad) {
90
            return cdev;
91
        }
92
    }
93
    return NULL;
94
}
95

    
96
void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response)
97
{
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    HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
99
    bus->response(dev, solicited, response);
100
}
101

    
102
bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
103
                    uint8_t *buf, uint32_t len)
104
{
105
    HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
106
    return bus->xfer(dev, stnr, output, buf, len);
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}
108

    
109
/* --------------------------------------------------------------------- */
110
/* intel hda emulation                                                   */
111

    
112
typedef struct IntelHDAStream IntelHDAStream;
113
typedef struct IntelHDAState IntelHDAState;
114
typedef struct IntelHDAReg IntelHDAReg;
115

    
116
typedef struct bpl {
117
    uint64_t addr;
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    uint32_t len;
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    uint32_t flags;
120
} bpl;
121

    
122
struct IntelHDAStream {
123
    /* registers */
124
    uint32_t ctl;
125
    uint32_t lpib;
126
    uint32_t cbl;
127
    uint32_t lvi;
128
    uint32_t fmt;
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    uint32_t bdlp_lbase;
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    uint32_t bdlp_ubase;
131

    
132
    /* state */
133
    bpl      *bpl;
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    uint32_t bentries;
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    uint32_t bsize, be, bp;
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};
137

    
138
struct IntelHDAState {
139
    PCIDevice pci;
140
    const char *name;
141
    HDACodecBus codecs;
142

    
143
    /* registers */
144
    uint32_t g_ctl;
145
    uint32_t wake_en;
146
    uint32_t state_sts;
147
    uint32_t int_ctl;
148
    uint32_t int_sts;
149
    uint32_t wall_clk;
150

    
151
    uint32_t corb_lbase;
152
    uint32_t corb_ubase;
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    uint32_t corb_rp;
154
    uint32_t corb_wp;
155
    uint32_t corb_ctl;
156
    uint32_t corb_sts;
157
    uint32_t corb_size;
158

    
159
    uint32_t rirb_lbase;
160
    uint32_t rirb_ubase;
161
    uint32_t rirb_wp;
162
    uint32_t rirb_cnt;
163
    uint32_t rirb_ctl;
164
    uint32_t rirb_sts;
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    uint32_t rirb_size;
166

    
167
    uint32_t dp_lbase;
168
    uint32_t dp_ubase;
169

    
170
    uint32_t icw;
171
    uint32_t irr;
172
    uint32_t ics;
173

    
174
    /* streams */
175
    IntelHDAStream st[8];
176

    
177
    /* state */
178
    int mmio_addr;
179
    uint32_t rirb_count;
180
    int64_t wall_base_ns;
181

    
182
    /* debug logging */
183
    const IntelHDAReg *last_reg;
184
    uint32_t last_val;
185
    uint32_t last_write;
186
    uint32_t last_sec;
187
    uint32_t repeat_count;
188

    
189
    /* properties */
190
    uint32_t debug;
191
};
192

    
193
struct IntelHDAReg {
194
    const char *name;      /* register name */
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    uint32_t   size;       /* size in bytes */
196
    uint32_t   reset;      /* reset value */
197
    uint32_t   wmask;      /* write mask */
198
    uint32_t   wclear;     /* write 1 to clear bits */
199
    uint32_t   offset;     /* location in IntelHDAState */
200
    uint32_t   shift;      /* byte access entries for dwords */
201
    uint32_t   stream;
202
    void       (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
203
    void       (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
204
};
205

    
206
static void intel_hda_reset(DeviceState *dev);
207

    
208
/* --------------------------------------------------------------------- */
209

    
210
static target_phys_addr_t intel_hda_addr(uint32_t lbase, uint32_t ubase)
211
{
212
    target_phys_addr_t addr;
213

    
214
#if TARGET_PHYS_ADDR_BITS == 32
215
    addr = lbase;
216
#else
217
    addr = ubase;
218
    addr <<= 32;
219
    addr |= lbase;
220
#endif
221
    return addr;
222
}
223

    
224
static void stl_phys_le(target_phys_addr_t addr, uint32_t value)
225
{
226
    uint32_t value_le = cpu_to_le32(value);
227
    cpu_physical_memory_write(addr, (uint8_t*)(&value_le), sizeof(value_le));
228
}
229

    
230
static uint32_t ldl_phys_le(target_phys_addr_t addr)
231
{
232
    uint32_t value_le;
233
    cpu_physical_memory_read(addr, (uint8_t*)(&value_le), sizeof(value_le));
234
    return le32_to_cpu(value_le);
235
}
236

    
237
static void intel_hda_update_int_sts(IntelHDAState *d)
238
{
239
    uint32_t sts = 0;
240
    uint32_t i;
241

    
242
    /* update controller status */
243
    if (d->rirb_sts & ICH6_RBSTS_IRQ) {
244
        sts |= (1 << 30);
245
    }
246
    if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
247
        sts |= (1 << 30);
248
    }
249
    if (d->state_sts & d->wake_en) {
250
        sts |= (1 << 30);
251
    }
252

    
253
    /* update stream status */
254
    for (i = 0; i < 8; i++) {
255
        /* buffer completion interrupt */
256
        if (d->st[i].ctl & (1 << 26)) {
257
            sts |= (1 << i);
258
        }
259
    }
260

    
261
    /* update global status */
262
    if (sts & d->int_ctl) {
263
        sts |= (1 << 31);
264
    }
265

    
266
    d->int_sts = sts;
267
}
268

    
269
static void intel_hda_update_irq(IntelHDAState *d)
270
{
271
    int level;
272

    
273
    intel_hda_update_int_sts(d);
274
    if (d->int_sts & (1 << 31) && d->int_ctl & (1 << 31)) {
275
        level = 1;
276
    } else {
277
        level = 0;
278
    }
279
    dprint(d, 2, "%s: level %d\n", __FUNCTION__, level);
280
    qemu_set_irq(d->pci.irq[0], level);
281
}
282

    
283
static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
284
{
285
    uint32_t cad, nid, data;
286
    HDACodecDevice *codec;
287

    
288
    cad = (verb >> 28) & 0x0f;
289
    if (verb & (1 << 27)) {
290
        /* indirect node addressing, not specified in HDA 1.0 */
291
        dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__);
292
        return -1;
293
    }
294
    nid = (verb >> 20) & 0x7f;
295
    data = verb & 0xfffff;
296

    
297
    codec = hda_codec_find(&d->codecs, cad);
298
    if (codec == NULL) {
299
        dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__);
300
        return -1;
301
    }
302
    codec->info->command(codec, nid, data);
303
    return 0;
304
}
305

    
306
static void intel_hda_corb_run(IntelHDAState *d)
307
{
308
    target_phys_addr_t addr;
309
    uint32_t rp, verb;
310

    
311
    if (d->ics & ICH6_IRS_BUSY) {
312
        dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw);
313
        intel_hda_send_command(d, d->icw);
314
        return;
315
    }
316

    
317
    for (;;) {
318
        if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
319
            dprint(d, 2, "%s: !run\n", __FUNCTION__);
320
            return;
321
        }
322
        if ((d->corb_rp & 0xff) == d->corb_wp) {
323
            dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__);
324
            return;
325
        }
326
        if (d->rirb_count == d->rirb_cnt) {
327
            dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__);
328
            return;
329
        }
330

    
331
        rp = (d->corb_rp + 1) & 0xff;
332
        addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
333
        verb = ldl_phys_le(addr + 4*rp);
334
        d->corb_rp = rp;
335

    
336
        dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb);
337
        intel_hda_send_command(d, verb);
338
    }
339
}
340

    
341
static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
342
{
343
    HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
344
    IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
345
    target_phys_addr_t addr;
346
    uint32_t wp, ex;
347

    
348
    if (d->ics & ICH6_IRS_BUSY) {
349
        dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
350
               __FUNCTION__, response, dev->cad);
351
        d->irr = response;
352
        d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
353
        d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
354
        return;
355
    }
356

    
357
    if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
358
        dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__);
359
        return;
360
    }
361

    
362
    ex = (solicited ? 0 : (1 << 4)) | dev->cad;
363
    wp = (d->rirb_wp + 1) & 0xff;
364
    addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
365
    stl_phys_le(addr + 8*wp, response);
366
    stl_phys_le(addr + 8*wp + 4, ex);
367
    d->rirb_wp = wp;
368

    
369
    dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
370
           __FUNCTION__, wp, response, ex);
371

    
372
    d->rirb_count++;
373
    if (d->rirb_count == d->rirb_cnt) {
374
        dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count);
375
        if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
376
            d->rirb_sts |= ICH6_RBSTS_IRQ;
377
            intel_hda_update_irq(d);
378
        }
379
    } else if ((d->corb_rp & 0xff) == d->corb_wp) {
380
        dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__,
381
               d->rirb_count, d->rirb_cnt);
382
        if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
383
            d->rirb_sts |= ICH6_RBSTS_IRQ;
384
            intel_hda_update_irq(d);
385
        }
386
    }
387
}
388

    
389
static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
390
                           uint8_t *buf, uint32_t len)
391
{
392
    HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
393
    IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
394
    IntelHDAStream *st = NULL;
395
    target_phys_addr_t addr;
396
    uint32_t s, copy, left;
397
    bool irq = false;
398

    
399
    for (s = 0; s < ARRAY_SIZE(d->st); s++) {
400
        if (stnr == ((d->st[s].ctl >> 20) & 0x0f)) {
401
            st = d->st + s;
402
            break;
403
        }
404
    }
405
    if (st == NULL) {
406
        return false;
407
    }
408
    if (st->bpl == NULL) {
409
        return false;
410
    }
411
    if (st->ctl & (1 << 26)) {
412
        /*
413
         * Wait with the next DMA xfer until the guest
414
         * has acked the buffer completion interrupt
415
         */
416
        return false;
417
    }
418

    
419
    left = len;
420
    while (left > 0) {
421
        copy = left;
422
        if (copy > st->bsize - st->lpib)
423
            copy = st->bsize - st->lpib;
424
        if (copy > st->bpl[st->be].len - st->bp)
425
            copy = st->bpl[st->be].len - st->bp;
426

    
427
        dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n",
428
               st->be, st->bp, st->bpl[st->be].len, copy);
429

    
430
        cpu_physical_memory_rw(st->bpl[st->be].addr + st->bp,
431
                               buf, copy, !output);
432
        st->lpib += copy;
433
        st->bp += copy;
434
        buf += copy;
435
        left -= copy;
436

    
437
        if (st->bpl[st->be].len == st->bp) {
438
            /* bpl entry filled */
439
            if (st->bpl[st->be].flags & 0x01) {
440
                irq = true;
441
            }
442
            st->bp = 0;
443
            st->be++;
444
            if (st->be == st->bentries) {
445
                /* bpl wrap around */
446
                st->be = 0;
447
                st->lpib = 0;
448
            }
449
        }
450
    }
451
    if (d->dp_lbase & 0x01) {
452
        addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
453
        stl_phys_le(addr + 8*s, st->lpib);
454
    }
455
    dprint(d, 3, "dma: --\n");
456

    
457
    if (irq) {
458
        st->ctl |= (1 << 26); /* buffer completion interrupt */
459
        intel_hda_update_irq(d);
460
    }
461
    return true;
462
}
463

    
464
static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
465
{
466
    target_phys_addr_t addr;
467
    uint8_t buf[16];
468
    uint32_t i;
469

    
470
    addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
471
    st->bentries = st->lvi +1;
472
    qemu_free(st->bpl);
473
    st->bpl = qemu_malloc(sizeof(bpl) * st->bentries);
474
    for (i = 0; i < st->bentries; i++, addr += 16) {
475
        cpu_physical_memory_read(addr, buf, 16);
476
        st->bpl[i].addr  = le64_to_cpu(*(uint64_t *)buf);
477
        st->bpl[i].len   = le32_to_cpu(*(uint32_t *)(buf + 8));
478
        st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
479
        dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n",
480
               i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags);
481
    }
482

    
483
    st->bsize = st->cbl;
484
    st->lpib  = 0;
485
    st->be    = 0;
486
    st->bp    = 0;
487
}
488

    
489
static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running)
490
{
491
    DeviceState *qdev;
492
    HDACodecDevice *cdev;
493

    
494
    QLIST_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
495
        cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
496
        if (cdev->info->stream) {
497
            cdev->info->stream(cdev, stream, running);
498
        }
499
    }
500
}
501

    
502
/* --------------------------------------------------------------------- */
503

    
504
static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
505
{
506
    if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
507
        intel_hda_reset(&d->pci.qdev);
508
    }
509
}
510

    
511
static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
512
{
513
    intel_hda_update_irq(d);
514
}
515

    
516
static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
517
{
518
    intel_hda_update_irq(d);
519
}
520

    
521
static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
522
{
523
    intel_hda_update_irq(d);
524
}
525

    
526
static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
527
{
528
    int64_t ns;
529

    
530
    ns = qemu_get_clock_ns(vm_clock) - d->wall_base_ns;
531
    d->wall_clk = (uint32_t)(ns * 24 / 1000);  /* 24 MHz */
532
}
533

    
534
static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
535
{
536
    intel_hda_corb_run(d);
537
}
538

    
539
static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
540
{
541
    intel_hda_corb_run(d);
542
}
543

    
544
static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
545
{
546
    if (d->rirb_wp & ICH6_RIRBWP_RST) {
547
        d->rirb_wp = 0;
548
    }
549
}
550

    
551
static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
552
{
553
    intel_hda_update_irq(d);
554

    
555
    if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
556
        /* cleared ICH6_RBSTS_IRQ */
557
        d->rirb_count = 0;
558
        intel_hda_corb_run(d);
559
    }
560
}
561

    
562
static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
563
{
564
    if (d->ics & ICH6_IRS_BUSY) {
565
        intel_hda_corb_run(d);
566
    }
567
}
568

    
569
static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
570
{
571
    IntelHDAStream *st = d->st + reg->stream;
572

    
573
    if (st->ctl & 0x01) {
574
        /* reset */
575
        dprint(d, 1, "st #%d: reset\n", reg->stream);
576
        st->ctl = 0;
577
    }
578
    if ((st->ctl & 0x02) != (old & 0x02)) {
579
        uint32_t stnr = (st->ctl >> 20) & 0x0f;
580
        /* run bit flipped */
581
        if (st->ctl & 0x02) {
582
            /* start */
583
            dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",
584
                   reg->stream, stnr, st->cbl);
585
            intel_hda_parse_bdl(d, st);
586
            intel_hda_notify_codecs(d, stnr, true);
587
        } else {
588
            /* stop */
589
            dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);
590
            intel_hda_notify_codecs(d, stnr, false);
591
        }
592
    }
593
    intel_hda_update_irq(d);
594
}
595

    
596
/* --------------------------------------------------------------------- */
597

    
598
#define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
599

    
600
static const struct IntelHDAReg regtab[] = {
601
    /* global */
602
    [ ICH6_REG_GCAP ] = {
603
        .name     = "GCAP",
604
        .size     = 2,
605
        .reset    = 0x4401,
606
    },
607
    [ ICH6_REG_VMIN ] = {
608
        .name     = "VMIN",
609
        .size     = 1,
610
    },
611
    [ ICH6_REG_VMAJ ] = {
612
        .name     = "VMAJ",
613
        .size     = 1,
614
        .reset    = 1,
615
    },
616
    [ ICH6_REG_OUTPAY ] = {
617
        .name     = "OUTPAY",
618
        .size     = 2,
619
        .reset    = 0x3c,
620
    },
621
    [ ICH6_REG_INPAY ] = {
622
        .name     = "INPAY",
623
        .size     = 2,
624
        .reset    = 0x1d,
625
    },
626
    [ ICH6_REG_GCTL ] = {
627
        .name     = "GCTL",
628
        .size     = 4,
629
        .wmask    = 0x0103,
630
        .offset   = offsetof(IntelHDAState, g_ctl),
631
        .whandler = intel_hda_set_g_ctl,
632
    },
633
    [ ICH6_REG_WAKEEN ] = {
634
        .name     = "WAKEEN",
635
        .size     = 2,
636
        .wmask    = 0x3fff,
637
        .offset   = offsetof(IntelHDAState, wake_en),
638
        .whandler = intel_hda_set_wake_en,
639
    },
640
    [ ICH6_REG_STATESTS ] = {
641
        .name     = "STATESTS",
642
        .size     = 2,
643
        .wmask    = 0x3fff,
644
        .wclear   = 0x3fff,
645
        .offset   = offsetof(IntelHDAState, state_sts),
646
        .whandler = intel_hda_set_state_sts,
647
    },
648

    
649
    /* interrupts */
650
    [ ICH6_REG_INTCTL ] = {
651
        .name     = "INTCTL",
652
        .size     = 4,
653
        .wmask    = 0xc00000ff,
654
        .offset   = offsetof(IntelHDAState, int_ctl),
655
        .whandler = intel_hda_set_int_ctl,
656
    },
657
    [ ICH6_REG_INTSTS ] = {
658
        .name     = "INTSTS",
659
        .size     = 4,
660
        .wmask    = 0xc00000ff,
661
        .wclear   = 0xc00000ff,
662
        .offset   = offsetof(IntelHDAState, int_sts),
663
    },
664

    
665
    /* misc */
666
    [ ICH6_REG_WALLCLK ] = {
667
        .name     = "WALLCLK",
668
        .size     = 4,
669
        .offset   = offsetof(IntelHDAState, wall_clk),
670
        .rhandler = intel_hda_get_wall_clk,
671
    },
672
    [ ICH6_REG_WALLCLK + 0x2000 ] = {
673
        .name     = "WALLCLK(alias)",
674
        .size     = 4,
675
        .offset   = offsetof(IntelHDAState, wall_clk),
676
        .rhandler = intel_hda_get_wall_clk,
677
    },
678

    
679
    /* dma engine */
680
    [ ICH6_REG_CORBLBASE ] = {
681
        .name     = "CORBLBASE",
682
        .size     = 4,
683
        .wmask    = 0xffffff80,
684
        .offset   = offsetof(IntelHDAState, corb_lbase),
685
    },
686
    [ ICH6_REG_CORBUBASE ] = {
687
        .name     = "CORBUBASE",
688
        .size     = 4,
689
        .wmask    = 0xffffffff,
690
        .offset   = offsetof(IntelHDAState, corb_ubase),
691
    },
692
    [ ICH6_REG_CORBWP ] = {
693
        .name     = "CORBWP",
694
        .size     = 2,
695
        .wmask    = 0xff,
696
        .offset   = offsetof(IntelHDAState, corb_wp),
697
        .whandler = intel_hda_set_corb_wp,
698
    },
699
    [ ICH6_REG_CORBRP ] = {
700
        .name     = "CORBRP",
701
        .size     = 2,
702
        .wmask    = 0x80ff,
703
        .offset   = offsetof(IntelHDAState, corb_rp),
704
    },
705
    [ ICH6_REG_CORBCTL ] = {
706
        .name     = "CORBCTL",
707
        .size     = 1,
708
        .wmask    = 0x03,
709
        .offset   = offsetof(IntelHDAState, corb_ctl),
710
        .whandler = intel_hda_set_corb_ctl,
711
    },
712
    [ ICH6_REG_CORBSTS ] = {
713
        .name     = "CORBSTS",
714
        .size     = 1,
715
        .wmask    = 0x01,
716
        .wclear   = 0x01,
717
        .offset   = offsetof(IntelHDAState, corb_sts),
718
    },
719
    [ ICH6_REG_CORBSIZE ] = {
720
        .name     = "CORBSIZE",
721
        .size     = 1,
722
        .reset    = 0x42,
723
        .offset   = offsetof(IntelHDAState, corb_size),
724
    },
725
    [ ICH6_REG_RIRBLBASE ] = {
726
        .name     = "RIRBLBASE",
727
        .size     = 4,
728
        .wmask    = 0xffffff80,
729
        .offset   = offsetof(IntelHDAState, rirb_lbase),
730
    },
731
    [ ICH6_REG_RIRBUBASE ] = {
732
        .name     = "RIRBUBASE",
733
        .size     = 4,
734
        .wmask    = 0xffffffff,
735
        .offset   = offsetof(IntelHDAState, rirb_ubase),
736
    },
737
    [ ICH6_REG_RIRBWP ] = {
738
        .name     = "RIRBWP",
739
        .size     = 2,
740
        .wmask    = 0x8000,
741
        .offset   = offsetof(IntelHDAState, rirb_wp),
742
        .whandler = intel_hda_set_rirb_wp,
743
    },
744
    [ ICH6_REG_RINTCNT ] = {
745
        .name     = "RINTCNT",
746
        .size     = 2,
747
        .wmask    = 0xff,
748
        .offset   = offsetof(IntelHDAState, rirb_cnt),
749
    },
750
    [ ICH6_REG_RIRBCTL ] = {
751
        .name     = "RIRBCTL",
752
        .size     = 1,
753
        .wmask    = 0x07,
754
        .offset   = offsetof(IntelHDAState, rirb_ctl),
755
    },
756
    [ ICH6_REG_RIRBSTS ] = {
757
        .name     = "RIRBSTS",
758
        .size     = 1,
759
        .wmask    = 0x05,
760
        .wclear   = 0x05,
761
        .offset   = offsetof(IntelHDAState, rirb_sts),
762
        .whandler = intel_hda_set_rirb_sts,
763
    },
764
    [ ICH6_REG_RIRBSIZE ] = {
765
        .name     = "RIRBSIZE",
766
        .size     = 1,
767
        .reset    = 0x42,
768
        .offset   = offsetof(IntelHDAState, rirb_size),
769
    },
770

    
771
    [ ICH6_REG_DPLBASE ] = {
772
        .name     = "DPLBASE",
773
        .size     = 4,
774
        .wmask    = 0xffffff81,
775
        .offset   = offsetof(IntelHDAState, dp_lbase),
776
    },
777
    [ ICH6_REG_DPUBASE ] = {
778
        .name     = "DPUBASE",
779
        .size     = 4,
780
        .wmask    = 0xffffffff,
781
        .offset   = offsetof(IntelHDAState, dp_ubase),
782
    },
783

    
784
    [ ICH6_REG_IC ] = {
785
        .name     = "ICW",
786
        .size     = 4,
787
        .wmask    = 0xffffffff,
788
        .offset   = offsetof(IntelHDAState, icw),
789
    },
790
    [ ICH6_REG_IR ] = {
791
        .name     = "IRR",
792
        .size     = 4,
793
        .offset   = offsetof(IntelHDAState, irr),
794
    },
795
    [ ICH6_REG_IRS ] = {
796
        .name     = "ICS",
797
        .size     = 2,
798
        .wmask    = 0x0003,
799
        .wclear   = 0x0002,
800
        .offset   = offsetof(IntelHDAState, ics),
801
        .whandler = intel_hda_set_ics,
802
    },
803

    
804
#define HDA_STREAM(_t, _i)                                            \
805
    [ ST_REG(_i, ICH6_REG_SD_CTL) ] = {                               \
806
        .stream   = _i,                                               \
807
        .name     = _t stringify(_i) " CTL",                          \
808
        .size     = 4,                                                \
809
        .wmask    = 0x1cff001f,                                       \
810
        .offset   = offsetof(IntelHDAState, st[_i].ctl),              \
811
        .whandler = intel_hda_set_st_ctl,                             \
812
    },                                                                \
813
    [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = {                            \
814
        .stream   = _i,                                               \
815
        .name     = _t stringify(_i) " CTL(stnr)",                    \
816
        .size     = 1,                                                \
817
        .shift    = 16,                                               \
818
        .wmask    = 0x00ff0000,                                       \
819
        .offset   = offsetof(IntelHDAState, st[_i].ctl),              \
820
        .whandler = intel_hda_set_st_ctl,                             \
821
    },                                                                \
822
    [ ST_REG(_i, ICH6_REG_SD_STS)] = {                                \
823
        .stream   = _i,                                               \
824
        .name     = _t stringify(_i) " CTL(sts)",                     \
825
        .size     = 1,                                                \
826
        .shift    = 24,                                               \
827
        .wmask    = 0x1c000000,                                       \
828
        .wclear   = 0x1c000000,                                       \
829
        .offset   = offsetof(IntelHDAState, st[_i].ctl),              \
830
        .whandler = intel_hda_set_st_ctl,                             \
831
    },                                                                \
832
    [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = {                              \
833
        .stream   = _i,                                               \
834
        .name     = _t stringify(_i) " LPIB",                         \
835
        .size     = 4,                                                \
836
        .offset   = offsetof(IntelHDAState, st[_i].lpib),             \
837
    },                                                                \
838
    [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = {                     \
839
        .stream   = _i,                                               \
840
        .name     = _t stringify(_i) " LPIB(alias)",                  \
841
        .size     = 4,                                                \
842
        .offset   = offsetof(IntelHDAState, st[_i].lpib),             \
843
    },                                                                \
844
    [ ST_REG(_i, ICH6_REG_SD_CBL) ] = {                               \
845
        .stream   = _i,                                               \
846
        .name     = _t stringify(_i) " CBL",                          \
847
        .size     = 4,                                                \
848
        .wmask    = 0xffffffff,                                       \
849
        .offset   = offsetof(IntelHDAState, st[_i].cbl),              \
850
    },                                                                \
851
    [ ST_REG(_i, ICH6_REG_SD_LVI) ] = {                               \
852
        .stream   = _i,                                               \
853
        .name     = _t stringify(_i) " LVI",                          \
854
        .size     = 2,                                                \
855
        .wmask    = 0x00ff,                                           \
856
        .offset   = offsetof(IntelHDAState, st[_i].lvi),              \
857
    },                                                                \
858
    [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = {                          \
859
        .stream   = _i,                                               \
860
        .name     = _t stringify(_i) " FIFOS",                        \
861
        .size     = 2,                                                \
862
        .reset    = HDA_BUFFER_SIZE,                                  \
863
    },                                                                \
864
    [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = {                            \
865
        .stream   = _i,                                               \
866
        .name     = _t stringify(_i) " FMT",                          \
867
        .size     = 2,                                                \
868
        .wmask    = 0x7f7f,                                           \
869
        .offset   = offsetof(IntelHDAState, st[_i].fmt),              \
870
    },                                                                \
871
    [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = {                             \
872
        .stream   = _i,                                               \
873
        .name     = _t stringify(_i) " BDLPL",                        \
874
        .size     = 4,                                                \
875
        .wmask    = 0xffffff80,                                       \
876
        .offset   = offsetof(IntelHDAState, st[_i].bdlp_lbase),       \
877
    },                                                                \
878
    [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = {                             \
879
        .stream   = _i,                                               \
880
        .name     = _t stringify(_i) " BDLPU",                        \
881
        .size     = 4,                                                \
882
        .wmask    = 0xffffffff,                                       \
883
        .offset   = offsetof(IntelHDAState, st[_i].bdlp_ubase),       \
884
    },                                                                \
885

    
886
    HDA_STREAM("IN", 0)
887
    HDA_STREAM("IN", 1)
888
    HDA_STREAM("IN", 2)
889
    HDA_STREAM("IN", 3)
890

    
891
    HDA_STREAM("OUT", 4)
892
    HDA_STREAM("OUT", 5)
893
    HDA_STREAM("OUT", 6)
894
    HDA_STREAM("OUT", 7)
895

    
896
};
897

    
898
static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, target_phys_addr_t addr)
899
{
900
    const IntelHDAReg *reg;
901

    
902
    if (addr >= sizeof(regtab)/sizeof(regtab[0])) {
903
        goto noreg;
904
    }
905
    reg = regtab+addr;
906
    if (reg->name == NULL) {
907
        goto noreg;
908
    }
909
    return reg;
910

    
911
noreg:
912
    dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr);
913
    return NULL;
914
}
915

    
916
static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
917
{
918
    uint8_t *addr = (void*)d;
919

    
920
    addr += reg->offset;
921
    return (uint32_t*)addr;
922
}
923

    
924
static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val,
925
                                uint32_t wmask)
926
{
927
    uint32_t *addr;
928
    uint32_t old;
929

    
930
    if (!reg) {
931
        return;
932
    }
933

    
934
    if (d->debug) {
935
        time_t now = time(NULL);
936
        if (d->last_write && d->last_reg == reg && d->last_val == val) {
937
            d->repeat_count++;
938
            if (d->last_sec != now) {
939
                dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
940
                d->last_sec = now;
941
                d->repeat_count = 0;
942
            }
943
        } else {
944
            if (d->repeat_count) {
945
                dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
946
            }
947
            dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask);
948
            d->last_write = 1;
949
            d->last_reg   = reg;
950
            d->last_val   = val;
951
            d->last_sec   = now;
952
            d->repeat_count = 0;
953
        }
954
    }
955
    assert(reg->offset != 0);
956

    
957
    addr = intel_hda_reg_addr(d, reg);
958
    old = *addr;
959

    
960
    if (reg->shift) {
961
        val <<= reg->shift;
962
        wmask <<= reg->shift;
963
    }
964
    wmask &= reg->wmask;
965
    *addr &= ~wmask;
966
    *addr |= wmask & val;
967
    *addr &= ~(val & reg->wclear);
968

    
969
    if (reg->whandler) {
970
        reg->whandler(d, reg, old);
971
    }
972
}
973

    
974
static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg,
975
                                   uint32_t rmask)
976
{
977
    uint32_t *addr, ret;
978

    
979
    if (!reg) {
980
        return 0;
981
    }
982

    
983
    if (reg->rhandler) {
984
        reg->rhandler(d, reg);
985
    }
986

    
987
    if (reg->offset == 0) {
988
        /* constant read-only register */
989
        ret = reg->reset;
990
    } else {
991
        addr = intel_hda_reg_addr(d, reg);
992
        ret = *addr;
993
        if (reg->shift) {
994
            ret >>= reg->shift;
995
        }
996
        ret &= rmask;
997
    }
998
    if (d->debug) {
999
        time_t now = time(NULL);
1000
        if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
1001
            d->repeat_count++;
1002
            if (d->last_sec != now) {
1003
                dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1004
                d->last_sec = now;
1005
                d->repeat_count = 0;
1006
            }
1007
        } else {
1008
            if (d->repeat_count) {
1009
                dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1010
            }
1011
            dprint(d, 2, "read  %-16s: 0x%x (%x)\n", reg->name, ret, rmask);
1012
            d->last_write = 0;
1013
            d->last_reg   = reg;
1014
            d->last_val   = ret;
1015
            d->last_sec   = now;
1016
            d->repeat_count = 0;
1017
        }
1018
    }
1019
    return ret;
1020
}
1021

    
1022
static void intel_hda_regs_reset(IntelHDAState *d)
1023
{
1024
    uint32_t *addr;
1025
    int i;
1026

    
1027
    for (i = 0; i < sizeof(regtab)/sizeof(regtab[0]); i++) {
1028
        if (regtab[i].name == NULL) {
1029
            continue;
1030
        }
1031
        if (regtab[i].offset == 0) {
1032
            continue;
1033
        }
1034
        addr = intel_hda_reg_addr(d, regtab + i);
1035
        *addr = regtab[i].reset;
1036
    }
1037
}
1038

    
1039
/* --------------------------------------------------------------------- */
1040

    
1041
static void intel_hda_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1042
{
1043
    IntelHDAState *d = opaque;
1044
    const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1045

    
1046
    intel_hda_reg_write(d, reg, val, 0xff);
1047
}
1048

    
1049
static void intel_hda_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1050
{
1051
    IntelHDAState *d = opaque;
1052
    const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1053

    
1054
    intel_hda_reg_write(d, reg, val, 0xffff);
1055
}
1056

    
1057
static void intel_hda_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1058
{
1059
    IntelHDAState *d = opaque;
1060
    const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1061

    
1062
    intel_hda_reg_write(d, reg, val, 0xffffffff);
1063
}
1064

    
1065
static uint32_t intel_hda_mmio_readb(void *opaque, target_phys_addr_t addr)
1066
{
1067
    IntelHDAState *d = opaque;
1068
    const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1069

    
1070
    return intel_hda_reg_read(d, reg, 0xff);
1071
}
1072

    
1073
static uint32_t intel_hda_mmio_readw(void *opaque, target_phys_addr_t addr)
1074
{
1075
    IntelHDAState *d = opaque;
1076
    const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1077

    
1078
    return intel_hda_reg_read(d, reg, 0xffff);
1079
}
1080

    
1081
static uint32_t intel_hda_mmio_readl(void *opaque, target_phys_addr_t addr)
1082
{
1083
    IntelHDAState *d = opaque;
1084
    const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1085

    
1086
    return intel_hda_reg_read(d, reg, 0xffffffff);
1087
}
1088

    
1089
static CPUReadMemoryFunc * const intel_hda_mmio_read[3] = {
1090
    intel_hda_mmio_readb,
1091
    intel_hda_mmio_readw,
1092
    intel_hda_mmio_readl,
1093
};
1094

    
1095
static CPUWriteMemoryFunc * const intel_hda_mmio_write[3] = {
1096
    intel_hda_mmio_writeb,
1097
    intel_hda_mmio_writew,
1098
    intel_hda_mmio_writel,
1099
};
1100

    
1101
static void intel_hda_map(PCIDevice *pci, int region_num,
1102
                          pcibus_t addr, pcibus_t size, int type)
1103
{
1104
    IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1105

    
1106
    cpu_register_physical_memory(addr, 0x4000, d->mmio_addr);
1107
}
1108

    
1109
/* --------------------------------------------------------------------- */
1110

    
1111
static void intel_hda_reset(DeviceState *dev)
1112
{
1113
    IntelHDAState *d = DO_UPCAST(IntelHDAState, pci.qdev, dev);
1114
    DeviceState *qdev;
1115
    HDACodecDevice *cdev;
1116

    
1117
    intel_hda_regs_reset(d);
1118
    d->wall_base_ns = qemu_get_clock(vm_clock);
1119

    
1120
    /* reset codecs */
1121
    QLIST_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
1122
        cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
1123
        if (qdev->info->reset) {
1124
            qdev->info->reset(qdev);
1125
        }
1126
        d->state_sts |= (1 << cdev->cad);
1127
    }
1128
    intel_hda_update_irq(d);
1129
}
1130

    
1131
static int intel_hda_init(PCIDevice *pci)
1132
{
1133
    IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1134
    uint8_t *conf = d->pci.config;
1135

    
1136
    d->name = d->pci.qdev.info->name;
1137

    
1138
    pci_config_set_vendor_id(conf, PCI_VENDOR_ID_INTEL);
1139
    pci_config_set_device_id(conf, 0x2668);
1140
    pci_config_set_revision(conf, 1);
1141
    pci_config_set_class(conf, PCI_CLASS_MULTIMEDIA_HD_AUDIO);
1142
    pci_config_set_interrupt_pin(conf, 1);
1143

    
1144
    /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1145
    conf[0x40] = 0x01;
1146

    
1147
    d->mmio_addr = cpu_register_io_memory(intel_hda_mmio_read,
1148
                                          intel_hda_mmio_write, d);
1149
    pci_register_bar(&d->pci, 0, 0x4000, PCI_BASE_ADDRESS_SPACE_MEMORY,
1150
                     intel_hda_map);
1151

    
1152
    hda_codec_bus_init(&d->pci.qdev, &d->codecs,
1153
                       intel_hda_response, intel_hda_xfer);
1154

    
1155
    return 0;
1156
}
1157

    
1158
static int intel_hda_exit(PCIDevice *pci)
1159
{
1160
    IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1161

    
1162
    cpu_unregister_io_memory(d->mmio_addr);
1163
    return 0;
1164
}
1165

    
1166
static int intel_hda_post_load(void *opaque, int version)
1167
{
1168
    IntelHDAState* d = opaque;
1169
    int i;
1170

    
1171
    dprint(d, 1, "%s\n", __FUNCTION__);
1172
    for (i = 0; i < ARRAY_SIZE(d->st); i++) {
1173
        if (d->st[i].ctl & 0x02) {
1174
            intel_hda_parse_bdl(d, &d->st[i]);
1175
        }
1176
    }
1177
    intel_hda_update_irq(d);
1178
    return 0;
1179
}
1180

    
1181
static const VMStateDescription vmstate_intel_hda_stream = {
1182
    .name = "intel-hda-stream",
1183
    .version_id = 1,
1184
    .fields = (VMStateField []) {
1185
        VMSTATE_UINT32(ctl, IntelHDAStream),
1186
        VMSTATE_UINT32(lpib, IntelHDAStream),
1187
        VMSTATE_UINT32(cbl, IntelHDAStream),
1188
        VMSTATE_UINT32(lvi, IntelHDAStream),
1189
        VMSTATE_UINT32(fmt, IntelHDAStream),
1190
        VMSTATE_UINT32(bdlp_lbase, IntelHDAStream),
1191
        VMSTATE_UINT32(bdlp_ubase, IntelHDAStream),
1192
        VMSTATE_END_OF_LIST()
1193
    }
1194
};
1195

    
1196
static const VMStateDescription vmstate_intel_hda = {
1197
    .name = "intel-hda",
1198
    .version_id = 1,
1199
    .post_load = intel_hda_post_load,
1200
    .fields = (VMStateField []) {
1201
        VMSTATE_PCI_DEVICE(pci, IntelHDAState),
1202

    
1203
        /* registers */
1204
        VMSTATE_UINT32(g_ctl, IntelHDAState),
1205
        VMSTATE_UINT32(wake_en, IntelHDAState),
1206
        VMSTATE_UINT32(state_sts, IntelHDAState),
1207
        VMSTATE_UINT32(int_ctl, IntelHDAState),
1208
        VMSTATE_UINT32(int_sts, IntelHDAState),
1209
        VMSTATE_UINT32(wall_clk, IntelHDAState),
1210
        VMSTATE_UINT32(corb_lbase, IntelHDAState),
1211
        VMSTATE_UINT32(corb_ubase, IntelHDAState),
1212
        VMSTATE_UINT32(corb_rp, IntelHDAState),
1213
        VMSTATE_UINT32(corb_wp, IntelHDAState),
1214
        VMSTATE_UINT32(corb_ctl, IntelHDAState),
1215
        VMSTATE_UINT32(corb_sts, IntelHDAState),
1216
        VMSTATE_UINT32(corb_size, IntelHDAState),
1217
        VMSTATE_UINT32(rirb_lbase, IntelHDAState),
1218
        VMSTATE_UINT32(rirb_ubase, IntelHDAState),
1219
        VMSTATE_UINT32(rirb_wp, IntelHDAState),
1220
        VMSTATE_UINT32(rirb_cnt, IntelHDAState),
1221
        VMSTATE_UINT32(rirb_ctl, IntelHDAState),
1222
        VMSTATE_UINT32(rirb_sts, IntelHDAState),
1223
        VMSTATE_UINT32(rirb_size, IntelHDAState),
1224
        VMSTATE_UINT32(dp_lbase, IntelHDAState),
1225
        VMSTATE_UINT32(dp_ubase, IntelHDAState),
1226
        VMSTATE_UINT32(icw, IntelHDAState),
1227
        VMSTATE_UINT32(irr, IntelHDAState),
1228
        VMSTATE_UINT32(ics, IntelHDAState),
1229
        VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0,
1230
                             vmstate_intel_hda_stream,
1231
                             IntelHDAStream),
1232

    
1233
        /* additional state info */
1234
        VMSTATE_UINT32(rirb_count, IntelHDAState),
1235
        VMSTATE_INT64(wall_base_ns, IntelHDAState),
1236

    
1237
        VMSTATE_END_OF_LIST()
1238
    }
1239
};
1240

    
1241
static PCIDeviceInfo intel_hda_info = {
1242
    .qdev.name    = "intel-hda",
1243
    .qdev.desc    = "Intel HD Audio Controller",
1244
    .qdev.size    = sizeof(IntelHDAState),
1245
    .qdev.vmsd    = &vmstate_intel_hda,
1246
    .qdev.reset   = intel_hda_reset,
1247
    .init         = intel_hda_init,
1248
    .exit         = intel_hda_exit,
1249
    .qdev.props   = (Property[]) {
1250
        DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
1251
        DEFINE_PROP_END_OF_LIST(),
1252
    }
1253
};
1254

    
1255
static void intel_hda_register(void)
1256
{
1257
    pci_qdev_register(&intel_hda_info);
1258
}
1259
device_init(intel_hda_register);
1260

    
1261
/*
1262
 * create intel hda controller with codec attached to it,
1263
 * so '-soundhw hda' works.
1264
 */
1265
int intel_hda_and_codec_init(PCIBus *bus)
1266
{
1267
    PCIDevice *controller;
1268
    BusState *hdabus;
1269
    DeviceState *codec;
1270

    
1271
    controller = pci_create_simple(bus, -1, "intel-hda");
1272
    hdabus = QLIST_FIRST(&controller->qdev.child_bus);
1273
    codec = qdev_create(hdabus, "hda-duplex");
1274
    qdev_init_nofail(codec);
1275
    return 0;
1276
}
1277