root / target-mips / op_helper.c @ 6a385343
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/*
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* MIPS emulation helpers for qemu.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdlib.h> |
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#include "exec.h" |
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#include "host-utils.h" |
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#include "helper.h" |
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#ifndef CONFIG_USER_ONLY
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static inline void cpu_mips_tlb_flush (CPUState *env, int flush_global); |
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#endif
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/*****************************************************************************/
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/* Exceptions processing helpers */
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void helper_raise_exception_err (uint32_t exception, int error_code) |
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{ |
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#if 1 |
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if (exception < 0x100) |
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qemu_log("%s: %d %d\n", __func__, exception, error_code);
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#endif
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env->exception_index = exception; |
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env->error_code = error_code; |
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cpu_loop_exit(); |
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} |
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void helper_raise_exception (uint32_t exception)
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{ |
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helper_raise_exception_err(exception, 0);
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} |
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#if !defined(CONFIG_USER_ONLY)
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static void do_restore_state (void *pc_ptr) |
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{ |
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TranslationBlock *tb; |
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unsigned long pc = (unsigned long) pc_ptr; |
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tb = tb_find_pc (pc); |
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if (tb) {
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cpu_restore_state (tb, env, pc, NULL);
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} |
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} |
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#endif
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#if defined(CONFIG_USER_ONLY)
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#define HELPER_LD(name, insn, type) \
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static inline type do_##name(target_ulong addr, int mem_idx) \ |
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{ \ |
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return (type) insn##_raw(addr); \ |
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} |
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#else
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#define HELPER_LD(name, insn, type) \
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static inline type do_##name(target_ulong addr, int mem_idx) \ |
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{ \ |
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switch (mem_idx) \
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{ \ |
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case 0: return (type) insn##_kernel(addr); break; \ |
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case 1: return (type) insn##_super(addr); break; \ |
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default: \
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case 2: return (type) insn##_user(addr); break; \ |
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} \ |
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} |
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#endif
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HELPER_LD(lbu, ldub, uint8_t) |
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HELPER_LD(lw, ldl, int32_t) |
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#ifdef TARGET_MIPS64
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HELPER_LD(ld, ldq, int64_t) |
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#endif
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#undef HELPER_LD
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#if defined(CONFIG_USER_ONLY)
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#define HELPER_ST(name, insn, type) \
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static inline void do_##name(target_ulong addr, type val, int mem_idx) \ |
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{ \ |
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insn##_raw(addr, val); \ |
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} |
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#else
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#define HELPER_ST(name, insn, type) \
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static inline void do_##name(target_ulong addr, type val, int mem_idx) \ |
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{ \ |
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switch (mem_idx) \
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{ \ |
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case 0: insn##_kernel(addr, val); break; \ |
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case 1: insn##_super(addr, val); break; \ |
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default: \
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case 2: insn##_user(addr, val); break; \ |
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} \ |
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} |
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#endif
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HELPER_ST(sb, stb, uint8_t) |
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HELPER_ST(sw, stl, uint32_t) |
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#ifdef TARGET_MIPS64
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HELPER_ST(sd, stq, uint64_t) |
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#endif
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#undef HELPER_ST
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target_ulong helper_clo (target_ulong arg1) |
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{ |
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return clo32(arg1);
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} |
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target_ulong helper_clz (target_ulong arg1) |
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{ |
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return clz32(arg1);
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} |
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#if defined(TARGET_MIPS64)
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target_ulong helper_dclo (target_ulong arg1) |
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{ |
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return clo64(arg1);
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} |
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target_ulong helper_dclz (target_ulong arg1) |
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{ |
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return clz64(arg1);
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} |
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#endif /* TARGET_MIPS64 */ |
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/* 64 bits arithmetic for 32 bits hosts */
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static inline uint64_t get_HILO (void) |
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{ |
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return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0]; |
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} |
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static inline void set_HILO (uint64_t HILO) |
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{ |
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env->active_tc.LO[0] = (int32_t)HILO;
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env->active_tc.HI[0] = (int32_t)(HILO >> 32); |
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} |
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static inline void set_HIT0_LO (target_ulong arg1, uint64_t HILO) |
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{ |
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env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); |
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arg1 = env->active_tc.HI[0] = (int32_t)(HILO >> 32); |
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} |
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static inline void set_HI_LOT0 (target_ulong arg1, uint64_t HILO) |
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{ |
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arg1 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); |
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env->active_tc.HI[0] = (int32_t)(HILO >> 32); |
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} |
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/* Multiplication variants of the vr54xx. */
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target_ulong helper_muls (target_ulong arg1, target_ulong arg2) |
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{ |
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set_HI_LOT0(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
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return arg1;
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} |
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target_ulong helper_mulsu (target_ulong arg1, target_ulong arg2) |
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{ |
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set_HI_LOT0(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
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return arg1;
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} |
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target_ulong helper_macc (target_ulong arg1, target_ulong arg2) |
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{ |
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set_HI_LOT0(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); |
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return arg1;
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} |
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target_ulong helper_macchi (target_ulong arg1, target_ulong arg2) |
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{ |
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set_HIT0_LO(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); |
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return arg1;
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} |
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target_ulong helper_maccu (target_ulong arg1, target_ulong arg2) |
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{ |
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set_HI_LOT0(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); |
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return arg1;
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} |
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target_ulong helper_macchiu (target_ulong arg1, target_ulong arg2) |
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{ |
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set_HIT0_LO(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); |
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return arg1;
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} |
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target_ulong helper_msac (target_ulong arg1, target_ulong arg2) |
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{ |
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set_HI_LOT0(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); |
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return arg1;
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} |
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target_ulong helper_msachi (target_ulong arg1, target_ulong arg2) |
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{ |
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set_HIT0_LO(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); |
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return arg1;
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} |
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target_ulong helper_msacu (target_ulong arg1, target_ulong arg2) |
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{ |
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set_HI_LOT0(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); |
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return arg1;
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} |
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target_ulong helper_msachiu (target_ulong arg1, target_ulong arg2) |
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{ |
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set_HIT0_LO(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); |
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return arg1;
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} |
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target_ulong helper_mulhi (target_ulong arg1, target_ulong arg2) |
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{ |
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set_HIT0_LO(arg1, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2); |
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return arg1;
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} |
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target_ulong helper_mulhiu (target_ulong arg1, target_ulong arg2) |
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{ |
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set_HIT0_LO(arg1, (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); |
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return arg1;
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} |
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target_ulong helper_mulshi (target_ulong arg1, target_ulong arg2) |
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{ |
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set_HIT0_LO(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
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return arg1;
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} |
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target_ulong helper_mulshiu (target_ulong arg1, target_ulong arg2) |
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{ |
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set_HIT0_LO(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
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return arg1;
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} |
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#ifdef TARGET_MIPS64
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void helper_dmult (target_ulong arg1, target_ulong arg2)
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{ |
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muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2); |
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} |
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void helper_dmultu (target_ulong arg1, target_ulong arg2)
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{ |
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mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2); |
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} |
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#endif
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#ifndef CONFIG_USER_ONLY
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static inline target_phys_addr_t do_translate_address(target_ulong address, int rw) |
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{ |
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target_phys_addr_t lladdr; |
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lladdr = cpu_mips_translate_address(env, address, rw); |
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if (lladdr == -1LL) { |
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cpu_loop_exit(); |
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} else {
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return lladdr;
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} |
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} |
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#define HELPER_LD_ATOMIC(name, insn) \
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target_ulong helper_##name(target_ulong arg, int mem_idx) \ |
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{ \ |
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env->lladdr = do_translate_address(arg, 0); \
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env->llval = do_##insn(arg, mem_idx); \ |
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return env->llval; \
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} |
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HELPER_LD_ATOMIC(ll, lw) |
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#ifdef TARGET_MIPS64
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HELPER_LD_ATOMIC(lld, ld) |
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#endif
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#undef HELPER_LD_ATOMIC
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#define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
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target_ulong helper_##name(target_ulong arg1, target_ulong arg2, int mem_idx) \ |
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{ \ |
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target_long tmp; \ |
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\ |
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if (arg2 & almask) { \
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env->CP0_BadVAddr = arg2; \ |
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helper_raise_exception(EXCP_AdES); \ |
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} \ |
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if (do_translate_address(arg2, 1) == env->lladdr) { \ |
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tmp = do_##ld_insn(arg2, mem_idx); \ |
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if (tmp == env->llval) { \
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do_##st_insn(arg2, arg1, mem_idx); \ |
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return 1; \ |
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} \ |
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} \ |
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return 0; \ |
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} |
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HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
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#ifdef TARGET_MIPS64
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HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
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#endif
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#undef HELPER_ST_ATOMIC
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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#define GET_LMASK(v) ((v) & 3) |
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#define GET_OFFSET(addr, offset) (addr + (offset))
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#else
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#define GET_LMASK(v) (((v) & 3) ^ 3) |
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#define GET_OFFSET(addr, offset) (addr - (offset))
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#endif
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target_ulong helper_lwl(target_ulong arg1, target_ulong arg2, int mem_idx)
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{ |
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target_ulong tmp; |
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tmp = do_lbu(arg2, mem_idx); |
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arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24); |
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if (GET_LMASK(arg2) <= 2) { |
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tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx);
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arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16); |
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} |
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if (GET_LMASK(arg2) <= 1) { |
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tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx);
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arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8); |
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} |
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if (GET_LMASK(arg2) == 0) { |
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tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx);
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arg1 = (arg1 & 0xFFFFFF00) | tmp;
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} |
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return (int32_t)arg1;
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} |
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target_ulong helper_lwr(target_ulong arg1, target_ulong arg2, int mem_idx)
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{ |
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target_ulong tmp; |
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tmp = do_lbu(arg2, mem_idx); |
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arg1 = (arg1 & 0xFFFFFF00) | tmp;
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if (GET_LMASK(arg2) >= 1) { |
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tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx);
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arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8); |
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} |
367 |
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if (GET_LMASK(arg2) >= 2) { |
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tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx);
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arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16); |
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} |
372 |
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if (GET_LMASK(arg2) == 3) { |
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tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx);
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arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24); |
376 |
} |
377 |
return (int32_t)arg1;
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} |
379 |
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void helper_swl(target_ulong arg1, target_ulong arg2, int mem_idx) |
381 |
{ |
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do_sb(arg2, (uint8_t)(arg1 >> 24), mem_idx);
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if (GET_LMASK(arg2) <= 2) |
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do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx); |
386 |
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if (GET_LMASK(arg2) <= 1) |
388 |
do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx); |
389 |
|
390 |
if (GET_LMASK(arg2) == 0) |
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do_sb(GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
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392 |
} |
393 |
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void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx) |
395 |
{ |
396 |
do_sb(arg2, (uint8_t)arg1, mem_idx); |
397 |
|
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if (GET_LMASK(arg2) >= 1) |
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do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); |
400 |
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if (GET_LMASK(arg2) >= 2) |
402 |
do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); |
403 |
|
404 |
if (GET_LMASK(arg2) == 3) |
405 |
do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); |
406 |
} |
407 |
|
408 |
#if defined(TARGET_MIPS64)
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/* "half" load and stores. We must do the memory access inline,
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or fault handling won't work. */
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411 |
|
412 |
#ifdef TARGET_WORDS_BIGENDIAN
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413 |
#define GET_LMASK64(v) ((v) & 7) |
414 |
#else
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415 |
#define GET_LMASK64(v) (((v) & 7) ^ 7) |
416 |
#endif
|
417 |
|
418 |
target_ulong helper_ldl(target_ulong arg1, target_ulong arg2, int mem_idx)
|
419 |
{ |
420 |
uint64_t tmp; |
421 |
|
422 |
tmp = do_lbu(arg2, mem_idx); |
423 |
arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); |
424 |
|
425 |
if (GET_LMASK64(arg2) <= 6) { |
426 |
tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx);
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arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); |
428 |
} |
429 |
|
430 |
if (GET_LMASK64(arg2) <= 5) { |
431 |
tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx);
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432 |
arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); |
433 |
} |
434 |
|
435 |
if (GET_LMASK64(arg2) <= 4) { |
436 |
tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx);
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437 |
arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); |
438 |
} |
439 |
|
440 |
if (GET_LMASK64(arg2) <= 3) { |
441 |
tmp = do_lbu(GET_OFFSET(arg2, 4), mem_idx);
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arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); |
443 |
} |
444 |
|
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if (GET_LMASK64(arg2) <= 2) { |
446 |
tmp = do_lbu(GET_OFFSET(arg2, 5), mem_idx);
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arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); |
448 |
} |
449 |
|
450 |
if (GET_LMASK64(arg2) <= 1) { |
451 |
tmp = do_lbu(GET_OFFSET(arg2, 6), mem_idx);
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arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); |
453 |
} |
454 |
|
455 |
if (GET_LMASK64(arg2) == 0) { |
456 |
tmp = do_lbu(GET_OFFSET(arg2, 7), mem_idx);
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457 |
arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
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458 |
} |
459 |
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return arg1;
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} |
462 |
|
463 |
target_ulong helper_ldr(target_ulong arg1, target_ulong arg2, int mem_idx)
|
464 |
{ |
465 |
uint64_t tmp; |
466 |
|
467 |
tmp = do_lbu(arg2, mem_idx); |
468 |
arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
|
469 |
|
470 |
if (GET_LMASK64(arg2) >= 1) { |
471 |
tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx);
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472 |
arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); |
473 |
} |
474 |
|
475 |
if (GET_LMASK64(arg2) >= 2) { |
476 |
tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx);
|
477 |
arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); |
478 |
} |
479 |
|
480 |
if (GET_LMASK64(arg2) >= 3) { |
481 |
tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx);
|
482 |
arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); |
483 |
} |
484 |
|
485 |
if (GET_LMASK64(arg2) >= 4) { |
486 |
tmp = do_lbu(GET_OFFSET(arg2, -4), mem_idx);
|
487 |
arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); |
488 |
} |
489 |
|
490 |
if (GET_LMASK64(arg2) >= 5) { |
491 |
tmp = do_lbu(GET_OFFSET(arg2, -5), mem_idx);
|
492 |
arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); |
493 |
} |
494 |
|
495 |
if (GET_LMASK64(arg2) >= 6) { |
496 |
tmp = do_lbu(GET_OFFSET(arg2, -6), mem_idx);
|
497 |
arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); |
498 |
} |
499 |
|
500 |
if (GET_LMASK64(arg2) == 7) { |
501 |
tmp = do_lbu(GET_OFFSET(arg2, -7), mem_idx);
|
502 |
arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); |
503 |
} |
504 |
|
505 |
return arg1;
|
506 |
} |
507 |
|
508 |
void helper_sdl(target_ulong arg1, target_ulong arg2, int mem_idx) |
509 |
{ |
510 |
do_sb(arg2, (uint8_t)(arg1 >> 56), mem_idx);
|
511 |
|
512 |
if (GET_LMASK64(arg2) <= 6) |
513 |
do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx); |
514 |
|
515 |
if (GET_LMASK64(arg2) <= 5) |
516 |
do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx); |
517 |
|
518 |
if (GET_LMASK64(arg2) <= 4) |
519 |
do_sb(GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx); |
520 |
|
521 |
if (GET_LMASK64(arg2) <= 3) |
522 |
do_sb(GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx); |
523 |
|
524 |
if (GET_LMASK64(arg2) <= 2) |
525 |
do_sb(GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx); |
526 |
|
527 |
if (GET_LMASK64(arg2) <= 1) |
528 |
do_sb(GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx); |
529 |
|
530 |
if (GET_LMASK64(arg2) <= 0) |
531 |
do_sb(GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
|
532 |
} |
533 |
|
534 |
void helper_sdr(target_ulong arg1, target_ulong arg2, int mem_idx) |
535 |
{ |
536 |
do_sb(arg2, (uint8_t)arg1, mem_idx); |
537 |
|
538 |
if (GET_LMASK64(arg2) >= 1) |
539 |
do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); |
540 |
|
541 |
if (GET_LMASK64(arg2) >= 2) |
542 |
do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); |
543 |
|
544 |
if (GET_LMASK64(arg2) >= 3) |
545 |
do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); |
546 |
|
547 |
if (GET_LMASK64(arg2) >= 4) |
548 |
do_sb(GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx); |
549 |
|
550 |
if (GET_LMASK64(arg2) >= 5) |
551 |
do_sb(GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx); |
552 |
|
553 |
if (GET_LMASK64(arg2) >= 6) |
554 |
do_sb(GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx); |
555 |
|
556 |
if (GET_LMASK64(arg2) == 7) |
557 |
do_sb(GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx); |
558 |
} |
559 |
#endif /* TARGET_MIPS64 */ |
560 |
|
561 |
static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 }; |
562 |
|
563 |
void helper_lwm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
|
564 |
{ |
565 |
target_ulong base_reglist = reglist & 0xf;
|
566 |
target_ulong do_r31 = reglist & 0x10;
|
567 |
#ifdef CONFIG_USER_ONLY
|
568 |
#undef ldfun
|
569 |
#define ldfun ldl_raw
|
570 |
#else
|
571 |
uint32_t (*ldfun)(target_ulong); |
572 |
|
573 |
switch (mem_idx)
|
574 |
{ |
575 |
case 0: ldfun = ldl_kernel; break; |
576 |
case 1: ldfun = ldl_super; break; |
577 |
default:
|
578 |
case 2: ldfun = ldl_user; break; |
579 |
} |
580 |
#endif
|
581 |
|
582 |
if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { |
583 |
target_ulong i; |
584 |
|
585 |
for (i = 0; i < base_reglist; i++) { |
586 |
env->active_tc.gpr[multiple_regs[i]] = (target_long) ldfun(addr); |
587 |
addr += 4;
|
588 |
} |
589 |
} |
590 |
|
591 |
if (do_r31) {
|
592 |
env->active_tc.gpr[31] = (target_long) ldfun(addr);
|
593 |
} |
594 |
} |
595 |
|
596 |
void helper_swm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
|
597 |
{ |
598 |
target_ulong base_reglist = reglist & 0xf;
|
599 |
target_ulong do_r31 = reglist & 0x10;
|
600 |
#ifdef CONFIG_USER_ONLY
|
601 |
#undef stfun
|
602 |
#define stfun stl_raw
|
603 |
#else
|
604 |
void (*stfun)(target_ulong, uint32_t);
|
605 |
|
606 |
switch (mem_idx)
|
607 |
{ |
608 |
case 0: stfun = stl_kernel; break; |
609 |
case 1: stfun = stl_super; break; |
610 |
default:
|
611 |
case 2: stfun = stl_user; break; |
612 |
} |
613 |
#endif
|
614 |
|
615 |
if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { |
616 |
target_ulong i; |
617 |
|
618 |
for (i = 0; i < base_reglist; i++) { |
619 |
stfun(addr, env->active_tc.gpr[multiple_regs[i]]); |
620 |
addr += 4;
|
621 |
} |
622 |
} |
623 |
|
624 |
if (do_r31) {
|
625 |
stfun(addr, env->active_tc.gpr[31]);
|
626 |
} |
627 |
} |
628 |
|
629 |
#if defined(TARGET_MIPS64)
|
630 |
void helper_ldm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
|
631 |
{ |
632 |
target_ulong base_reglist = reglist & 0xf;
|
633 |
target_ulong do_r31 = reglist & 0x10;
|
634 |
#ifdef CONFIG_USER_ONLY
|
635 |
#undef ldfun
|
636 |
#define ldfun ldq_raw
|
637 |
#else
|
638 |
uint64_t (*ldfun)(target_ulong); |
639 |
|
640 |
switch (mem_idx)
|
641 |
{ |
642 |
case 0: ldfun = ldq_kernel; break; |
643 |
case 1: ldfun = ldq_super; break; |
644 |
default:
|
645 |
case 2: ldfun = ldq_user; break; |
646 |
} |
647 |
#endif
|
648 |
|
649 |
if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { |
650 |
target_ulong i; |
651 |
|
652 |
for (i = 0; i < base_reglist; i++) { |
653 |
env->active_tc.gpr[multiple_regs[i]] = ldfun(addr); |
654 |
addr += 8;
|
655 |
} |
656 |
} |
657 |
|
658 |
if (do_r31) {
|
659 |
env->active_tc.gpr[31] = ldfun(addr);
|
660 |
} |
661 |
} |
662 |
|
663 |
void helper_sdm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
|
664 |
{ |
665 |
target_ulong base_reglist = reglist & 0xf;
|
666 |
target_ulong do_r31 = reglist & 0x10;
|
667 |
#ifdef CONFIG_USER_ONLY
|
668 |
#undef stfun
|
669 |
#define stfun stq_raw
|
670 |
#else
|
671 |
void (*stfun)(target_ulong, uint64_t);
|
672 |
|
673 |
switch (mem_idx)
|
674 |
{ |
675 |
case 0: stfun = stq_kernel; break; |
676 |
case 1: stfun = stq_super; break; |
677 |
default:
|
678 |
case 2: stfun = stq_user; break; |
679 |
} |
680 |
#endif
|
681 |
|
682 |
if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { |
683 |
target_ulong i; |
684 |
|
685 |
for (i = 0; i < base_reglist; i++) { |
686 |
stfun(addr, env->active_tc.gpr[multiple_regs[i]]); |
687 |
addr += 8;
|
688 |
} |
689 |
} |
690 |
|
691 |
if (do_r31) {
|
692 |
stfun(addr, env->active_tc.gpr[31]);
|
693 |
} |
694 |
} |
695 |
#endif
|
696 |
|
697 |
#ifndef CONFIG_USER_ONLY
|
698 |
/* CP0 helpers */
|
699 |
target_ulong helper_mfc0_mvpcontrol (void)
|
700 |
{ |
701 |
return env->mvp->CP0_MVPControl;
|
702 |
} |
703 |
|
704 |
target_ulong helper_mfc0_mvpconf0 (void)
|
705 |
{ |
706 |
return env->mvp->CP0_MVPConf0;
|
707 |
} |
708 |
|
709 |
target_ulong helper_mfc0_mvpconf1 (void)
|
710 |
{ |
711 |
return env->mvp->CP0_MVPConf1;
|
712 |
} |
713 |
|
714 |
target_ulong helper_mfc0_random (void)
|
715 |
{ |
716 |
return (int32_t)cpu_mips_get_random(env);
|
717 |
} |
718 |
|
719 |
target_ulong helper_mfc0_tcstatus (void)
|
720 |
{ |
721 |
return env->active_tc.CP0_TCStatus;
|
722 |
} |
723 |
|
724 |
target_ulong helper_mftc0_tcstatus(void)
|
725 |
{ |
726 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
727 |
|
728 |
if (other_tc == env->current_tc)
|
729 |
return env->active_tc.CP0_TCStatus;
|
730 |
else
|
731 |
return env->tcs[other_tc].CP0_TCStatus;
|
732 |
} |
733 |
|
734 |
target_ulong helper_mfc0_tcbind (void)
|
735 |
{ |
736 |
return env->active_tc.CP0_TCBind;
|
737 |
} |
738 |
|
739 |
target_ulong helper_mftc0_tcbind(void)
|
740 |
{ |
741 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
742 |
|
743 |
if (other_tc == env->current_tc)
|
744 |
return env->active_tc.CP0_TCBind;
|
745 |
else
|
746 |
return env->tcs[other_tc].CP0_TCBind;
|
747 |
} |
748 |
|
749 |
target_ulong helper_mfc0_tcrestart (void)
|
750 |
{ |
751 |
return env->active_tc.PC;
|
752 |
} |
753 |
|
754 |
target_ulong helper_mftc0_tcrestart(void)
|
755 |
{ |
756 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
757 |
|
758 |
if (other_tc == env->current_tc)
|
759 |
return env->active_tc.PC;
|
760 |
else
|
761 |
return env->tcs[other_tc].PC;
|
762 |
} |
763 |
|
764 |
target_ulong helper_mfc0_tchalt (void)
|
765 |
{ |
766 |
return env->active_tc.CP0_TCHalt;
|
767 |
} |
768 |
|
769 |
target_ulong helper_mftc0_tchalt(void)
|
770 |
{ |
771 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
772 |
|
773 |
if (other_tc == env->current_tc)
|
774 |
return env->active_tc.CP0_TCHalt;
|
775 |
else
|
776 |
return env->tcs[other_tc].CP0_TCHalt;
|
777 |
} |
778 |
|
779 |
target_ulong helper_mfc0_tccontext (void)
|
780 |
{ |
781 |
return env->active_tc.CP0_TCContext;
|
782 |
} |
783 |
|
784 |
target_ulong helper_mftc0_tccontext(void)
|
785 |
{ |
786 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
787 |
|
788 |
if (other_tc == env->current_tc)
|
789 |
return env->active_tc.CP0_TCContext;
|
790 |
else
|
791 |
return env->tcs[other_tc].CP0_TCContext;
|
792 |
} |
793 |
|
794 |
target_ulong helper_mfc0_tcschedule (void)
|
795 |
{ |
796 |
return env->active_tc.CP0_TCSchedule;
|
797 |
} |
798 |
|
799 |
target_ulong helper_mftc0_tcschedule(void)
|
800 |
{ |
801 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
802 |
|
803 |
if (other_tc == env->current_tc)
|
804 |
return env->active_tc.CP0_TCSchedule;
|
805 |
else
|
806 |
return env->tcs[other_tc].CP0_TCSchedule;
|
807 |
} |
808 |
|
809 |
target_ulong helper_mfc0_tcschefback (void)
|
810 |
{ |
811 |
return env->active_tc.CP0_TCScheFBack;
|
812 |
} |
813 |
|
814 |
target_ulong helper_mftc0_tcschefback(void)
|
815 |
{ |
816 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
817 |
|
818 |
if (other_tc == env->current_tc)
|
819 |
return env->active_tc.CP0_TCScheFBack;
|
820 |
else
|
821 |
return env->tcs[other_tc].CP0_TCScheFBack;
|
822 |
} |
823 |
|
824 |
target_ulong helper_mfc0_count (void)
|
825 |
{ |
826 |
return (int32_t)cpu_mips_get_count(env);
|
827 |
} |
828 |
|
829 |
target_ulong helper_mftc0_entryhi(void)
|
830 |
{ |
831 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
832 |
int32_t tcstatus; |
833 |
|
834 |
if (other_tc == env->current_tc)
|
835 |
tcstatus = env->active_tc.CP0_TCStatus; |
836 |
else
|
837 |
tcstatus = env->tcs[other_tc].CP0_TCStatus; |
838 |
|
839 |
return (env->CP0_EntryHi & ~0xff) | (tcstatus & 0xff); |
840 |
} |
841 |
|
842 |
target_ulong helper_mftc0_status(void)
|
843 |
{ |
844 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
845 |
target_ulong t0; |
846 |
int32_t tcstatus; |
847 |
|
848 |
if (other_tc == env->current_tc)
|
849 |
tcstatus = env->active_tc.CP0_TCStatus; |
850 |
else
|
851 |
tcstatus = env->tcs[other_tc].CP0_TCStatus; |
852 |
|
853 |
t0 = env->CP0_Status & ~0xf1000018;
|
854 |
t0 |= tcstatus & (0xf << CP0TCSt_TCU0);
|
855 |
t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
|
856 |
t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
|
857 |
|
858 |
return t0;
|
859 |
} |
860 |
|
861 |
target_ulong helper_mfc0_lladdr (void)
|
862 |
{ |
863 |
return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
|
864 |
} |
865 |
|
866 |
target_ulong helper_mfc0_watchlo (uint32_t sel) |
867 |
{ |
868 |
return (int32_t)env->CP0_WatchLo[sel];
|
869 |
} |
870 |
|
871 |
target_ulong helper_mfc0_watchhi (uint32_t sel) |
872 |
{ |
873 |
return env->CP0_WatchHi[sel];
|
874 |
} |
875 |
|
876 |
target_ulong helper_mfc0_debug (void)
|
877 |
{ |
878 |
target_ulong t0 = env->CP0_Debug; |
879 |
if (env->hflags & MIPS_HFLAG_DM)
|
880 |
t0 |= 1 << CP0DB_DM;
|
881 |
|
882 |
return t0;
|
883 |
} |
884 |
|
885 |
target_ulong helper_mftc0_debug(void)
|
886 |
{ |
887 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
888 |
int32_t tcstatus; |
889 |
|
890 |
if (other_tc == env->current_tc)
|
891 |
tcstatus = env->active_tc.CP0_Debug_tcstatus; |
892 |
else
|
893 |
tcstatus = env->tcs[other_tc].CP0_Debug_tcstatus; |
894 |
|
895 |
/* XXX: Might be wrong, check with EJTAG spec. */
|
896 |
return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
897 |
(tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
898 |
} |
899 |
|
900 |
#if defined(TARGET_MIPS64)
|
901 |
target_ulong helper_dmfc0_tcrestart (void)
|
902 |
{ |
903 |
return env->active_tc.PC;
|
904 |
} |
905 |
|
906 |
target_ulong helper_dmfc0_tchalt (void)
|
907 |
{ |
908 |
return env->active_tc.CP0_TCHalt;
|
909 |
} |
910 |
|
911 |
target_ulong helper_dmfc0_tccontext (void)
|
912 |
{ |
913 |
return env->active_tc.CP0_TCContext;
|
914 |
} |
915 |
|
916 |
target_ulong helper_dmfc0_tcschedule (void)
|
917 |
{ |
918 |
return env->active_tc.CP0_TCSchedule;
|
919 |
} |
920 |
|
921 |
target_ulong helper_dmfc0_tcschefback (void)
|
922 |
{ |
923 |
return env->active_tc.CP0_TCScheFBack;
|
924 |
} |
925 |
|
926 |
target_ulong helper_dmfc0_lladdr (void)
|
927 |
{ |
928 |
return env->lladdr >> env->CP0_LLAddr_shift;
|
929 |
} |
930 |
|
931 |
target_ulong helper_dmfc0_watchlo (uint32_t sel) |
932 |
{ |
933 |
return env->CP0_WatchLo[sel];
|
934 |
} |
935 |
#endif /* TARGET_MIPS64 */ |
936 |
|
937 |
void helper_mtc0_index (target_ulong arg1)
|
938 |
{ |
939 |
int num = 1; |
940 |
unsigned int tmp = env->tlb->nb_tlb; |
941 |
|
942 |
do {
|
943 |
tmp >>= 1;
|
944 |
num <<= 1;
|
945 |
} while (tmp);
|
946 |
env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1)); |
947 |
} |
948 |
|
949 |
void helper_mtc0_mvpcontrol (target_ulong arg1)
|
950 |
{ |
951 |
uint32_t mask = 0;
|
952 |
uint32_t newval; |
953 |
|
954 |
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) |
955 |
mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | |
956 |
(1 << CP0MVPCo_EVP);
|
957 |
if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
958 |
mask |= (1 << CP0MVPCo_STLB);
|
959 |
newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); |
960 |
|
961 |
// TODO: Enable/disable shared TLB, enable/disable VPEs.
|
962 |
|
963 |
env->mvp->CP0_MVPControl = newval; |
964 |
} |
965 |
|
966 |
void helper_mtc0_vpecontrol (target_ulong arg1)
|
967 |
{ |
968 |
uint32_t mask; |
969 |
uint32_t newval; |
970 |
|
971 |
mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | |
972 |
(1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); |
973 |
newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask); |
974 |
|
975 |
/* Yield scheduler intercept not implemented. */
|
976 |
/* Gating storage scheduler intercept not implemented. */
|
977 |
|
978 |
// TODO: Enable/disable TCs.
|
979 |
|
980 |
env->CP0_VPEControl = newval; |
981 |
} |
982 |
|
983 |
void helper_mtc0_vpeconf0 (target_ulong arg1)
|
984 |
{ |
985 |
uint32_t mask = 0;
|
986 |
uint32_t newval; |
987 |
|
988 |
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { |
989 |
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) |
990 |
mask |= (0xff << CP0VPEC0_XTC);
|
991 |
mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); |
992 |
} |
993 |
newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask); |
994 |
|
995 |
// TODO: TC exclusive handling due to ERL/EXL.
|
996 |
|
997 |
env->CP0_VPEConf0 = newval; |
998 |
} |
999 |
|
1000 |
void helper_mtc0_vpeconf1 (target_ulong arg1)
|
1001 |
{ |
1002 |
uint32_t mask = 0;
|
1003 |
uint32_t newval; |
1004 |
|
1005 |
if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
1006 |
mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | |
1007 |
(0xff << CP0VPEC1_NCP1);
|
1008 |
newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask); |
1009 |
|
1010 |
/* UDI not implemented. */
|
1011 |
/* CP2 not implemented. */
|
1012 |
|
1013 |
// TODO: Handle FPU (CP1) binding.
|
1014 |
|
1015 |
env->CP0_VPEConf1 = newval; |
1016 |
} |
1017 |
|
1018 |
void helper_mtc0_yqmask (target_ulong arg1)
|
1019 |
{ |
1020 |
/* Yield qualifier inputs not implemented. */
|
1021 |
env->CP0_YQMask = 0x00000000;
|
1022 |
} |
1023 |
|
1024 |
void helper_mtc0_vpeopt (target_ulong arg1)
|
1025 |
{ |
1026 |
env->CP0_VPEOpt = arg1 & 0x0000ffff;
|
1027 |
} |
1028 |
|
1029 |
void helper_mtc0_entrylo0 (target_ulong arg1)
|
1030 |
{ |
1031 |
/* Large physaddr (PABITS) not implemented */
|
1032 |
/* 1k pages not implemented */
|
1033 |
env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
|
1034 |
} |
1035 |
|
1036 |
void helper_mtc0_tcstatus (target_ulong arg1)
|
1037 |
{ |
1038 |
uint32_t mask = env->CP0_TCStatus_rw_bitmask; |
1039 |
uint32_t newval; |
1040 |
|
1041 |
newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask); |
1042 |
|
1043 |
// TODO: Sync with CP0_Status.
|
1044 |
|
1045 |
env->active_tc.CP0_TCStatus = newval; |
1046 |
} |
1047 |
|
1048 |
void helper_mttc0_tcstatus (target_ulong arg1)
|
1049 |
{ |
1050 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1051 |
|
1052 |
// TODO: Sync with CP0_Status.
|
1053 |
|
1054 |
if (other_tc == env->current_tc)
|
1055 |
env->active_tc.CP0_TCStatus = arg1; |
1056 |
else
|
1057 |
env->tcs[other_tc].CP0_TCStatus = arg1; |
1058 |
} |
1059 |
|
1060 |
void helper_mtc0_tcbind (target_ulong arg1)
|
1061 |
{ |
1062 |
uint32_t mask = (1 << CP0TCBd_TBE);
|
1063 |
uint32_t newval; |
1064 |
|
1065 |
if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
1066 |
mask |= (1 << CP0TCBd_CurVPE);
|
1067 |
newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); |
1068 |
env->active_tc.CP0_TCBind = newval; |
1069 |
} |
1070 |
|
1071 |
void helper_mttc0_tcbind (target_ulong arg1)
|
1072 |
{ |
1073 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1074 |
uint32_t mask = (1 << CP0TCBd_TBE);
|
1075 |
uint32_t newval; |
1076 |
|
1077 |
if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
1078 |
mask |= (1 << CP0TCBd_CurVPE);
|
1079 |
if (other_tc == env->current_tc) {
|
1080 |
newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); |
1081 |
env->active_tc.CP0_TCBind = newval; |
1082 |
} else {
|
1083 |
newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask); |
1084 |
env->tcs[other_tc].CP0_TCBind = newval; |
1085 |
} |
1086 |
} |
1087 |
|
1088 |
void helper_mtc0_tcrestart (target_ulong arg1)
|
1089 |
{ |
1090 |
env->active_tc.PC = arg1; |
1091 |
env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
|
1092 |
env->lladdr = 0ULL;
|
1093 |
/* MIPS16 not implemented. */
|
1094 |
} |
1095 |
|
1096 |
void helper_mttc0_tcrestart (target_ulong arg1)
|
1097 |
{ |
1098 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1099 |
|
1100 |
if (other_tc == env->current_tc) {
|
1101 |
env->active_tc.PC = arg1; |
1102 |
env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
|
1103 |
env->lladdr = 0ULL;
|
1104 |
/* MIPS16 not implemented. */
|
1105 |
} else {
|
1106 |
env->tcs[other_tc].PC = arg1; |
1107 |
env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
|
1108 |
env->lladdr = 0ULL;
|
1109 |
/* MIPS16 not implemented. */
|
1110 |
} |
1111 |
} |
1112 |
|
1113 |
void helper_mtc0_tchalt (target_ulong arg1)
|
1114 |
{ |
1115 |
env->active_tc.CP0_TCHalt = arg1 & 0x1;
|
1116 |
|
1117 |
// TODO: Halt TC / Restart (if allocated+active) TC.
|
1118 |
} |
1119 |
|
1120 |
void helper_mttc0_tchalt (target_ulong arg1)
|
1121 |
{ |
1122 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1123 |
|
1124 |
// TODO: Halt TC / Restart (if allocated+active) TC.
|
1125 |
|
1126 |
if (other_tc == env->current_tc)
|
1127 |
env->active_tc.CP0_TCHalt = arg1; |
1128 |
else
|
1129 |
env->tcs[other_tc].CP0_TCHalt = arg1; |
1130 |
} |
1131 |
|
1132 |
void helper_mtc0_tccontext (target_ulong arg1)
|
1133 |
{ |
1134 |
env->active_tc.CP0_TCContext = arg1; |
1135 |
} |
1136 |
|
1137 |
void helper_mttc0_tccontext (target_ulong arg1)
|
1138 |
{ |
1139 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1140 |
|
1141 |
if (other_tc == env->current_tc)
|
1142 |
env->active_tc.CP0_TCContext = arg1; |
1143 |
else
|
1144 |
env->tcs[other_tc].CP0_TCContext = arg1; |
1145 |
} |
1146 |
|
1147 |
void helper_mtc0_tcschedule (target_ulong arg1)
|
1148 |
{ |
1149 |
env->active_tc.CP0_TCSchedule = arg1; |
1150 |
} |
1151 |
|
1152 |
void helper_mttc0_tcschedule (target_ulong arg1)
|
1153 |
{ |
1154 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1155 |
|
1156 |
if (other_tc == env->current_tc)
|
1157 |
env->active_tc.CP0_TCSchedule = arg1; |
1158 |
else
|
1159 |
env->tcs[other_tc].CP0_TCSchedule = arg1; |
1160 |
} |
1161 |
|
1162 |
void helper_mtc0_tcschefback (target_ulong arg1)
|
1163 |
{ |
1164 |
env->active_tc.CP0_TCScheFBack = arg1; |
1165 |
} |
1166 |
|
1167 |
void helper_mttc0_tcschefback (target_ulong arg1)
|
1168 |
{ |
1169 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1170 |
|
1171 |
if (other_tc == env->current_tc)
|
1172 |
env->active_tc.CP0_TCScheFBack = arg1; |
1173 |
else
|
1174 |
env->tcs[other_tc].CP0_TCScheFBack = arg1; |
1175 |
} |
1176 |
|
1177 |
void helper_mtc0_entrylo1 (target_ulong arg1)
|
1178 |
{ |
1179 |
/* Large physaddr (PABITS) not implemented */
|
1180 |
/* 1k pages not implemented */
|
1181 |
env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
|
1182 |
} |
1183 |
|
1184 |
void helper_mtc0_context (target_ulong arg1)
|
1185 |
{ |
1186 |
env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF); |
1187 |
} |
1188 |
|
1189 |
void helper_mtc0_pagemask (target_ulong arg1)
|
1190 |
{ |
1191 |
/* 1k pages not implemented */
|
1192 |
env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); |
1193 |
} |
1194 |
|
1195 |
void helper_mtc0_pagegrain (target_ulong arg1)
|
1196 |
{ |
1197 |
/* SmartMIPS not implemented */
|
1198 |
/* Large physaddr (PABITS) not implemented */
|
1199 |
/* 1k pages not implemented */
|
1200 |
env->CP0_PageGrain = 0;
|
1201 |
} |
1202 |
|
1203 |
void helper_mtc0_wired (target_ulong arg1)
|
1204 |
{ |
1205 |
env->CP0_Wired = arg1 % env->tlb->nb_tlb; |
1206 |
} |
1207 |
|
1208 |
void helper_mtc0_srsconf0 (target_ulong arg1)
|
1209 |
{ |
1210 |
env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask; |
1211 |
} |
1212 |
|
1213 |
void helper_mtc0_srsconf1 (target_ulong arg1)
|
1214 |
{ |
1215 |
env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask; |
1216 |
} |
1217 |
|
1218 |
void helper_mtc0_srsconf2 (target_ulong arg1)
|
1219 |
{ |
1220 |
env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask; |
1221 |
} |
1222 |
|
1223 |
void helper_mtc0_srsconf3 (target_ulong arg1)
|
1224 |
{ |
1225 |
env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask; |
1226 |
} |
1227 |
|
1228 |
void helper_mtc0_srsconf4 (target_ulong arg1)
|
1229 |
{ |
1230 |
env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask; |
1231 |
} |
1232 |
|
1233 |
void helper_mtc0_hwrena (target_ulong arg1)
|
1234 |
{ |
1235 |
env->CP0_HWREna = arg1 & 0x0000000F;
|
1236 |
} |
1237 |
|
1238 |
void helper_mtc0_count (target_ulong arg1)
|
1239 |
{ |
1240 |
cpu_mips_store_count(env, arg1); |
1241 |
} |
1242 |
|
1243 |
void helper_mtc0_entryhi (target_ulong arg1)
|
1244 |
{ |
1245 |
target_ulong old, val; |
1246 |
|
1247 |
/* 1k pages not implemented */
|
1248 |
val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF); |
1249 |
#if defined(TARGET_MIPS64)
|
1250 |
val &= env->SEGMask; |
1251 |
#endif
|
1252 |
old = env->CP0_EntryHi; |
1253 |
env->CP0_EntryHi = val; |
1254 |
if (env->CP0_Config3 & (1 << CP0C3_MT)) { |
1255 |
uint32_t tcst = env->active_tc.CP0_TCStatus & ~0xff;
|
1256 |
env->active_tc.CP0_TCStatus = tcst | (val & 0xff);
|
1257 |
} |
1258 |
/* If the ASID changes, flush qemu's TLB. */
|
1259 |
if ((old & 0xFF) != (val & 0xFF)) |
1260 |
cpu_mips_tlb_flush(env, 1);
|
1261 |
} |
1262 |
|
1263 |
void helper_mttc0_entryhi(target_ulong arg1)
|
1264 |
{ |
1265 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1266 |
int32_t tcstatus; |
1267 |
|
1268 |
env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (arg1 & ~0xff); |
1269 |
if (other_tc == env->current_tc) {
|
1270 |
tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (arg1 & 0xff); |
1271 |
env->active_tc.CP0_TCStatus = tcstatus; |
1272 |
} else {
|
1273 |
tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (arg1 & 0xff); |
1274 |
env->tcs[other_tc].CP0_TCStatus = tcstatus; |
1275 |
} |
1276 |
} |
1277 |
|
1278 |
void helper_mtc0_compare (target_ulong arg1)
|
1279 |
{ |
1280 |
cpu_mips_store_compare(env, arg1); |
1281 |
} |
1282 |
|
1283 |
void helper_mtc0_status (target_ulong arg1)
|
1284 |
{ |
1285 |
uint32_t val, old; |
1286 |
uint32_t mask = env->CP0_Status_rw_bitmask; |
1287 |
|
1288 |
val = arg1 & mask; |
1289 |
old = env->CP0_Status; |
1290 |
env->CP0_Status = (env->CP0_Status & ~mask) | val; |
1291 |
compute_hflags(env); |
1292 |
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
|
1293 |
qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
|
1294 |
old, old & env->CP0_Cause & CP0Ca_IP_mask, |
1295 |
val, val & env->CP0_Cause & CP0Ca_IP_mask, |
1296 |
env->CP0_Cause); |
1297 |
switch (env->hflags & MIPS_HFLAG_KSU) {
|
1298 |
case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; |
1299 |
case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; |
1300 |
case MIPS_HFLAG_KM: qemu_log("\n"); break; |
1301 |
default: cpu_abort(env, "Invalid MMU mode!\n"); break; |
1302 |
} |
1303 |
} |
1304 |
} |
1305 |
|
1306 |
void helper_mttc0_status(target_ulong arg1)
|
1307 |
{ |
1308 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1309 |
int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus; |
1310 |
|
1311 |
env->CP0_Status = arg1 & ~0xf1000018;
|
1312 |
tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (arg1 & (0xf << CP0St_CU0)); |
1313 |
tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((arg1 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX)); |
1314 |
tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((arg1 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU)); |
1315 |
if (other_tc == env->current_tc)
|
1316 |
env->active_tc.CP0_TCStatus = tcstatus; |
1317 |
else
|
1318 |
env->tcs[other_tc].CP0_TCStatus = tcstatus; |
1319 |
} |
1320 |
|
1321 |
void helper_mtc0_intctl (target_ulong arg1)
|
1322 |
{ |
1323 |
/* vectored interrupts not implemented, no performance counters. */
|
1324 |
env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (arg1 & 0x000002e0); |
1325 |
} |
1326 |
|
1327 |
void helper_mtc0_srsctl (target_ulong arg1)
|
1328 |
{ |
1329 |
uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); |
1330 |
env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask); |
1331 |
} |
1332 |
|
1333 |
void helper_mtc0_cause (target_ulong arg1)
|
1334 |
{ |
1335 |
uint32_t mask = 0x00C00300;
|
1336 |
uint32_t old = env->CP0_Cause; |
1337 |
int i;
|
1338 |
|
1339 |
if (env->insn_flags & ISA_MIPS32R2)
|
1340 |
mask |= 1 << CP0Ca_DC;
|
1341 |
|
1342 |
env->CP0_Cause = (env->CP0_Cause & ~mask) | (arg1 & mask); |
1343 |
|
1344 |
if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { |
1345 |
if (env->CP0_Cause & (1 << CP0Ca_DC)) |
1346 |
cpu_mips_stop_count(env); |
1347 |
else
|
1348 |
cpu_mips_start_count(env); |
1349 |
} |
1350 |
|
1351 |
/* Set/reset software interrupts */
|
1352 |
for (i = 0 ; i < 2 ; i++) { |
1353 |
if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { |
1354 |
cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
|
1355 |
} |
1356 |
} |
1357 |
} |
1358 |
|
1359 |
void helper_mtc0_ebase (target_ulong arg1)
|
1360 |
{ |
1361 |
/* vectored interrupts not implemented */
|
1362 |
env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000); |
1363 |
} |
1364 |
|
1365 |
void helper_mtc0_config0 (target_ulong arg1)
|
1366 |
{ |
1367 |
env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007); |
1368 |
} |
1369 |
|
1370 |
void helper_mtc0_config2 (target_ulong arg1)
|
1371 |
{ |
1372 |
/* tertiary/secondary caches not implemented */
|
1373 |
env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
|
1374 |
} |
1375 |
|
1376 |
void helper_mtc0_lladdr (target_ulong arg1)
|
1377 |
{ |
1378 |
target_long mask = env->CP0_LLAddr_rw_bitmask; |
1379 |
arg1 = arg1 << env->CP0_LLAddr_shift; |
1380 |
env->lladdr = (env->lladdr & ~mask) | (arg1 & mask); |
1381 |
} |
1382 |
|
1383 |
void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel)
|
1384 |
{ |
1385 |
/* Watch exceptions for instructions, data loads, data stores
|
1386 |
not implemented. */
|
1387 |
env->CP0_WatchLo[sel] = (arg1 & ~0x7);
|
1388 |
} |
1389 |
|
1390 |
void helper_mtc0_watchhi (target_ulong arg1, uint32_t sel)
|
1391 |
{ |
1392 |
env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
|
1393 |
env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
|
1394 |
} |
1395 |
|
1396 |
void helper_mtc0_xcontext (target_ulong arg1)
|
1397 |
{ |
1398 |
target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; |
1399 |
env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask); |
1400 |
} |
1401 |
|
1402 |
void helper_mtc0_framemask (target_ulong arg1)
|
1403 |
{ |
1404 |
env->CP0_Framemask = arg1; /* XXX */
|
1405 |
} |
1406 |
|
1407 |
void helper_mtc0_debug (target_ulong arg1)
|
1408 |
{ |
1409 |
env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); |
1410 |
if (arg1 & (1 << CP0DB_DM)) |
1411 |
env->hflags |= MIPS_HFLAG_DM; |
1412 |
else
|
1413 |
env->hflags &= ~MIPS_HFLAG_DM; |
1414 |
} |
1415 |
|
1416 |
void helper_mttc0_debug(target_ulong arg1)
|
1417 |
{ |
1418 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1419 |
uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); |
1420 |
|
1421 |
/* XXX: Might be wrong, check with EJTAG spec. */
|
1422 |
if (other_tc == env->current_tc)
|
1423 |
env->active_tc.CP0_Debug_tcstatus = val; |
1424 |
else
|
1425 |
env->tcs[other_tc].CP0_Debug_tcstatus = val; |
1426 |
env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
1427 |
(arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
1428 |
} |
1429 |
|
1430 |
void helper_mtc0_performance0 (target_ulong arg1)
|
1431 |
{ |
1432 |
env->CP0_Performance0 = arg1 & 0x000007ff;
|
1433 |
} |
1434 |
|
1435 |
void helper_mtc0_taglo (target_ulong arg1)
|
1436 |
{ |
1437 |
env->CP0_TagLo = arg1 & 0xFFFFFCF6;
|
1438 |
} |
1439 |
|
1440 |
void helper_mtc0_datalo (target_ulong arg1)
|
1441 |
{ |
1442 |
env->CP0_DataLo = arg1; /* XXX */
|
1443 |
} |
1444 |
|
1445 |
void helper_mtc0_taghi (target_ulong arg1)
|
1446 |
{ |
1447 |
env->CP0_TagHi = arg1; /* XXX */
|
1448 |
} |
1449 |
|
1450 |
void helper_mtc0_datahi (target_ulong arg1)
|
1451 |
{ |
1452 |
env->CP0_DataHi = arg1; /* XXX */
|
1453 |
} |
1454 |
|
1455 |
/* MIPS MT functions */
|
1456 |
target_ulong helper_mftgpr(uint32_t sel) |
1457 |
{ |
1458 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1459 |
|
1460 |
if (other_tc == env->current_tc)
|
1461 |
return env->active_tc.gpr[sel];
|
1462 |
else
|
1463 |
return env->tcs[other_tc].gpr[sel];
|
1464 |
} |
1465 |
|
1466 |
target_ulong helper_mftlo(uint32_t sel) |
1467 |
{ |
1468 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1469 |
|
1470 |
if (other_tc == env->current_tc)
|
1471 |
return env->active_tc.LO[sel];
|
1472 |
else
|
1473 |
return env->tcs[other_tc].LO[sel];
|
1474 |
} |
1475 |
|
1476 |
target_ulong helper_mfthi(uint32_t sel) |
1477 |
{ |
1478 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1479 |
|
1480 |
if (other_tc == env->current_tc)
|
1481 |
return env->active_tc.HI[sel];
|
1482 |
else
|
1483 |
return env->tcs[other_tc].HI[sel];
|
1484 |
} |
1485 |
|
1486 |
target_ulong helper_mftacx(uint32_t sel) |
1487 |
{ |
1488 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1489 |
|
1490 |
if (other_tc == env->current_tc)
|
1491 |
return env->active_tc.ACX[sel];
|
1492 |
else
|
1493 |
return env->tcs[other_tc].ACX[sel];
|
1494 |
} |
1495 |
|
1496 |
target_ulong helper_mftdsp(void)
|
1497 |
{ |
1498 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1499 |
|
1500 |
if (other_tc == env->current_tc)
|
1501 |
return env->active_tc.DSPControl;
|
1502 |
else
|
1503 |
return env->tcs[other_tc].DSPControl;
|
1504 |
} |
1505 |
|
1506 |
void helper_mttgpr(target_ulong arg1, uint32_t sel)
|
1507 |
{ |
1508 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1509 |
|
1510 |
if (other_tc == env->current_tc)
|
1511 |
env->active_tc.gpr[sel] = arg1; |
1512 |
else
|
1513 |
env->tcs[other_tc].gpr[sel] = arg1; |
1514 |
} |
1515 |
|
1516 |
void helper_mttlo(target_ulong arg1, uint32_t sel)
|
1517 |
{ |
1518 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1519 |
|
1520 |
if (other_tc == env->current_tc)
|
1521 |
env->active_tc.LO[sel] = arg1; |
1522 |
else
|
1523 |
env->tcs[other_tc].LO[sel] = arg1; |
1524 |
} |
1525 |
|
1526 |
void helper_mtthi(target_ulong arg1, uint32_t sel)
|
1527 |
{ |
1528 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1529 |
|
1530 |
if (other_tc == env->current_tc)
|
1531 |
env->active_tc.HI[sel] = arg1; |
1532 |
else
|
1533 |
env->tcs[other_tc].HI[sel] = arg1; |
1534 |
} |
1535 |
|
1536 |
void helper_mttacx(target_ulong arg1, uint32_t sel)
|
1537 |
{ |
1538 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1539 |
|
1540 |
if (other_tc == env->current_tc)
|
1541 |
env->active_tc.ACX[sel] = arg1; |
1542 |
else
|
1543 |
env->tcs[other_tc].ACX[sel] = arg1; |
1544 |
} |
1545 |
|
1546 |
void helper_mttdsp(target_ulong arg1)
|
1547 |
{ |
1548 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
1549 |
|
1550 |
if (other_tc == env->current_tc)
|
1551 |
env->active_tc.DSPControl = arg1; |
1552 |
else
|
1553 |
env->tcs[other_tc].DSPControl = arg1; |
1554 |
} |
1555 |
|
1556 |
/* MIPS MT functions */
|
1557 |
target_ulong helper_dmt(void)
|
1558 |
{ |
1559 |
// TODO
|
1560 |
return 0; |
1561 |
} |
1562 |
|
1563 |
target_ulong helper_emt(void)
|
1564 |
{ |
1565 |
// TODO
|
1566 |
return 0; |
1567 |
} |
1568 |
|
1569 |
target_ulong helper_dvpe(void)
|
1570 |
{ |
1571 |
// TODO
|
1572 |
return 0; |
1573 |
} |
1574 |
|
1575 |
target_ulong helper_evpe(void)
|
1576 |
{ |
1577 |
// TODO
|
1578 |
return 0; |
1579 |
} |
1580 |
#endif /* !CONFIG_USER_ONLY */ |
1581 |
|
1582 |
void helper_fork(target_ulong arg1, target_ulong arg2)
|
1583 |
{ |
1584 |
// arg1 = rt, arg2 = rs
|
1585 |
arg1 = 0;
|
1586 |
// TODO: store to TC register
|
1587 |
} |
1588 |
|
1589 |
target_ulong helper_yield(target_ulong arg) |
1590 |
{ |
1591 |
target_long arg1 = arg; |
1592 |
|
1593 |
if (arg1 < 0) { |
1594 |
/* No scheduling policy implemented. */
|
1595 |
if (arg1 != -2) { |
1596 |
if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && |
1597 |
env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
|
1598 |
env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
1599 |
env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
|
1600 |
helper_raise_exception(EXCP_THREAD); |
1601 |
} |
1602 |
} |
1603 |
} else if (arg1 == 0) { |
1604 |
if (0 /* TODO: TC underflow */) { |
1605 |
env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
1606 |
helper_raise_exception(EXCP_THREAD); |
1607 |
} else {
|
1608 |
// TODO: Deallocate TC
|
1609 |
} |
1610 |
} else if (arg1 > 0) { |
1611 |
/* Yield qualifier inputs not implemented. */
|
1612 |
env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
1613 |
env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
|
1614 |
helper_raise_exception(EXCP_THREAD); |
1615 |
} |
1616 |
return env->CP0_YQMask;
|
1617 |
} |
1618 |
|
1619 |
#ifndef CONFIG_USER_ONLY
|
1620 |
/* TLB management */
|
1621 |
static void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
1622 |
{ |
1623 |
/* Flush qemu's TLB and discard all shadowed entries. */
|
1624 |
tlb_flush (env, flush_global); |
1625 |
env->tlb->tlb_in_use = env->tlb->nb_tlb; |
1626 |
} |
1627 |
|
1628 |
static void r4k_mips_tlb_flush_extra (CPUState *env, int first) |
1629 |
{ |
1630 |
/* Discard entries from env->tlb[first] onwards. */
|
1631 |
while (env->tlb->tlb_in_use > first) {
|
1632 |
r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
|
1633 |
} |
1634 |
} |
1635 |
|
1636 |
static void r4k_fill_tlb (int idx) |
1637 |
{ |
1638 |
r4k_tlb_t *tlb; |
1639 |
|
1640 |
/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
|
1641 |
tlb = &env->tlb->mmu.r4k.tlb[idx]; |
1642 |
tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
|
1643 |
#if defined(TARGET_MIPS64)
|
1644 |
tlb->VPN &= env->SEGMask; |
1645 |
#endif
|
1646 |
tlb->ASID = env->CP0_EntryHi & 0xFF;
|
1647 |
tlb->PageMask = env->CP0_PageMask; |
1648 |
tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
|
1649 |
tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
1650 |
tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; |
1651 |
tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; |
1652 |
tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
1653 |
tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
1654 |
tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; |
1655 |
tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; |
1656 |
tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
1657 |
} |
1658 |
|
1659 |
void r4k_helper_tlbwi (void) |
1660 |
{ |
1661 |
int idx;
|
1662 |
|
1663 |
idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
|
1664 |
|
1665 |
/* Discard cached TLB entries. We could avoid doing this if the
|
1666 |
tlbwi is just upgrading access permissions on the current entry;
|
1667 |
that might be a further win. */
|
1668 |
r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb); |
1669 |
|
1670 |
r4k_invalidate_tlb(env, idx, 0);
|
1671 |
r4k_fill_tlb(idx); |
1672 |
} |
1673 |
|
1674 |
void r4k_helper_tlbwr (void) |
1675 |
{ |
1676 |
int r = cpu_mips_get_random(env);
|
1677 |
|
1678 |
r4k_invalidate_tlb(env, r, 1);
|
1679 |
r4k_fill_tlb(r); |
1680 |
} |
1681 |
|
1682 |
void r4k_helper_tlbp (void) |
1683 |
{ |
1684 |
r4k_tlb_t *tlb; |
1685 |
target_ulong mask; |
1686 |
target_ulong tag; |
1687 |
target_ulong VPN; |
1688 |
uint8_t ASID; |
1689 |
int i;
|
1690 |
|
1691 |
ASID = env->CP0_EntryHi & 0xFF;
|
1692 |
for (i = 0; i < env->tlb->nb_tlb; i++) { |
1693 |
tlb = &env->tlb->mmu.r4k.tlb[i]; |
1694 |
/* 1k pages are not supported. */
|
1695 |
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
1696 |
tag = env->CP0_EntryHi & ~mask; |
1697 |
VPN = tlb->VPN & ~mask; |
1698 |
/* Check ASID, virtual page number & size */
|
1699 |
if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
1700 |
/* TLB match */
|
1701 |
env->CP0_Index = i; |
1702 |
break;
|
1703 |
} |
1704 |
} |
1705 |
if (i == env->tlb->nb_tlb) {
|
1706 |
/* No match. Discard any shadow entries, if any of them match. */
|
1707 |
for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
|
1708 |
tlb = &env->tlb->mmu.r4k.tlb[i]; |
1709 |
/* 1k pages are not supported. */
|
1710 |
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
1711 |
tag = env->CP0_EntryHi & ~mask; |
1712 |
VPN = tlb->VPN & ~mask; |
1713 |
/* Check ASID, virtual page number & size */
|
1714 |
if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
1715 |
r4k_mips_tlb_flush_extra (env, i); |
1716 |
break;
|
1717 |
} |
1718 |
} |
1719 |
|
1720 |
env->CP0_Index |= 0x80000000;
|
1721 |
} |
1722 |
} |
1723 |
|
1724 |
void r4k_helper_tlbr (void) |
1725 |
{ |
1726 |
r4k_tlb_t *tlb; |
1727 |
uint8_t ASID; |
1728 |
int idx;
|
1729 |
|
1730 |
ASID = env->CP0_EntryHi & 0xFF;
|
1731 |
idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
|
1732 |
tlb = &env->tlb->mmu.r4k.tlb[idx]; |
1733 |
|
1734 |
/* If this will change the current ASID, flush qemu's TLB. */
|
1735 |
if (ASID != tlb->ASID)
|
1736 |
cpu_mips_tlb_flush (env, 1);
|
1737 |
|
1738 |
r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); |
1739 |
|
1740 |
env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
1741 |
env->CP0_PageMask = tlb->PageMask; |
1742 |
env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
1743 |
(tlb->C0 << 3) | (tlb->PFN[0] >> 6); |
1744 |
env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | |
1745 |
(tlb->C1 << 3) | (tlb->PFN[1] >> 6); |
1746 |
} |
1747 |
|
1748 |
void helper_tlbwi(void) |
1749 |
{ |
1750 |
env->tlb->helper_tlbwi(); |
1751 |
} |
1752 |
|
1753 |
void helper_tlbwr(void) |
1754 |
{ |
1755 |
env->tlb->helper_tlbwr(); |
1756 |
} |
1757 |
|
1758 |
void helper_tlbp(void) |
1759 |
{ |
1760 |
env->tlb->helper_tlbp(); |
1761 |
} |
1762 |
|
1763 |
void helper_tlbr(void) |
1764 |
{ |
1765 |
env->tlb->helper_tlbr(); |
1766 |
} |
1767 |
|
1768 |
/* Specials */
|
1769 |
target_ulong helper_di (void)
|
1770 |
{ |
1771 |
target_ulong t0 = env->CP0_Status; |
1772 |
|
1773 |
env->CP0_Status = t0 & ~(1 << CP0St_IE);
|
1774 |
return t0;
|
1775 |
} |
1776 |
|
1777 |
target_ulong helper_ei (void)
|
1778 |
{ |
1779 |
target_ulong t0 = env->CP0_Status; |
1780 |
|
1781 |
env->CP0_Status = t0 | (1 << CP0St_IE);
|
1782 |
return t0;
|
1783 |
} |
1784 |
|
1785 |
static void debug_pre_eret (void) |
1786 |
{ |
1787 |
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
|
1788 |
qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
1789 |
env->active_tc.PC, env->CP0_EPC); |
1790 |
if (env->CP0_Status & (1 << CP0St_ERL)) |
1791 |
qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
1792 |
if (env->hflags & MIPS_HFLAG_DM)
|
1793 |
qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
1794 |
qemu_log("\n");
|
1795 |
} |
1796 |
} |
1797 |
|
1798 |
static void debug_post_eret (void) |
1799 |
{ |
1800 |
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
|
1801 |
qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
1802 |
env->active_tc.PC, env->CP0_EPC); |
1803 |
if (env->CP0_Status & (1 << CP0St_ERL)) |
1804 |
qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
1805 |
if (env->hflags & MIPS_HFLAG_DM)
|
1806 |
qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
1807 |
switch (env->hflags & MIPS_HFLAG_KSU) {
|
1808 |
case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; |
1809 |
case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; |
1810 |
case MIPS_HFLAG_KM: qemu_log("\n"); break; |
1811 |
default: cpu_abort(env, "Invalid MMU mode!\n"); break; |
1812 |
} |
1813 |
} |
1814 |
} |
1815 |
|
1816 |
static void set_pc (target_ulong error_pc) |
1817 |
{ |
1818 |
env->active_tc.PC = error_pc & ~(target_ulong)1;
|
1819 |
if (error_pc & 1) { |
1820 |
env->hflags |= MIPS_HFLAG_M16; |
1821 |
} else {
|
1822 |
env->hflags &= ~(MIPS_HFLAG_M16); |
1823 |
} |
1824 |
} |
1825 |
|
1826 |
void helper_eret (void) |
1827 |
{ |
1828 |
debug_pre_eret(); |
1829 |
if (env->CP0_Status & (1 << CP0St_ERL)) { |
1830 |
set_pc(env->CP0_ErrorEPC); |
1831 |
env->CP0_Status &= ~(1 << CP0St_ERL);
|
1832 |
} else {
|
1833 |
set_pc(env->CP0_EPC); |
1834 |
env->CP0_Status &= ~(1 << CP0St_EXL);
|
1835 |
} |
1836 |
compute_hflags(env); |
1837 |
debug_post_eret(); |
1838 |
env->lladdr = 1;
|
1839 |
} |
1840 |
|
1841 |
void helper_deret (void) |
1842 |
{ |
1843 |
debug_pre_eret(); |
1844 |
set_pc(env->CP0_DEPC); |
1845 |
|
1846 |
env->hflags &= MIPS_HFLAG_DM; |
1847 |
compute_hflags(env); |
1848 |
debug_post_eret(); |
1849 |
env->lladdr = 1;
|
1850 |
} |
1851 |
#endif /* !CONFIG_USER_ONLY */ |
1852 |
|
1853 |
target_ulong helper_rdhwr_cpunum(void)
|
1854 |
{ |
1855 |
if ((env->hflags & MIPS_HFLAG_CP0) ||
|
1856 |
(env->CP0_HWREna & (1 << 0))) |
1857 |
return env->CP0_EBase & 0x3ff; |
1858 |
else
|
1859 |
helper_raise_exception(EXCP_RI); |
1860 |
|
1861 |
return 0; |
1862 |
} |
1863 |
|
1864 |
target_ulong helper_rdhwr_synci_step(void)
|
1865 |
{ |
1866 |
if ((env->hflags & MIPS_HFLAG_CP0) ||
|
1867 |
(env->CP0_HWREna & (1 << 1))) |
1868 |
return env->SYNCI_Step;
|
1869 |
else
|
1870 |
helper_raise_exception(EXCP_RI); |
1871 |
|
1872 |
return 0; |
1873 |
} |
1874 |
|
1875 |
target_ulong helper_rdhwr_cc(void)
|
1876 |
{ |
1877 |
if ((env->hflags & MIPS_HFLAG_CP0) ||
|
1878 |
(env->CP0_HWREna & (1 << 2))) |
1879 |
return env->CP0_Count;
|
1880 |
else
|
1881 |
helper_raise_exception(EXCP_RI); |
1882 |
|
1883 |
return 0; |
1884 |
} |
1885 |
|
1886 |
target_ulong helper_rdhwr_ccres(void)
|
1887 |
{ |
1888 |
if ((env->hflags & MIPS_HFLAG_CP0) ||
|
1889 |
(env->CP0_HWREna & (1 << 3))) |
1890 |
return env->CCRes;
|
1891 |
else
|
1892 |
helper_raise_exception(EXCP_RI); |
1893 |
|
1894 |
return 0; |
1895 |
} |
1896 |
|
1897 |
void helper_pmon (int function) |
1898 |
{ |
1899 |
function /= 2;
|
1900 |
switch (function) {
|
1901 |
case 2: /* TODO: char inbyte(int waitflag); */ |
1902 |
if (env->active_tc.gpr[4] == 0) |
1903 |
env->active_tc.gpr[2] = -1; |
1904 |
/* Fall through */
|
1905 |
case 11: /* TODO: char inbyte (void); */ |
1906 |
env->active_tc.gpr[2] = -1; |
1907 |
break;
|
1908 |
case 3: |
1909 |
case 12: |
1910 |
printf("%c", (char)(env->active_tc.gpr[4] & 0xFF)); |
1911 |
break;
|
1912 |
case 17: |
1913 |
break;
|
1914 |
case 158: |
1915 |
{ |
1916 |
unsigned char *fmt = (void *)(unsigned long)env->active_tc.gpr[4]; |
1917 |
printf("%s", fmt);
|
1918 |
} |
1919 |
break;
|
1920 |
} |
1921 |
} |
1922 |
|
1923 |
void helper_wait (void) |
1924 |
{ |
1925 |
env->halted = 1;
|
1926 |
helper_raise_exception(EXCP_HLT); |
1927 |
} |
1928 |
|
1929 |
#if !defined(CONFIG_USER_ONLY)
|
1930 |
|
1931 |
static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); |
1932 |
|
1933 |
#define MMUSUFFIX _mmu
|
1934 |
#define ALIGNED_ONLY
|
1935 |
|
1936 |
#define SHIFT 0 |
1937 |
#include "softmmu_template.h" |
1938 |
|
1939 |
#define SHIFT 1 |
1940 |
#include "softmmu_template.h" |
1941 |
|
1942 |
#define SHIFT 2 |
1943 |
#include "softmmu_template.h" |
1944 |
|
1945 |
#define SHIFT 3 |
1946 |
#include "softmmu_template.h" |
1947 |
|
1948 |
static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) |
1949 |
{ |
1950 |
env->CP0_BadVAddr = addr; |
1951 |
do_restore_state (retaddr); |
1952 |
helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
|
1953 |
} |
1954 |
|
1955 |
void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
1956 |
{ |
1957 |
TranslationBlock *tb; |
1958 |
CPUState *saved_env; |
1959 |
unsigned long pc; |
1960 |
int ret;
|
1961 |
|
1962 |
/* XXX: hack to restore env in all cases, even if not called from
|
1963 |
generated code */
|
1964 |
saved_env = env; |
1965 |
env = cpu_single_env; |
1966 |
ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
|
1967 |
if (ret) {
|
1968 |
if (retaddr) {
|
1969 |
/* now we have a real cpu fault */
|
1970 |
pc = (unsigned long)retaddr; |
1971 |
tb = tb_find_pc(pc); |
1972 |
if (tb) {
|
1973 |
/* the PC is inside the translated code. It means that we have
|
1974 |
a virtual CPU fault */
|
1975 |
cpu_restore_state(tb, env, pc, NULL);
|
1976 |
} |
1977 |
} |
1978 |
helper_raise_exception_err(env->exception_index, env->error_code); |
1979 |
} |
1980 |
env = saved_env; |
1981 |
} |
1982 |
|
1983 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
1984 |
int unused, int size) |
1985 |
{ |
1986 |
if (is_exec)
|
1987 |
helper_raise_exception(EXCP_IBE); |
1988 |
else
|
1989 |
helper_raise_exception(EXCP_DBE); |
1990 |
} |
1991 |
#endif /* !CONFIG_USER_ONLY */ |
1992 |
|
1993 |
/* Complex FPU operations which may need stack space. */
|
1994 |
|
1995 |
#define FLOAT_ONE32 make_float32(0x3f8 << 20) |
1996 |
#define FLOAT_ONE64 make_float64(0x3ffULL << 52) |
1997 |
#define FLOAT_TWO32 make_float32(1 << 30) |
1998 |
#define FLOAT_TWO64 make_float64(1ULL << 62) |
1999 |
#define FLOAT_QNAN32 0x7fbfffff |
2000 |
#define FLOAT_QNAN64 0x7ff7ffffffffffffULL |
2001 |
#define FLOAT_SNAN32 0x7fffffff |
2002 |
#define FLOAT_SNAN64 0x7fffffffffffffffULL |
2003 |
|
2004 |
/* convert MIPS rounding mode in FCR31 to IEEE library */
|
2005 |
static unsigned int ieee_rm[] = { |
2006 |
float_round_nearest_even, |
2007 |
float_round_to_zero, |
2008 |
float_round_up, |
2009 |
float_round_down |
2010 |
}; |
2011 |
|
2012 |
#define RESTORE_ROUNDING_MODE \
|
2013 |
set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
|
2014 |
|
2015 |
#define RESTORE_FLUSH_MODE \
|
2016 |
set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status); |
2017 |
|
2018 |
target_ulong helper_cfc1 (uint32_t reg) |
2019 |
{ |
2020 |
target_ulong arg1; |
2021 |
|
2022 |
switch (reg) {
|
2023 |
case 0: |
2024 |
arg1 = (int32_t)env->active_fpu.fcr0; |
2025 |
break;
|
2026 |
case 25: |
2027 |
arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1); |
2028 |
break;
|
2029 |
case 26: |
2030 |
arg1 = env->active_fpu.fcr31 & 0x0003f07c;
|
2031 |
break;
|
2032 |
case 28: |
2033 |
arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4); |
2034 |
break;
|
2035 |
default:
|
2036 |
arg1 = (int32_t)env->active_fpu.fcr31; |
2037 |
break;
|
2038 |
} |
2039 |
|
2040 |
return arg1;
|
2041 |
} |
2042 |
|
2043 |
void helper_ctc1 (target_ulong arg1, uint32_t reg)
|
2044 |
{ |
2045 |
switch(reg) {
|
2046 |
case 25: |
2047 |
if (arg1 & 0xffffff00) |
2048 |
return;
|
2049 |
env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) | |
2050 |
((arg1 & 0x1) << 23); |
2051 |
break;
|
2052 |
case 26: |
2053 |
if (arg1 & 0x007c0000) |
2054 |
return;
|
2055 |
env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c); |
2056 |
break;
|
2057 |
case 28: |
2058 |
if (arg1 & 0x007c0000) |
2059 |
return;
|
2060 |
env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) | |
2061 |
((arg1 & 0x4) << 22); |
2062 |
break;
|
2063 |
case 31: |
2064 |
if (arg1 & 0x007c0000) |
2065 |
return;
|
2066 |
env->active_fpu.fcr31 = arg1; |
2067 |
break;
|
2068 |
default:
|
2069 |
return;
|
2070 |
} |
2071 |
/* set rounding mode */
|
2072 |
RESTORE_ROUNDING_MODE; |
2073 |
/* set flush-to-zero mode */
|
2074 |
RESTORE_FLUSH_MODE; |
2075 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2076 |
if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31)) |
2077 |
helper_raise_exception(EXCP_FPE); |
2078 |
} |
2079 |
|
2080 |
static inline int ieee_ex_to_mips(int xcpt) |
2081 |
{ |
2082 |
int ret = 0; |
2083 |
if (xcpt) {
|
2084 |
if (xcpt & float_flag_invalid) {
|
2085 |
ret |= FP_INVALID; |
2086 |
} |
2087 |
if (xcpt & float_flag_overflow) {
|
2088 |
ret |= FP_OVERFLOW; |
2089 |
} |
2090 |
if (xcpt & float_flag_underflow) {
|
2091 |
ret |= FP_UNDERFLOW; |
2092 |
} |
2093 |
if (xcpt & float_flag_divbyzero) {
|
2094 |
ret |= FP_DIV0; |
2095 |
} |
2096 |
if (xcpt & float_flag_inexact) {
|
2097 |
ret |= FP_INEXACT; |
2098 |
} |
2099 |
} |
2100 |
return ret;
|
2101 |
} |
2102 |
|
2103 |
static inline void update_fcr31(void) |
2104 |
{ |
2105 |
int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
|
2106 |
|
2107 |
SET_FP_CAUSE(env->active_fpu.fcr31, tmp); |
2108 |
if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp)
|
2109 |
helper_raise_exception(EXCP_FPE); |
2110 |
else
|
2111 |
UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp); |
2112 |
} |
2113 |
|
2114 |
/* Float support.
|
2115 |
Single precition routines have a "s" suffix, double precision a
|
2116 |
"d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
|
2117 |
paired single lower "pl", paired single upper "pu". */
|
2118 |
|
2119 |
/* unary operations, modifying fp status */
|
2120 |
uint64_t helper_float_sqrt_d(uint64_t fdt0) |
2121 |
{ |
2122 |
return float64_sqrt(fdt0, &env->active_fpu.fp_status);
|
2123 |
} |
2124 |
|
2125 |
uint32_t helper_float_sqrt_s(uint32_t fst0) |
2126 |
{ |
2127 |
return float32_sqrt(fst0, &env->active_fpu.fp_status);
|
2128 |
} |
2129 |
|
2130 |
uint64_t helper_float_cvtd_s(uint32_t fst0) |
2131 |
{ |
2132 |
uint64_t fdt2; |
2133 |
|
2134 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2135 |
fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status); |
2136 |
update_fcr31(); |
2137 |
return fdt2;
|
2138 |
} |
2139 |
|
2140 |
uint64_t helper_float_cvtd_w(uint32_t wt0) |
2141 |
{ |
2142 |
uint64_t fdt2; |
2143 |
|
2144 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2145 |
fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status); |
2146 |
update_fcr31(); |
2147 |
return fdt2;
|
2148 |
} |
2149 |
|
2150 |
uint64_t helper_float_cvtd_l(uint64_t dt0) |
2151 |
{ |
2152 |
uint64_t fdt2; |
2153 |
|
2154 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2155 |
fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status); |
2156 |
update_fcr31(); |
2157 |
return fdt2;
|
2158 |
} |
2159 |
|
2160 |
uint64_t helper_float_cvtl_d(uint64_t fdt0) |
2161 |
{ |
2162 |
uint64_t dt2; |
2163 |
|
2164 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2165 |
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
2166 |
update_fcr31(); |
2167 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2168 |
dt2 = FLOAT_SNAN64; |
2169 |
return dt2;
|
2170 |
} |
2171 |
|
2172 |
uint64_t helper_float_cvtl_s(uint32_t fst0) |
2173 |
{ |
2174 |
uint64_t dt2; |
2175 |
|
2176 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2177 |
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
2178 |
update_fcr31(); |
2179 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2180 |
dt2 = FLOAT_SNAN64; |
2181 |
return dt2;
|
2182 |
} |
2183 |
|
2184 |
uint64_t helper_float_cvtps_pw(uint64_t dt0) |
2185 |
{ |
2186 |
uint32_t fst2; |
2187 |
uint32_t fsth2; |
2188 |
|
2189 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2190 |
fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
|
2191 |
fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
|
2192 |
update_fcr31(); |
2193 |
return ((uint64_t)fsth2 << 32) | fst2; |
2194 |
} |
2195 |
|
2196 |
uint64_t helper_float_cvtpw_ps(uint64_t fdt0) |
2197 |
{ |
2198 |
uint32_t wt2; |
2199 |
uint32_t wth2; |
2200 |
|
2201 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2202 |
wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
|
2203 |
wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
|
2204 |
update_fcr31(); |
2205 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) {
|
2206 |
wt2 = FLOAT_SNAN32; |
2207 |
wth2 = FLOAT_SNAN32; |
2208 |
} |
2209 |
return ((uint64_t)wth2 << 32) | wt2; |
2210 |
} |
2211 |
|
2212 |
uint32_t helper_float_cvts_d(uint64_t fdt0) |
2213 |
{ |
2214 |
uint32_t fst2; |
2215 |
|
2216 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2217 |
fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status); |
2218 |
update_fcr31(); |
2219 |
return fst2;
|
2220 |
} |
2221 |
|
2222 |
uint32_t helper_float_cvts_w(uint32_t wt0) |
2223 |
{ |
2224 |
uint32_t fst2; |
2225 |
|
2226 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2227 |
fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status); |
2228 |
update_fcr31(); |
2229 |
return fst2;
|
2230 |
} |
2231 |
|
2232 |
uint32_t helper_float_cvts_l(uint64_t dt0) |
2233 |
{ |
2234 |
uint32_t fst2; |
2235 |
|
2236 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2237 |
fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status); |
2238 |
update_fcr31(); |
2239 |
return fst2;
|
2240 |
} |
2241 |
|
2242 |
uint32_t helper_float_cvts_pl(uint32_t wt0) |
2243 |
{ |
2244 |
uint32_t wt2; |
2245 |
|
2246 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2247 |
wt2 = wt0; |
2248 |
update_fcr31(); |
2249 |
return wt2;
|
2250 |
} |
2251 |
|
2252 |
uint32_t helper_float_cvts_pu(uint32_t wth0) |
2253 |
{ |
2254 |
uint32_t wt2; |
2255 |
|
2256 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2257 |
wt2 = wth0; |
2258 |
update_fcr31(); |
2259 |
return wt2;
|
2260 |
} |
2261 |
|
2262 |
uint32_t helper_float_cvtw_s(uint32_t fst0) |
2263 |
{ |
2264 |
uint32_t wt2; |
2265 |
|
2266 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2267 |
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
2268 |
update_fcr31(); |
2269 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2270 |
wt2 = FLOAT_SNAN32; |
2271 |
return wt2;
|
2272 |
} |
2273 |
|
2274 |
uint32_t helper_float_cvtw_d(uint64_t fdt0) |
2275 |
{ |
2276 |
uint32_t wt2; |
2277 |
|
2278 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2279 |
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
2280 |
update_fcr31(); |
2281 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2282 |
wt2 = FLOAT_SNAN32; |
2283 |
return wt2;
|
2284 |
} |
2285 |
|
2286 |
uint64_t helper_float_roundl_d(uint64_t fdt0) |
2287 |
{ |
2288 |
uint64_t dt2; |
2289 |
|
2290 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2291 |
set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2292 |
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
2293 |
RESTORE_ROUNDING_MODE; |
2294 |
update_fcr31(); |
2295 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2296 |
dt2 = FLOAT_SNAN64; |
2297 |
return dt2;
|
2298 |
} |
2299 |
|
2300 |
uint64_t helper_float_roundl_s(uint32_t fst0) |
2301 |
{ |
2302 |
uint64_t dt2; |
2303 |
|
2304 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2305 |
set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2306 |
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
2307 |
RESTORE_ROUNDING_MODE; |
2308 |
update_fcr31(); |
2309 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2310 |
dt2 = FLOAT_SNAN64; |
2311 |
return dt2;
|
2312 |
} |
2313 |
|
2314 |
uint32_t helper_float_roundw_d(uint64_t fdt0) |
2315 |
{ |
2316 |
uint32_t wt2; |
2317 |
|
2318 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2319 |
set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2320 |
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
2321 |
RESTORE_ROUNDING_MODE; |
2322 |
update_fcr31(); |
2323 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2324 |
wt2 = FLOAT_SNAN32; |
2325 |
return wt2;
|
2326 |
} |
2327 |
|
2328 |
uint32_t helper_float_roundw_s(uint32_t fst0) |
2329 |
{ |
2330 |
uint32_t wt2; |
2331 |
|
2332 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2333 |
set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2334 |
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
2335 |
RESTORE_ROUNDING_MODE; |
2336 |
update_fcr31(); |
2337 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2338 |
wt2 = FLOAT_SNAN32; |
2339 |
return wt2;
|
2340 |
} |
2341 |
|
2342 |
uint64_t helper_float_truncl_d(uint64_t fdt0) |
2343 |
{ |
2344 |
uint64_t dt2; |
2345 |
|
2346 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2347 |
dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status); |
2348 |
update_fcr31(); |
2349 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2350 |
dt2 = FLOAT_SNAN64; |
2351 |
return dt2;
|
2352 |
} |
2353 |
|
2354 |
uint64_t helper_float_truncl_s(uint32_t fst0) |
2355 |
{ |
2356 |
uint64_t dt2; |
2357 |
|
2358 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2359 |
dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status); |
2360 |
update_fcr31(); |
2361 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2362 |
dt2 = FLOAT_SNAN64; |
2363 |
return dt2;
|
2364 |
} |
2365 |
|
2366 |
uint32_t helper_float_truncw_d(uint64_t fdt0) |
2367 |
{ |
2368 |
uint32_t wt2; |
2369 |
|
2370 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2371 |
wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status); |
2372 |
update_fcr31(); |
2373 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2374 |
wt2 = FLOAT_SNAN32; |
2375 |
return wt2;
|
2376 |
} |
2377 |
|
2378 |
uint32_t helper_float_truncw_s(uint32_t fst0) |
2379 |
{ |
2380 |
uint32_t wt2; |
2381 |
|
2382 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2383 |
wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status); |
2384 |
update_fcr31(); |
2385 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2386 |
wt2 = FLOAT_SNAN32; |
2387 |
return wt2;
|
2388 |
} |
2389 |
|
2390 |
uint64_t helper_float_ceill_d(uint64_t fdt0) |
2391 |
{ |
2392 |
uint64_t dt2; |
2393 |
|
2394 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2395 |
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2396 |
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
2397 |
RESTORE_ROUNDING_MODE; |
2398 |
update_fcr31(); |
2399 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2400 |
dt2 = FLOAT_SNAN64; |
2401 |
return dt2;
|
2402 |
} |
2403 |
|
2404 |
uint64_t helper_float_ceill_s(uint32_t fst0) |
2405 |
{ |
2406 |
uint64_t dt2; |
2407 |
|
2408 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2409 |
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2410 |
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
2411 |
RESTORE_ROUNDING_MODE; |
2412 |
update_fcr31(); |
2413 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2414 |
dt2 = FLOAT_SNAN64; |
2415 |
return dt2;
|
2416 |
} |
2417 |
|
2418 |
uint32_t helper_float_ceilw_d(uint64_t fdt0) |
2419 |
{ |
2420 |
uint32_t wt2; |
2421 |
|
2422 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2423 |
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2424 |
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
2425 |
RESTORE_ROUNDING_MODE; |
2426 |
update_fcr31(); |
2427 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2428 |
wt2 = FLOAT_SNAN32; |
2429 |
return wt2;
|
2430 |
} |
2431 |
|
2432 |
uint32_t helper_float_ceilw_s(uint32_t fst0) |
2433 |
{ |
2434 |
uint32_t wt2; |
2435 |
|
2436 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2437 |
set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2438 |
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
2439 |
RESTORE_ROUNDING_MODE; |
2440 |
update_fcr31(); |
2441 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2442 |
wt2 = FLOAT_SNAN32; |
2443 |
return wt2;
|
2444 |
} |
2445 |
|
2446 |
uint64_t helper_float_floorl_d(uint64_t fdt0) |
2447 |
{ |
2448 |
uint64_t dt2; |
2449 |
|
2450 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2451 |
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2452 |
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
2453 |
RESTORE_ROUNDING_MODE; |
2454 |
update_fcr31(); |
2455 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2456 |
dt2 = FLOAT_SNAN64; |
2457 |
return dt2;
|
2458 |
} |
2459 |
|
2460 |
uint64_t helper_float_floorl_s(uint32_t fst0) |
2461 |
{ |
2462 |
uint64_t dt2; |
2463 |
|
2464 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2465 |
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2466 |
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
2467 |
RESTORE_ROUNDING_MODE; |
2468 |
update_fcr31(); |
2469 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2470 |
dt2 = FLOAT_SNAN64; |
2471 |
return dt2;
|
2472 |
} |
2473 |
|
2474 |
uint32_t helper_float_floorw_d(uint64_t fdt0) |
2475 |
{ |
2476 |
uint32_t wt2; |
2477 |
|
2478 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2479 |
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2480 |
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
2481 |
RESTORE_ROUNDING_MODE; |
2482 |
update_fcr31(); |
2483 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2484 |
wt2 = FLOAT_SNAN32; |
2485 |
return wt2;
|
2486 |
} |
2487 |
|
2488 |
uint32_t helper_float_floorw_s(uint32_t fst0) |
2489 |
{ |
2490 |
uint32_t wt2; |
2491 |
|
2492 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2493 |
set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2494 |
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
2495 |
RESTORE_ROUNDING_MODE; |
2496 |
update_fcr31(); |
2497 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
|
2498 |
wt2 = FLOAT_SNAN32; |
2499 |
return wt2;
|
2500 |
} |
2501 |
|
2502 |
/* unary operations, not modifying fp status */
|
2503 |
#define FLOAT_UNOP(name) \
|
2504 |
uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \ |
2505 |
{ \ |
2506 |
return float64_ ## name(fdt0); \ |
2507 |
} \ |
2508 |
uint32_t helper_float_ ## name ## _s(uint32_t fst0) \ |
2509 |
{ \ |
2510 |
return float32_ ## name(fst0); \ |
2511 |
} \ |
2512 |
uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \ |
2513 |
{ \ |
2514 |
uint32_t wt0; \ |
2515 |
uint32_t wth0; \ |
2516 |
\ |
2517 |
wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \ |
2518 |
wth0 = float32_ ## name(fdt0 >> 32); \ |
2519 |
return ((uint64_t)wth0 << 32) | wt0; \ |
2520 |
} |
2521 |
FLOAT_UNOP(abs) |
2522 |
FLOAT_UNOP(chs) |
2523 |
#undef FLOAT_UNOP
|
2524 |
|
2525 |
/* MIPS specific unary operations */
|
2526 |
uint64_t helper_float_recip_d(uint64_t fdt0) |
2527 |
{ |
2528 |
uint64_t fdt2; |
2529 |
|
2530 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2531 |
fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); |
2532 |
update_fcr31(); |
2533 |
return fdt2;
|
2534 |
} |
2535 |
|
2536 |
uint32_t helper_float_recip_s(uint32_t fst0) |
2537 |
{ |
2538 |
uint32_t fst2; |
2539 |
|
2540 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2541 |
fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); |
2542 |
update_fcr31(); |
2543 |
return fst2;
|
2544 |
} |
2545 |
|
2546 |
uint64_t helper_float_rsqrt_d(uint64_t fdt0) |
2547 |
{ |
2548 |
uint64_t fdt2; |
2549 |
|
2550 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2551 |
fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); |
2552 |
fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); |
2553 |
update_fcr31(); |
2554 |
return fdt2;
|
2555 |
} |
2556 |
|
2557 |
uint32_t helper_float_rsqrt_s(uint32_t fst0) |
2558 |
{ |
2559 |
uint32_t fst2; |
2560 |
|
2561 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2562 |
fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); |
2563 |
fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); |
2564 |
update_fcr31(); |
2565 |
return fst2;
|
2566 |
} |
2567 |
|
2568 |
uint64_t helper_float_recip1_d(uint64_t fdt0) |
2569 |
{ |
2570 |
uint64_t fdt2; |
2571 |
|
2572 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2573 |
fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); |
2574 |
update_fcr31(); |
2575 |
return fdt2;
|
2576 |
} |
2577 |
|
2578 |
uint32_t helper_float_recip1_s(uint32_t fst0) |
2579 |
{ |
2580 |
uint32_t fst2; |
2581 |
|
2582 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2583 |
fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); |
2584 |
update_fcr31(); |
2585 |
return fst2;
|
2586 |
} |
2587 |
|
2588 |
uint64_t helper_float_recip1_ps(uint64_t fdt0) |
2589 |
{ |
2590 |
uint32_t fst2; |
2591 |
uint32_t fsth2; |
2592 |
|
2593 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2594 |
fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
|
2595 |
fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status);
|
2596 |
update_fcr31(); |
2597 |
return ((uint64_t)fsth2 << 32) | fst2; |
2598 |
} |
2599 |
|
2600 |
uint64_t helper_float_rsqrt1_d(uint64_t fdt0) |
2601 |
{ |
2602 |
uint64_t fdt2; |
2603 |
|
2604 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2605 |
fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); |
2606 |
fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); |
2607 |
update_fcr31(); |
2608 |
return fdt2;
|
2609 |
} |
2610 |
|
2611 |
uint32_t helper_float_rsqrt1_s(uint32_t fst0) |
2612 |
{ |
2613 |
uint32_t fst2; |
2614 |
|
2615 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2616 |
fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); |
2617 |
fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); |
2618 |
update_fcr31(); |
2619 |
return fst2;
|
2620 |
} |
2621 |
|
2622 |
uint64_t helper_float_rsqrt1_ps(uint64_t fdt0) |
2623 |
{ |
2624 |
uint32_t fst2; |
2625 |
uint32_t fsth2; |
2626 |
|
2627 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2628 |
fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
|
2629 |
fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
|
2630 |
fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); |
2631 |
fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status); |
2632 |
update_fcr31(); |
2633 |
return ((uint64_t)fsth2 << 32) | fst2; |
2634 |
} |
2635 |
|
2636 |
#define FLOAT_OP(name, p) void helper_float_##name##_##p(void) |
2637 |
|
2638 |
/* binary operations */
|
2639 |
#define FLOAT_BINOP(name) \
|
2640 |
uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \ |
2641 |
{ \ |
2642 |
uint64_t dt2; \ |
2643 |
\ |
2644 |
set_float_exception_flags(0, &env->active_fpu.fp_status); \
|
2645 |
dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \ |
2646 |
update_fcr31(); \ |
2647 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
|
2648 |
dt2 = FLOAT_QNAN64; \ |
2649 |
return dt2; \
|
2650 |
} \ |
2651 |
\ |
2652 |
uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \ |
2653 |
{ \ |
2654 |
uint32_t wt2; \ |
2655 |
\ |
2656 |
set_float_exception_flags(0, &env->active_fpu.fp_status); \
|
2657 |
wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ |
2658 |
update_fcr31(); \ |
2659 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
|
2660 |
wt2 = FLOAT_QNAN32; \ |
2661 |
return wt2; \
|
2662 |
} \ |
2663 |
\ |
2664 |
uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \ |
2665 |
{ \ |
2666 |
uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
|
2667 |
uint32_t fsth0 = fdt0 >> 32; \
|
2668 |
uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
|
2669 |
uint32_t fsth1 = fdt1 >> 32; \
|
2670 |
uint32_t wt2; \ |
2671 |
uint32_t wth2; \ |
2672 |
\ |
2673 |
set_float_exception_flags(0, &env->active_fpu.fp_status); \
|
2674 |
wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ |
2675 |
wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \ |
2676 |
update_fcr31(); \ |
2677 |
if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \
|
2678 |
wt2 = FLOAT_QNAN32; \ |
2679 |
wth2 = FLOAT_QNAN32; \ |
2680 |
} \ |
2681 |
return ((uint64_t)wth2 << 32) | wt2; \ |
2682 |
} |
2683 |
|
2684 |
FLOAT_BINOP(add) |
2685 |
FLOAT_BINOP(sub) |
2686 |
FLOAT_BINOP(mul) |
2687 |
FLOAT_BINOP(div) |
2688 |
#undef FLOAT_BINOP
|
2689 |
|
2690 |
/* ternary operations */
|
2691 |
#define FLOAT_TERNOP(name1, name2) \
|
2692 |
uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \ |
2693 |
uint64_t fdt2) \ |
2694 |
{ \ |
2695 |
fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \ |
2696 |
return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \ |
2697 |
} \ |
2698 |
\ |
2699 |
uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \ |
2700 |
uint32_t fst2) \ |
2701 |
{ \ |
2702 |
fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ |
2703 |
return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ |
2704 |
} \ |
2705 |
\ |
2706 |
uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \ |
2707 |
uint64_t fdt2) \ |
2708 |
{ \ |
2709 |
uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
|
2710 |
uint32_t fsth0 = fdt0 >> 32; \
|
2711 |
uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
|
2712 |
uint32_t fsth1 = fdt1 >> 32; \
|
2713 |
uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
|
2714 |
uint32_t fsth2 = fdt2 >> 32; \
|
2715 |
\ |
2716 |
fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ |
2717 |
fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \ |
2718 |
fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ |
2719 |
fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \ |
2720 |
return ((uint64_t)fsth2 << 32) | fst2; \ |
2721 |
} |
2722 |
|
2723 |
FLOAT_TERNOP(mul, add) |
2724 |
FLOAT_TERNOP(mul, sub) |
2725 |
#undef FLOAT_TERNOP
|
2726 |
|
2727 |
/* negated ternary operations */
|
2728 |
#define FLOAT_NTERNOP(name1, name2) \
|
2729 |
uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \ |
2730 |
uint64_t fdt2) \ |
2731 |
{ \ |
2732 |
fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \ |
2733 |
fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \ |
2734 |
return float64_chs(fdt2); \
|
2735 |
} \ |
2736 |
\ |
2737 |
uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \ |
2738 |
uint32_t fst2) \ |
2739 |
{ \ |
2740 |
fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ |
2741 |
fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ |
2742 |
return float32_chs(fst2); \
|
2743 |
} \ |
2744 |
\ |
2745 |
uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\ |
2746 |
uint64_t fdt2) \ |
2747 |
{ \ |
2748 |
uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
|
2749 |
uint32_t fsth0 = fdt0 >> 32; \
|
2750 |
uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
|
2751 |
uint32_t fsth1 = fdt1 >> 32; \
|
2752 |
uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
|
2753 |
uint32_t fsth2 = fdt2 >> 32; \
|
2754 |
\ |
2755 |
fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ |
2756 |
fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \ |
2757 |
fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ |
2758 |
fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \ |
2759 |
fst2 = float32_chs(fst2); \ |
2760 |
fsth2 = float32_chs(fsth2); \ |
2761 |
return ((uint64_t)fsth2 << 32) | fst2; \ |
2762 |
} |
2763 |
|
2764 |
FLOAT_NTERNOP(mul, add) |
2765 |
FLOAT_NTERNOP(mul, sub) |
2766 |
#undef FLOAT_NTERNOP
|
2767 |
|
2768 |
/* MIPS specific binary operations */
|
2769 |
uint64_t helper_float_recip2_d(uint64_t fdt0, uint64_t fdt2) |
2770 |
{ |
2771 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2772 |
fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); |
2773 |
fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status)); |
2774 |
update_fcr31(); |
2775 |
return fdt2;
|
2776 |
} |
2777 |
|
2778 |
uint32_t helper_float_recip2_s(uint32_t fst0, uint32_t fst2) |
2779 |
{ |
2780 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2781 |
fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
2782 |
fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); |
2783 |
update_fcr31(); |
2784 |
return fst2;
|
2785 |
} |
2786 |
|
2787 |
uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2) |
2788 |
{ |
2789 |
uint32_t fst0 = fdt0 & 0XFFFFFFFF;
|
2790 |
uint32_t fsth0 = fdt0 >> 32;
|
2791 |
uint32_t fst2 = fdt2 & 0XFFFFFFFF;
|
2792 |
uint32_t fsth2 = fdt2 >> 32;
|
2793 |
|
2794 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2795 |
fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
2796 |
fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); |
2797 |
fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); |
2798 |
fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status)); |
2799 |
update_fcr31(); |
2800 |
return ((uint64_t)fsth2 << 32) | fst2; |
2801 |
} |
2802 |
|
2803 |
uint64_t helper_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2) |
2804 |
{ |
2805 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2806 |
fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); |
2807 |
fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status); |
2808 |
fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status)); |
2809 |
update_fcr31(); |
2810 |
return fdt2;
|
2811 |
} |
2812 |
|
2813 |
uint32_t helper_float_rsqrt2_s(uint32_t fst0, uint32_t fst2) |
2814 |
{ |
2815 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2816 |
fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
2817 |
fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); |
2818 |
fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); |
2819 |
update_fcr31(); |
2820 |
return fst2;
|
2821 |
} |
2822 |
|
2823 |
uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2) |
2824 |
{ |
2825 |
uint32_t fst0 = fdt0 & 0XFFFFFFFF;
|
2826 |
uint32_t fsth0 = fdt0 >> 32;
|
2827 |
uint32_t fst2 = fdt2 & 0XFFFFFFFF;
|
2828 |
uint32_t fsth2 = fdt2 >> 32;
|
2829 |
|
2830 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2831 |
fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
2832 |
fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); |
2833 |
fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); |
2834 |
fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status); |
2835 |
fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); |
2836 |
fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status)); |
2837 |
update_fcr31(); |
2838 |
return ((uint64_t)fsth2 << 32) | fst2; |
2839 |
} |
2840 |
|
2841 |
uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1) |
2842 |
{ |
2843 |
uint32_t fst0 = fdt0 & 0XFFFFFFFF;
|
2844 |
uint32_t fsth0 = fdt0 >> 32;
|
2845 |
uint32_t fst1 = fdt1 & 0XFFFFFFFF;
|
2846 |
uint32_t fsth1 = fdt1 >> 32;
|
2847 |
uint32_t fst2; |
2848 |
uint32_t fsth2; |
2849 |
|
2850 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2851 |
fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status); |
2852 |
fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status); |
2853 |
update_fcr31(); |
2854 |
return ((uint64_t)fsth2 << 32) | fst2; |
2855 |
} |
2856 |
|
2857 |
uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1) |
2858 |
{ |
2859 |
uint32_t fst0 = fdt0 & 0XFFFFFFFF;
|
2860 |
uint32_t fsth0 = fdt0 >> 32;
|
2861 |
uint32_t fst1 = fdt1 & 0XFFFFFFFF;
|
2862 |
uint32_t fsth1 = fdt1 >> 32;
|
2863 |
uint32_t fst2; |
2864 |
uint32_t fsth2; |
2865 |
|
2866 |
set_float_exception_flags(0, &env->active_fpu.fp_status);
|
2867 |
fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status); |
2868 |
fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status); |
2869 |
update_fcr31(); |
2870 |
return ((uint64_t)fsth2 << 32) | fst2; |
2871 |
} |
2872 |
|
2873 |
/* compare operations */
|
2874 |
#define FOP_COND_D(op, cond) \
|
2875 |
void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ |
2876 |
{ \ |
2877 |
int c; \
|
2878 |
set_float_exception_flags(0, &env->active_fpu.fp_status); \
|
2879 |
c = cond; \ |
2880 |
update_fcr31(); \ |
2881 |
if (c) \
|
2882 |
SET_FP_COND(cc, env->active_fpu); \ |
2883 |
else \
|
2884 |
CLEAR_FP_COND(cc, env->active_fpu); \ |
2885 |
} \ |
2886 |
void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ |
2887 |
{ \ |
2888 |
int c; \
|
2889 |
set_float_exception_flags(0, &env->active_fpu.fp_status); \
|
2890 |
fdt0 = float64_abs(fdt0); \ |
2891 |
fdt1 = float64_abs(fdt1); \ |
2892 |
c = cond; \ |
2893 |
update_fcr31(); \ |
2894 |
if (c) \
|
2895 |
SET_FP_COND(cc, env->active_fpu); \ |
2896 |
else \
|
2897 |
CLEAR_FP_COND(cc, env->active_fpu); \ |
2898 |
} |
2899 |
|
2900 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
2901 |
* but float64_unordered_quiet() is still called. */
|
2902 |
FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
|
2903 |
FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)) |
2904 |
FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
2905 |
FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
2906 |
FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
2907 |
FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
2908 |
FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
2909 |
FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
2910 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
2911 |
* but float64_unordered() is still called. */
|
2912 |
FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
|
2913 |
FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)) |
2914 |
FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) |
2915 |
FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) |
2916 |
FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) |
2917 |
FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) |
2918 |
FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) |
2919 |
FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) |
2920 |
|
2921 |
#define FOP_COND_S(op, cond) \
|
2922 |
void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \ |
2923 |
{ \ |
2924 |
int c; \
|
2925 |
set_float_exception_flags(0, &env->active_fpu.fp_status); \
|
2926 |
c = cond; \ |
2927 |
update_fcr31(); \ |
2928 |
if (c) \
|
2929 |
SET_FP_COND(cc, env->active_fpu); \ |
2930 |
else \
|
2931 |
CLEAR_FP_COND(cc, env->active_fpu); \ |
2932 |
} \ |
2933 |
void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \ |
2934 |
{ \ |
2935 |
int c; \
|
2936 |
set_float_exception_flags(0, &env->active_fpu.fp_status); \
|
2937 |
fst0 = float32_abs(fst0); \ |
2938 |
fst1 = float32_abs(fst1); \ |
2939 |
c = cond; \ |
2940 |
update_fcr31(); \ |
2941 |
if (c) \
|
2942 |
SET_FP_COND(cc, env->active_fpu); \ |
2943 |
else \
|
2944 |
CLEAR_FP_COND(cc, env->active_fpu); \ |
2945 |
} |
2946 |
|
2947 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
2948 |
* but float32_unordered_quiet() is still called. */
|
2949 |
FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
|
2950 |
FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)) |
2951 |
FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
2952 |
FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
2953 |
FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
2954 |
FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
2955 |
FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
2956 |
FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
2957 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
2958 |
* but float32_unordered() is still called. */
|
2959 |
FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
|
2960 |
FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status)) |
2961 |
FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status)) |
2962 |
FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status)) |
2963 |
FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status)) |
2964 |
FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status)) |
2965 |
FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status)) |
2966 |
FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status)) |
2967 |
|
2968 |
#define FOP_COND_PS(op, condl, condh) \
|
2969 |
void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ |
2970 |
{ \ |
2971 |
uint32_t fst0, fsth0, fst1, fsth1; \ |
2972 |
int ch, cl; \
|
2973 |
set_float_exception_flags(0, &env->active_fpu.fp_status); \
|
2974 |
fst0 = fdt0 & 0XFFFFFFFF; \
|
2975 |
fsth0 = fdt0 >> 32; \
|
2976 |
fst1 = fdt1 & 0XFFFFFFFF; \
|
2977 |
fsth1 = fdt1 >> 32; \
|
2978 |
cl = condl; \ |
2979 |
ch = condh; \ |
2980 |
update_fcr31(); \ |
2981 |
if (cl) \
|
2982 |
SET_FP_COND(cc, env->active_fpu); \ |
2983 |
else \
|
2984 |
CLEAR_FP_COND(cc, env->active_fpu); \ |
2985 |
if (ch) \
|
2986 |
SET_FP_COND(cc + 1, env->active_fpu); \
|
2987 |
else \
|
2988 |
CLEAR_FP_COND(cc + 1, env->active_fpu); \
|
2989 |
} \ |
2990 |
void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ |
2991 |
{ \ |
2992 |
uint32_t fst0, fsth0, fst1, fsth1; \ |
2993 |
int ch, cl; \
|
2994 |
fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
|
2995 |
fsth0 = float32_abs(fdt0 >> 32); \
|
2996 |
fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
|
2997 |
fsth1 = float32_abs(fdt1 >> 32); \
|
2998 |
cl = condl; \ |
2999 |
ch = condh; \ |
3000 |
update_fcr31(); \ |
3001 |
if (cl) \
|
3002 |
SET_FP_COND(cc, env->active_fpu); \ |
3003 |
else \
|
3004 |
CLEAR_FP_COND(cc, env->active_fpu); \ |
3005 |
if (ch) \
|
3006 |
SET_FP_COND(cc + 1, env->active_fpu); \
|
3007 |
else \
|
3008 |
CLEAR_FP_COND(cc + 1, env->active_fpu); \
|
3009 |
} |
3010 |
|
3011 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
3012 |
* but float32_unordered_quiet() is still called. */
|
3013 |
FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
|
3014 |
(float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
|
3015 |
FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), |
3016 |
float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)) |
3017 |
FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status), |
3018 |
float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
3019 |
FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status), |
3020 |
float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
3021 |
FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status), |
3022 |
float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
3023 |
FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status), |
3024 |
float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
3025 |
FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status), |
3026 |
float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
3027 |
FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status), |
3028 |
float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
3029 |
/* NOTE: the comma operator will make "cond" to eval to false,
|
3030 |
* but float32_unordered() is still called. */
|
3031 |
FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
|
3032 |
(float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
|
3033 |
FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status), |
3034 |
float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)) |
3035 |
FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status), |
3036 |
float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) |
3037 |
FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status), |
3038 |
float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) |
3039 |
FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status), |
3040 |
float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) |
3041 |
FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status), |
3042 |
float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) |
3043 |
FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status), |
3044 |
float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) |
3045 |
FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status), |
3046 |
float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) |