Revision 6a8aabd3
b/hw/omap.h | ||
---|---|---|
664 | 664 |
struct omap_uart_s; |
665 | 665 |
struct omap_uart_s *omap_uart_init(target_phys_addr_t base, |
666 | 666 |
qemu_irq irq, omap_clk fclk, omap_clk iclk, |
667 |
qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr); |
|
667 |
qemu_irq txdma, qemu_irq rxdma, |
|
668 |
const char *label, CharDriverState *chr); |
|
668 | 669 |
struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta, |
669 | 670 |
qemu_irq irq, omap_clk fclk, omap_clk iclk, |
670 |
qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr); |
|
671 |
qemu_irq txdma, qemu_irq rxdma, |
|
672 |
const char *label, CharDriverState *chr); |
|
671 | 673 |
void omap_uart_reset(struct omap_uart_s *s); |
672 | 674 |
void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr); |
673 | 675 |
|
b/hw/omap1.c | ||
---|---|---|
3809 | 3809 |
omap_findclk(s, "uart1_ck"), |
3810 | 3810 |
omap_findclk(s, "uart1_ck"), |
3811 | 3811 |
s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX], |
3812 |
"uart1", |
|
3812 | 3813 |
serial_hds[0]); |
3813 | 3814 |
s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2], |
3814 | 3815 |
omap_findclk(s, "uart2_ck"), |
3815 | 3816 |
omap_findclk(s, "uart2_ck"), |
3816 | 3817 |
s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX], |
3818 |
"uart2", |
|
3817 | 3819 |
serial_hds[0] ? serial_hds[1] : NULL); |
3818 | 3820 |
s->uart[2] = omap_uart_init(0xfffb9800, s->irq[0][OMAP_INT_UART3], |
3819 | 3821 |
omap_findclk(s, "uart3_ck"), |
3820 | 3822 |
omap_findclk(s, "uart3_ck"), |
3821 | 3823 |
s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX], |
3824 |
"uart3", |
|
3822 | 3825 |
serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL); |
3823 | 3826 |
|
3824 | 3827 |
omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1")); |
b/hw/omap2.c | ||
---|---|---|
2291 | 2291 |
omap_findclk(s, "uart1_fclk"), |
2292 | 2292 |
omap_findclk(s, "uart1_iclk"), |
2293 | 2293 |
s->drq[OMAP24XX_DMA_UART1_TX], |
2294 |
s->drq[OMAP24XX_DMA_UART1_RX], serial_hds[0]); |
|
2294 |
s->drq[OMAP24XX_DMA_UART1_RX], |
|
2295 |
"uart1", |
|
2296 |
serial_hds[0]); |
|
2295 | 2297 |
s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20), |
2296 | 2298 |
s->irq[0][OMAP_INT_24XX_UART2_IRQ], |
2297 | 2299 |
omap_findclk(s, "uart2_fclk"), |
2298 | 2300 |
omap_findclk(s, "uart2_iclk"), |
2299 | 2301 |
s->drq[OMAP24XX_DMA_UART2_TX], |
2300 | 2302 |
s->drq[OMAP24XX_DMA_UART2_RX], |
2303 |
"uart2", |
|
2301 | 2304 |
serial_hds[0] ? serial_hds[1] : NULL); |
2302 | 2305 |
s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21), |
2303 | 2306 |
s->irq[0][OMAP_INT_24XX_UART3_IRQ], |
... | ... | |
2305 | 2308 |
omap_findclk(s, "uart3_iclk"), |
2306 | 2309 |
s->drq[OMAP24XX_DMA_UART3_TX], |
2307 | 2310 |
s->drq[OMAP24XX_DMA_UART3_RX], |
2311 |
"uart3", |
|
2308 | 2312 |
serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL); |
2309 | 2313 |
|
2310 | 2314 |
s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7), |
b/hw/omap_uart.c | ||
---|---|---|
51 | 51 |
|
52 | 52 |
struct omap_uart_s *omap_uart_init(target_phys_addr_t base, |
53 | 53 |
qemu_irq irq, omap_clk fclk, omap_clk iclk, |
54 |
qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr) |
|
54 |
qemu_irq txdma, qemu_irq rxdma, |
|
55 |
const char *label, CharDriverState *chr) |
|
55 | 56 |
{ |
56 | 57 |
struct omap_uart_s *s = (struct omap_uart_s *) |
57 | 58 |
qemu_mallocz(sizeof(struct omap_uart_s)); |
... | ... | |
61 | 62 |
s->irq = irq; |
62 | 63 |
#ifdef TARGET_WORDS_BIGENDIAN |
63 | 64 |
s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16, |
64 |
chr ?: qemu_chr_open("null", "null", NULL), 1,
|
|
65 |
chr ?: qemu_chr_open(label, "null", NULL), 1,
|
|
65 | 66 |
1); |
66 | 67 |
#else |
67 | 68 |
s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16, |
68 |
chr ?: qemu_chr_open("null", "null", NULL), 1,
|
|
69 |
chr ?: qemu_chr_open(label, "null", NULL), 1,
|
|
69 | 70 |
0); |
70 | 71 |
#endif |
71 | 72 |
return s; |
... | ... | |
162 | 163 |
|
163 | 164 |
struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta, |
164 | 165 |
qemu_irq irq, omap_clk fclk, omap_clk iclk, |
165 |
qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr) |
|
166 |
qemu_irq txdma, qemu_irq rxdma, |
|
167 |
const char *label, CharDriverState *chr) |
|
166 | 168 |
{ |
167 | 169 |
target_phys_addr_t base = omap_l4_attach(ta, 0, 0); |
168 | 170 |
struct omap_uart_s *s = omap_uart_init(base, irq, |
169 |
fclk, iclk, txdma, rxdma, chr); |
|
171 |
fclk, iclk, txdma, rxdma, label, chr);
|
|
170 | 172 |
int iomemtype = cpu_register_io_memory(omap_uart_readfn, |
171 | 173 |
omap_uart_writefn, s); |
172 | 174 |
|
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