root / hw / mcf5208.c @ 6ac0e82d
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/*
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* Motorola ColdFire MCF5208 SoC emulation.
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*
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* Copyright (c) 2007 CodeSourcery.
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*
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* This code is licenced under the GPL
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*/
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#include "vl.h" |
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#define SYS_FREQ 66000000 |
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#define PCSR_EN 0x0001 |
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#define PCSR_RLD 0x0002 |
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#define PCSR_PIF 0x0004 |
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#define PCSR_PIE 0x0008 |
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#define PCSR_OVW 0x0010 |
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#define PCSR_DBG 0x0020 |
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#define PCSR_DOZE 0x0040 |
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#define PCSR_PRE_SHIFT 8 |
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#define PCSR_PRE_MASK 0x0f00 |
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|
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typedef struct { |
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qemu_irq irq; |
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ptimer_state *timer; |
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uint16_t pcsr; |
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uint16_t pmr; |
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uint16_t pcntr; |
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} m5208_timer_state; |
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|
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static void m5208_timer_update(m5208_timer_state *s) |
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{
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if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF))
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qemu_irq_raise(s->irq); |
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else
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qemu_irq_lower(s->irq); |
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} |
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static void m5208_timer_write(m5208_timer_state *s, int offset, |
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uint32_t value) |
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{
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int prescale;
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int limit;
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switch (offset) {
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case 0: |
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/* The PIF bit is set-to-clear. */
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if (value & PCSR_PIF) {
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s->pcsr &= ~PCSR_PIF; |
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value &= ~PCSR_PIF; |
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} |
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/* Avoid frobbing the timer if we're just twiddling IRQ bits. */
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if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) { |
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s->pcsr = value; |
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m5208_timer_update(s); |
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return;
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} |
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if (s->pcsr & PCSR_EN)
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ptimer_stop(s->timer); |
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s->pcsr = value; |
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prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT);
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ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale);
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if (s->pcsr & PCSR_RLD)
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limit = s->pmr; |
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else
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limit = 0xffff;
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ptimer_set_limit(s->timer, limit, 0);
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if (s->pcsr & PCSR_EN)
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ptimer_run(s->timer, 0);
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break;
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case 2: |
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s->pmr = value; |
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s->pcsr &= ~PCSR_PIF; |
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if ((s->pcsr & PCSR_RLD) == 0) { |
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if (s->pcsr & PCSR_OVW)
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ptimer_set_count(s->timer, value); |
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} else {
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ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW); |
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} |
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break;
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case 4: |
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break;
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default:
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/* Should never happen. */
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abort(); |
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} |
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m5208_timer_update(s); |
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} |
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static void m5208_timer_trigger(void *opaque) |
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{
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m5208_timer_state *s = (m5208_timer_state *)opaque; |
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s->pcsr |= PCSR_PIF; |
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m5208_timer_update(s); |
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} |
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typedef struct { |
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m5208_timer_state timer[2];
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} m5208_sys_state; |
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|
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static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr) |
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{
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m5208_sys_state *s = (m5208_sys_state *)opaque; |
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switch (addr) {
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/* PIT0 */
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case 0xfc080000: |
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return s->timer[0].pcsr; |
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case 0xfc080002: |
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return s->timer[0].pmr; |
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case 0xfc080004: |
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return ptimer_get_count(s->timer[0].timer); |
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/* PIT1 */
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case 0xfc084000: |
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return s->timer[1].pcsr; |
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case 0xfc084002: |
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return s->timer[1].pmr; |
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case 0xfc084004: |
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return ptimer_get_count(s->timer[1].timer); |
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/* SDRAM Controller. */
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case 0xfc0a8110: /* SDCS0 */ |
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{
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int n;
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for (n = 0; n < 32; n++) { |
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if (ram_size < (2u << n)) |
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break;
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} |
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return (n - 1) | 0x40000000; |
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} |
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case 0xfc0a8114: /* SDCS1 */ |
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return 0; |
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default:
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cpu_abort(cpu_single_env, "m5208_sys_read: Bad offset 0x%x\n",
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(int)addr);
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return 0; |
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} |
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} |
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static void m5208_sys_write(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{
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m5208_sys_state *s = (m5208_sys_state *)opaque; |
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switch (addr) {
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/* PIT0 */
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case 0xfc080000: |
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case 0xfc080002: |
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case 0xfc080004: |
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m5208_timer_write(&s->timer[0], addr & 0xf, value); |
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return;
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/* PIT1 */
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case 0xfc084000: |
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case 0xfc084002: |
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case 0xfc084004: |
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m5208_timer_write(&s->timer[1], addr & 0xf, value); |
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return;
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default:
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cpu_abort(cpu_single_env, "m5208_sys_write: Bad offset 0x%x\n",
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(int)addr);
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break;
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} |
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} |
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static CPUReadMemoryFunc *m5208_sys_readfn[] = {
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m5208_sys_read, |
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m5208_sys_read, |
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m5208_sys_read |
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}; |
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static CPUWriteMemoryFunc *m5208_sys_writefn[] = {
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m5208_sys_write, |
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m5208_sys_write, |
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m5208_sys_write |
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}; |
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static void mcf5208_sys_init(qemu_irq *pic) |
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{
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int iomemtype;
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m5208_sys_state *s; |
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QEMUBH *bh; |
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int i;
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s = (m5208_sys_state *)qemu_mallocz(sizeof(m5208_sys_state));
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iomemtype = cpu_register_io_memory(0, m5208_sys_readfn,
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m5208_sys_writefn, s); |
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/* SDRAMC. */
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cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype); |
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/* Timers. */
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for (i = 0; i < 2; i++) { |
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bh = qemu_bh_new(m5208_timer_trigger, &s->timer[i]); |
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s->timer[i].timer = ptimer_init(bh); |
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cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000, |
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iomemtype); |
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s->timer[i].irq = pic[4 + i];
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} |
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} |
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static void mcf5208evb_init(int ram_size, int vga_ram_size, |
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const char *boot_device, DisplayState *ds, |
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const char **fd_filename, int snapshot, |
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const char *kernel_filename, const char *kernel_cmdline, |
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const char *initrd_filename, const char *cpu_model) |
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{
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CPUState *env; |
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int kernel_size;
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uint64_t elf_entry; |
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target_ulong entry; |
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qemu_irq *pic; |
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env = cpu_init(); |
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if (!cpu_model)
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cpu_model = "m5208";
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if (cpu_m68k_set_model(env, cpu_model)) {
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cpu_abort(env, "Unable to find m68k CPU definition\n");
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} |
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/* Initialize CPU registers. */
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env->vbr = 0;
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/* TODO: Configure BARs. */
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/* DRAM at 0x20000000 */
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cpu_register_physical_memory(0x40000000, ram_size,
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qemu_ram_alloc(ram_size) | IO_MEM_RAM); |
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/* Internal SRAM. */
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cpu_register_physical_memory(0x80000000, 16384, |
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qemu_ram_alloc(16384) | IO_MEM_RAM);
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/* Internal peripherals. */
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pic = mcf_intc_init(0xfc048000, env);
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mcf_uart_mm_init(0xfc060000, pic[26], serial_hds[0]); |
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mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]); |
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mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]); |
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mcf5208_sys_init(pic); |
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if (nb_nics > 1) { |
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fprintf(stderr, "Too many NICs\n");
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exit(1);
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} |
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if (nd_table[0].vlan) { |
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if (nd_table[0].model == NULL |
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|| strcmp(nd_table[0].model, "mcf_fec") == 0) { |
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mcf_fec_init(&nd_table[0], 0xfc030000, pic + 36); |
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} else if (strcmp(nd_table[0].model, "?") == 0) { |
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fprintf(stderr, "qemu: Supported NICs: mcf_fec\n");
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exit (1);
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} else {
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fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
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exit (1);
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} |
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} |
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/* 0xfc000000 SCM. */
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/* 0xfc004000 XBS. */
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/* 0xfc008000 FlexBus CS. */
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/* 0xfc030000 FEC. */
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/* 0xfc040000 SCM + Power management. */
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/* 0xfc044000 eDMA. */
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/* 0xfc048000 INTC. */
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/* 0xfc058000 I2C. */
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/* 0xfc05c000 QSPI. */
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/* 0xfc060000 UART0. */
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/* 0xfc064000 UART0. */
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/* 0xfc068000 UART0. */
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/* 0xfc070000 DMA timers. */
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/* 0xfc080000 PIT0. */
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/* 0xfc084000 PIT1. */
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/* 0xfc088000 EPORT. */
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/* 0xfc08c000 Watchdog. */
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/* 0xfc090000 clock module. */
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/* 0xfc0a0000 CCM + reset. */
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/* 0xfc0a4000 GPIO. */
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/* 0xfc0a8000 SDRAM controller. */
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/* Load kernel. */
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if (!kernel_filename) {
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fprintf(stderr, "Kernel image must be specified\n");
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exit(1);
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} |
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kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL); |
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entry = elf_entry; |
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if (kernel_size < 0) { |
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kernel_size = load_uboot(kernel_filename, &entry, NULL);
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} |
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if (kernel_size < 0) { |
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kernel_size = load_image(kernel_filename, phys_ram_base); |
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entry = 0x20000000;
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} |
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if (kernel_size < 0) { |
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fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
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exit(1);
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} |
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env->pc = entry; |
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} |
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|
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QEMUMachine mcf5208evb_machine = {
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"mcf5208evb",
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"MCF5206EVB",
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mcf5208evb_init, |
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}; |