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/*
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* PXA270-based Clamshell PDA platforms.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Written by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This code is licensed under the GNU GPL v2.
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*/
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#include "vl.h" |
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#define spitz_printf(format, ...) \
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fprintf(stderr, "%s: " format, __FUNCTION__, ##__VA_ARGS__) |
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#undef REG_FMT
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#define REG_FMT "0x%02lx" |
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/* Spitz Flash */
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#define FLASH_BASE 0x0c000000 |
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#define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */ |
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#define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */ |
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#define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */ |
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#define FLASH_ECCCNTR 0x0c /* ECC byte counter */ |
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#define FLASH_ECCCLRR 0x10 /* Clear ECC */ |
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#define FLASH_FLASHIO 0x14 /* Flash I/O */ |
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#define FLASH_FLASHCTL 0x18 /* Flash Control */ |
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#define FLASHCTL_CE0 (1 << 0) |
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#define FLASHCTL_CLE (1 << 1) |
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#define FLASHCTL_ALE (1 << 2) |
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#define FLASHCTL_WP (1 << 3) |
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#define FLASHCTL_CE1 (1 << 4) |
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#define FLASHCTL_RYBY (1 << 5) |
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#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
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struct sl_nand_s {
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target_phys_addr_t target_base; |
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struct nand_flash_s *nand;
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uint8_t ctl; |
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struct ecc_state_s ecc;
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}; |
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static uint32_t sl_readb(void *opaque, target_phys_addr_t addr) |
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{ |
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struct sl_nand_s *s = (struct sl_nand_s *) opaque; |
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int ryby;
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addr -= s->target_base; |
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switch (addr) {
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#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to)) |
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case FLASH_ECCLPLB:
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return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) | |
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BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7); |
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#define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to)) |
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case FLASH_ECCLPUB:
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return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) | |
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BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7); |
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case FLASH_ECCCP:
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return s->ecc.cp;
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case FLASH_ECCCNTR:
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return s->ecc.count & 0xff; |
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case FLASH_FLASHCTL:
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nand_getpins(s->nand, &ryby); |
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if (ryby)
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return s->ctl | FLASHCTL_RYBY;
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else
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return s->ctl;
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case FLASH_FLASHIO:
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return ecc_digest(&s->ecc, nand_getio(s->nand));
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default:
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spitz_printf("Bad register offset " REG_FMT "\n", addr); |
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} |
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return 0; |
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} |
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static uint32_t sl_readl(void *opaque, target_phys_addr_t addr) |
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{ |
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struct sl_nand_s *s = (struct sl_nand_s *) opaque; |
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addr -= s->target_base; |
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if (addr == FLASH_FLASHIO)
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return ecc_digest(&s->ecc, nand_getio(s->nand)) |
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(ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
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return sl_readb(opaque, addr);
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} |
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static void sl_writeb(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{ |
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struct sl_nand_s *s = (struct sl_nand_s *) opaque; |
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addr -= s->target_base; |
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switch (addr) {
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case FLASH_ECCCLRR:
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/* Value is ignored. */
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ecc_reset(&s->ecc); |
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break;
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case FLASH_FLASHCTL:
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s->ctl = value & 0xff & ~FLASHCTL_RYBY;
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nand_setpins(s->nand, |
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s->ctl & FLASHCTL_CLE, |
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s->ctl & FLASHCTL_ALE, |
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s->ctl & FLASHCTL_NCE, |
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s->ctl & FLASHCTL_WP, |
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0);
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break;
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case FLASH_FLASHIO:
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nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
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break;
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default:
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spitz_printf("Bad register offset " REG_FMT "\n", addr); |
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} |
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} |
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static void sl_save(QEMUFile *f, void *opaque) |
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{ |
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struct sl_nand_s *s = (struct sl_nand_s *) opaque; |
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qemu_put_8s(f, &s->ctl); |
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ecc_put(f, &s->ecc); |
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} |
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static int sl_load(QEMUFile *f, void *opaque, int version_id) |
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{ |
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struct sl_nand_s *s = (struct sl_nand_s *) opaque; |
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qemu_get_8s(f, &s->ctl); |
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ecc_get(f, &s->ecc); |
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return 0; |
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} |
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enum {
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FLASH_128M, |
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FLASH_1024M, |
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}; |
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static void sl_flash_register(struct pxa2xx_state_s *cpu, int size) |
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{ |
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int iomemtype;
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struct sl_nand_s *s;
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CPUReadMemoryFunc *sl_readfn[] = { |
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sl_readb, |
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sl_readb, |
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sl_readl, |
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}; |
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CPUWriteMemoryFunc *sl_writefn[] = { |
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sl_writeb, |
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sl_writeb, |
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sl_writeb, |
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}; |
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s = (struct sl_nand_s *) qemu_mallocz(sizeof(struct sl_nand_s)); |
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s->target_base = FLASH_BASE; |
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s->ctl = 0;
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if (size == FLASH_128M)
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s->nand = nand_init(NAND_MFR_SAMSUNG, 0x73);
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else if (size == FLASH_1024M) |
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s->nand = nand_init(NAND_MFR_SAMSUNG, 0xf1);
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iomemtype = cpu_register_io_memory(0, sl_readfn,
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sl_writefn, s); |
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cpu_register_physical_memory(s->target_base, 0x40, iomemtype);
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register_savevm("sl_flash", 0, 0, sl_save, sl_load, s); |
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} |
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/* Spitz Keyboard */
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#define SPITZ_KEY_STROBE_NUM 11 |
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#define SPITZ_KEY_SENSE_NUM 7 |
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|
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static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = { |
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12, 17, 91, 34, 36, 38, 39 |
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}; |
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static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = { |
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88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114 |
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}; |
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/* Eighth additional row maps the special keys */
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static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = { |
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{ 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 }, |
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{ -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 }, |
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{ 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 }, |
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{ 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 }, |
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{ 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 }, |
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{ 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x38 }, |
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{ 0x37, 0x3d, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 }, |
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{ 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 }, |
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}; |
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#define SPITZ_GPIO_AK_INT 13 /* Remote control */ |
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#define SPITZ_GPIO_SYNC 16 /* Sync button */ |
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#define SPITZ_GPIO_ON_KEY 95 /* Power button */ |
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#define SPITZ_GPIO_SWA 97 /* Lid */ |
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#define SPITZ_GPIO_SWB 96 /* Tablet mode */ |
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/* The special buttons are mapped to unused keys */
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static const int spitz_gpiomap[5] = { |
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SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY, |
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SPITZ_GPIO_SWA, SPITZ_GPIO_SWB, |
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}; |
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static int spitz_gpio_invert[5] = { 0, 0, 0, 0, 0, }; |
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struct spitz_keyboard_s {
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struct pxa2xx_state_s *cpu;
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int keymap[0x80]; |
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uint16_t keyrow[SPITZ_KEY_SENSE_NUM]; |
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uint16_t strobe_state; |
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uint16_t sense_state; |
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uint16_t pre_map[0x100];
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uint16_t modifiers; |
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uint16_t imodifiers; |
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uint8_t fifo[16];
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int fifopos, fifolen;
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QEMUTimer *kbdtimer; |
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}; |
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static void spitz_keyboard_sense_update(struct spitz_keyboard_s *s) |
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{ |
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int i;
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uint16_t strobe, sense = 0;
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for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) { |
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strobe = s->keyrow[i] & s->strobe_state; |
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if (strobe) {
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sense |= 1 << i;
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if (!(s->sense_state & (1 << i))) |
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pxa2xx_gpio_set(s->cpu->gpio, spitz_gpio_key_sense[i], 1);
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} else if (s->sense_state & (1 << i)) |
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pxa2xx_gpio_set(s->cpu->gpio, spitz_gpio_key_sense[i], 0);
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} |
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s->sense_state = sense; |
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} |
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static void spitz_keyboard_strobe(int line, int level, |
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struct spitz_keyboard_s *s)
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{ |
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int i;
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for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++) |
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if (spitz_gpio_key_strobe[i] == line) {
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if (level)
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s->strobe_state |= 1 << i;
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else
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s->strobe_state &= ~(1 << i);
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spitz_keyboard_sense_update(s); |
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break;
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} |
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} |
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static void spitz_keyboard_keydown(struct spitz_keyboard_s *s, int keycode) |
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{ |
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int spitz_keycode = s->keymap[keycode & 0x7f]; |
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if (spitz_keycode == -1) |
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return;
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/* Handle the additional keys */
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if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) { |
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pxa2xx_gpio_set(s->cpu->gpio, spitz_gpiomap[spitz_keycode & 0xf],
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(keycode < 0x80) ^
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spitz_gpio_invert[spitz_keycode & 0xf]);
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return;
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} |
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if (keycode & 0x80) |
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s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf)); |
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else
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s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf); |
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spitz_keyboard_sense_update(s); |
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} |
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|
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#define SHIFT (1 << 7) |
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#define CTRL (1 << 8) |
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#define FN (1 << 9) |
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#define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c |
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|
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static void spitz_keyboard_handler(struct spitz_keyboard_s *s, int keycode) |
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{ |
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uint16_t code; |
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int mapcode;
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switch (keycode) {
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case 0x2a: /* Left Shift */ |
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s->modifiers |= 1;
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break;
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case 0xaa: |
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s->modifiers &= ~1;
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break;
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case 0x36: /* Right Shift */ |
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s->modifiers |= 2;
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break;
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case 0xb6: |
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s->modifiers &= ~2;
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break;
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case 0x1d: /* Control */ |
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s->modifiers |= 4;
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break;
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case 0x9d: |
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s->modifiers &= ~4;
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break;
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case 0x38: /* Alt */ |
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s->modifiers |= 8;
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break;
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case 0xb8: |
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s->modifiers &= ~8;
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break;
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} |
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code = s->pre_map[mapcode = ((s->modifiers & 3) ?
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(keycode | SHIFT) : |
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(keycode & ~SHIFT))]; |
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|
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if (code != mapcode) {
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#if 0
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if ((code & SHIFT) && !(s->modifiers & 1))
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QUEUE_KEY(0x2a | (keycode & 0x80));
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if ((code & CTRL ) && !(s->modifiers & 4))
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QUEUE_KEY(0x1d | (keycode & 0x80));
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if ((code & FN ) && !(s->modifiers & 8))
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QUEUE_KEY(0x38 | (keycode & 0x80));
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if ((code & FN ) && (s->modifiers & 1))
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QUEUE_KEY(0x2a | (~keycode & 0x80));
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if ((code & FN ) && (s->modifiers & 2))
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QUEUE_KEY(0x36 | (~keycode & 0x80));
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#else
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if (keycode & 0x80) { |
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if ((s->imodifiers & 1 ) && !(s->modifiers & 1)) |
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QUEUE_KEY(0x2a | 0x80); |
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if ((s->imodifiers & 4 ) && !(s->modifiers & 4)) |
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QUEUE_KEY(0x1d | 0x80); |
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if ((s->imodifiers & 8 ) && !(s->modifiers & 8)) |
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QUEUE_KEY(0x38 | 0x80); |
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if ((s->imodifiers & 0x10) && (s->modifiers & 1)) |
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QUEUE_KEY(0x2a);
|
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if ((s->imodifiers & 0x20) && (s->modifiers & 2)) |
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QUEUE_KEY(0x36);
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s->imodifiers = 0;
|
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} else {
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if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) { |
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QUEUE_KEY(0x2a);
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s->imodifiers |= 1;
|
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} |
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if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) { |
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QUEUE_KEY(0x1d);
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s->imodifiers |= 4;
|
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} |
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if ((code & FN ) && !((s->modifiers | s->imodifiers) & 8)) { |
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QUEUE_KEY(0x38);
|
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s->imodifiers |= 8;
|
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} |
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if ((code & FN ) && (s->modifiers & 1) && |
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!(s->imodifiers & 0x10)) {
|
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QUEUE_KEY(0x2a | 0x80); |
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s->imodifiers |= 0x10;
|
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} |
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if ((code & FN ) && (s->modifiers & 2) && |
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!(s->imodifiers & 0x20)) {
|
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QUEUE_KEY(0x36 | 0x80); |
372 |
s->imodifiers |= 0x20;
|
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} |
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} |
375 |
#endif
|
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} |
377 |
|
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QUEUE_KEY((code & 0x7f) | (keycode & 0x80)); |
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} |
380 |
|
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static void spitz_keyboard_tick(void *opaque) |
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{ |
383 |
struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque; |
384 |
|
385 |
if (s->fifolen) {
|
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spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]); |
387 |
s->fifolen --; |
388 |
if (s->fifopos >= 16) |
389 |
s->fifopos = 0;
|
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} |
391 |
|
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qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + ticks_per_sec / 32);
|
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} |
394 |
|
395 |
static void spitz_keyboard_pre_map(struct spitz_keyboard_s *s) |
396 |
{ |
397 |
int i;
|
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for (i = 0; i < 0x100; i ++) |
399 |
s->pre_map[i] = i; |
400 |
s->pre_map[0x02 | SHIFT ] = 0x02 | SHIFT; /* exclam */ |
401 |
s->pre_map[0x28 | SHIFT ] = 0x03 | SHIFT; /* quotedbl */ |
402 |
s->pre_map[0x04 | SHIFT ] = 0x04 | SHIFT; /* numbersign */ |
403 |
s->pre_map[0x05 | SHIFT ] = 0x05 | SHIFT; /* dollar */ |
404 |
s->pre_map[0x06 | SHIFT ] = 0x06 | SHIFT; /* percent */ |
405 |
s->pre_map[0x08 | SHIFT ] = 0x07 | SHIFT; /* ampersand */ |
406 |
s->pre_map[0x28 ] = 0x08 | SHIFT; /* apostrophe */ |
407 |
s->pre_map[0x0a | SHIFT ] = 0x09 | SHIFT; /* parenleft */ |
408 |
s->pre_map[0x0b | SHIFT ] = 0x0a | SHIFT; /* parenright */ |
409 |
s->pre_map[0x29 | SHIFT ] = 0x0b | SHIFT; /* asciitilde */ |
410 |
s->pre_map[0x03 | SHIFT ] = 0x0c | SHIFT; /* at */ |
411 |
s->pre_map[0xd3 ] = 0x0e | FN; /* Delete */ |
412 |
s->pre_map[0x3a ] = 0x0f | FN; /* Caps_Lock */ |
413 |
s->pre_map[0x07 | SHIFT ] = 0x11 | FN; /* asciicircum */ |
414 |
s->pre_map[0x0d ] = 0x12 | FN; /* equal */ |
415 |
s->pre_map[0x0d | SHIFT ] = 0x13 | FN; /* plus */ |
416 |
s->pre_map[0x1a ] = 0x14 | FN; /* bracketleft */ |
417 |
s->pre_map[0x1b ] = 0x15 | FN; /* bracketright */ |
418 |
s->pre_map[0x1a | SHIFT ] = 0x16 | FN; /* braceleft */ |
419 |
s->pre_map[0x1b | SHIFT ] = 0x17 | FN; /* braceright */ |
420 |
s->pre_map[0x27 ] = 0x22 | FN; /* semicolon */ |
421 |
s->pre_map[0x27 | SHIFT ] = 0x23 | FN; /* colon */ |
422 |
s->pre_map[0x09 | SHIFT ] = 0x24 | FN; /* asterisk */ |
423 |
s->pre_map[0x2b ] = 0x25 | FN; /* backslash */ |
424 |
s->pre_map[0x2b | SHIFT ] = 0x26 | FN; /* bar */ |
425 |
s->pre_map[0x0c | SHIFT ] = 0x30 | FN; /* underscore */ |
426 |
s->pre_map[0x33 | SHIFT ] = 0x33 | FN; /* less */ |
427 |
s->pre_map[0x35 ] = 0x33 | SHIFT; /* slash */ |
428 |
s->pre_map[0x34 | SHIFT ] = 0x34 | FN; /* greater */ |
429 |
s->pre_map[0x35 | SHIFT ] = 0x34 | SHIFT; /* question */ |
430 |
s->pre_map[0x49 ] = 0x48 | FN; /* Page_Up */ |
431 |
s->pre_map[0x51 ] = 0x50 | FN; /* Page_Down */ |
432 |
|
433 |
s->modifiers = 0;
|
434 |
s->imodifiers = 0;
|
435 |
s->fifopos = 0;
|
436 |
s->fifolen = 0;
|
437 |
s->kbdtimer = qemu_new_timer(vm_clock, spitz_keyboard_tick, s); |
438 |
spitz_keyboard_tick(s); |
439 |
} |
440 |
|
441 |
#undef SHIFT
|
442 |
#undef CTRL
|
443 |
#undef FN
|
444 |
|
445 |
static void spitz_keyboard_save(QEMUFile *f, void *opaque) |
446 |
{ |
447 |
struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque; |
448 |
int i;
|
449 |
|
450 |
qemu_put_be16s(f, &s->sense_state); |
451 |
qemu_put_be16s(f, &s->strobe_state); |
452 |
for (i = 0; i < 5; i ++) |
453 |
qemu_put_byte(f, spitz_gpio_invert[i]); |
454 |
} |
455 |
|
456 |
static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id) |
457 |
{ |
458 |
struct spitz_keyboard_s *s = (struct spitz_keyboard_s *) opaque; |
459 |
int i;
|
460 |
|
461 |
qemu_get_be16s(f, &s->sense_state); |
462 |
qemu_get_be16s(f, &s->strobe_state); |
463 |
for (i = 0; i < 5; i ++) |
464 |
spitz_gpio_invert[i] = qemu_get_byte(f); |
465 |
|
466 |
/* Release all pressed keys */
|
467 |
memset(s->keyrow, 0, sizeof(s->keyrow)); |
468 |
spitz_keyboard_sense_update(s); |
469 |
s->modifiers = 0;
|
470 |
s->imodifiers = 0;
|
471 |
s->fifopos = 0;
|
472 |
s->fifolen = 0;
|
473 |
|
474 |
return 0; |
475 |
} |
476 |
|
477 |
static void spitz_keyboard_register(struct pxa2xx_state_s *cpu) |
478 |
{ |
479 |
int i, j;
|
480 |
struct spitz_keyboard_s *s;
|
481 |
|
482 |
s = (struct spitz_keyboard_s *)
|
483 |
qemu_mallocz(sizeof(struct spitz_keyboard_s)); |
484 |
memset(s, 0, sizeof(struct spitz_keyboard_s)); |
485 |
s->cpu = cpu; |
486 |
|
487 |
for (i = 0; i < 0x80; i ++) |
488 |
s->keymap[i] = -1;
|
489 |
for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++) |
490 |
for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++) |
491 |
if (spitz_keymap[i][j] != -1) |
492 |
s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
|
493 |
|
494 |
for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++) |
495 |
pxa2xx_gpio_handler_set(cpu->gpio, spitz_gpio_key_strobe[i], |
496 |
(gpio_handler_t) spitz_keyboard_strobe, s); |
497 |
|
498 |
spitz_keyboard_pre_map(s); |
499 |
qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s); |
500 |
|
501 |
register_savevm("spitz_keyboard", 0, 0, |
502 |
spitz_keyboard_save, spitz_keyboard_load, s); |
503 |
} |
504 |
|
505 |
/* SCOOP devices */
|
506 |
|
507 |
struct scoop_info_s {
|
508 |
target_phys_addr_t target_base; |
509 |
uint16_t status; |
510 |
uint16_t power; |
511 |
uint32_t gpio_level; |
512 |
uint32_t gpio_dir; |
513 |
uint32_t prev_level; |
514 |
struct {
|
515 |
gpio_handler_t fn; |
516 |
void *opaque;
|
517 |
} handler[16];
|
518 |
|
519 |
uint16_t mcr; |
520 |
uint16_t cdr; |
521 |
uint16_t ccr; |
522 |
uint16_t irr; |
523 |
uint16_t imr; |
524 |
uint16_t isr; |
525 |
uint16_t gprr; |
526 |
}; |
527 |
|
528 |
#define SCOOP_MCR 0x00 |
529 |
#define SCOOP_CDR 0x04 |
530 |
#define SCOOP_CSR 0x08 |
531 |
#define SCOOP_CPR 0x0c |
532 |
#define SCOOP_CCR 0x10 |
533 |
#define SCOOP_IRR_IRM 0x14 |
534 |
#define SCOOP_IMR 0x18 |
535 |
#define SCOOP_ISR 0x1c |
536 |
#define SCOOP_GPCR 0x20 |
537 |
#define SCOOP_GPWR 0x24 |
538 |
#define SCOOP_GPRR 0x28 |
539 |
|
540 |
static inline void scoop_gpio_handler_update(struct scoop_info_s *s) { |
541 |
uint32_t level, diff; |
542 |
int bit;
|
543 |
level = s->gpio_level & s->gpio_dir; |
544 |
|
545 |
for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { |
546 |
bit = ffs(diff) - 1;
|
547 |
if (s->handler[bit].fn)
|
548 |
s->handler[bit].fn(bit, (level >> bit) & 1,
|
549 |
s->handler[bit].opaque); |
550 |
} |
551 |
|
552 |
s->prev_level = level; |
553 |
} |
554 |
|
555 |
static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr) |
556 |
{ |
557 |
struct scoop_info_s *s = (struct scoop_info_s *) opaque; |
558 |
addr -= s->target_base; |
559 |
|
560 |
switch (addr) {
|
561 |
case SCOOP_MCR:
|
562 |
return s->mcr;
|
563 |
case SCOOP_CDR:
|
564 |
return s->cdr;
|
565 |
case SCOOP_CSR:
|
566 |
return s->status;
|
567 |
case SCOOP_CPR:
|
568 |
return s->power;
|
569 |
case SCOOP_CCR:
|
570 |
return s->ccr;
|
571 |
case SCOOP_IRR_IRM:
|
572 |
return s->irr;
|
573 |
case SCOOP_IMR:
|
574 |
return s->imr;
|
575 |
case SCOOP_ISR:
|
576 |
return s->isr;
|
577 |
case SCOOP_GPCR:
|
578 |
return s->gpio_dir;
|
579 |
case SCOOP_GPWR:
|
580 |
return s->gpio_level;
|
581 |
case SCOOP_GPRR:
|
582 |
return s->gprr;
|
583 |
default:
|
584 |
spitz_printf("Bad register offset " REG_FMT "\n", addr); |
585 |
} |
586 |
|
587 |
return 0; |
588 |
} |
589 |
|
590 |
static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) |
591 |
{ |
592 |
struct scoop_info_s *s = (struct scoop_info_s *) opaque; |
593 |
addr -= s->target_base; |
594 |
value &= 0xffff;
|
595 |
|
596 |
switch (addr) {
|
597 |
case SCOOP_MCR:
|
598 |
s->mcr = value; |
599 |
break;
|
600 |
case SCOOP_CDR:
|
601 |
s->cdr = value; |
602 |
break;
|
603 |
case SCOOP_CPR:
|
604 |
s->power = value; |
605 |
if (value & 0x80) |
606 |
s->power |= 0x8040;
|
607 |
break;
|
608 |
case SCOOP_CCR:
|
609 |
s->ccr = value; |
610 |
break;
|
611 |
case SCOOP_IRR_IRM:
|
612 |
s->irr = value; |
613 |
break;
|
614 |
case SCOOP_IMR:
|
615 |
s->imr = value; |
616 |
break;
|
617 |
case SCOOP_ISR:
|
618 |
s->isr = value; |
619 |
break;
|
620 |
case SCOOP_GPCR:
|
621 |
s->gpio_dir = value; |
622 |
scoop_gpio_handler_update(s); |
623 |
break;
|
624 |
case SCOOP_GPWR:
|
625 |
s->gpio_level = value & s->gpio_dir; |
626 |
scoop_gpio_handler_update(s); |
627 |
break;
|
628 |
case SCOOP_GPRR:
|
629 |
s->gprr = value; |
630 |
break;
|
631 |
default:
|
632 |
spitz_printf("Bad register offset " REG_FMT "\n", addr); |
633 |
} |
634 |
} |
635 |
|
636 |
CPUReadMemoryFunc *scoop_readfn[] = { |
637 |
scoop_readb, |
638 |
scoop_readb, |
639 |
scoop_readb, |
640 |
}; |
641 |
CPUWriteMemoryFunc *scoop_writefn[] = { |
642 |
scoop_writeb, |
643 |
scoop_writeb, |
644 |
scoop_writeb, |
645 |
}; |
646 |
|
647 |
static inline void scoop_gpio_set(struct scoop_info_s *s, int line, int level) |
648 |
{ |
649 |
if (line >= 16) { |
650 |
spitz_printf("No GPIO pin %i\n", line);
|
651 |
return;
|
652 |
} |
653 |
|
654 |
if (level)
|
655 |
s->gpio_level |= (1 << line);
|
656 |
else
|
657 |
s->gpio_level &= ~(1 << line);
|
658 |
} |
659 |
|
660 |
static inline void scoop_gpio_handler_set(struct scoop_info_s *s, int line, |
661 |
gpio_handler_t handler, void *opaque) {
|
662 |
if (line >= 16) { |
663 |
spitz_printf("No GPIO pin %i\n", line);
|
664 |
return;
|
665 |
} |
666 |
|
667 |
s->handler[line].fn = handler; |
668 |
s->handler[line].opaque = opaque; |
669 |
} |
670 |
|
671 |
static void scoop_save(QEMUFile *f, void *opaque) |
672 |
{ |
673 |
struct scoop_info_s *s = (struct scoop_info_s *) opaque; |
674 |
qemu_put_be16s(f, &s->status); |
675 |
qemu_put_be16s(f, &s->power); |
676 |
qemu_put_be32s(f, &s->gpio_level); |
677 |
qemu_put_be32s(f, &s->gpio_dir); |
678 |
qemu_put_be32s(f, &s->prev_level); |
679 |
qemu_put_be16s(f, &s->mcr); |
680 |
qemu_put_be16s(f, &s->cdr); |
681 |
qemu_put_be16s(f, &s->ccr); |
682 |
qemu_put_be16s(f, &s->irr); |
683 |
qemu_put_be16s(f, &s->imr); |
684 |
qemu_put_be16s(f, &s->isr); |
685 |
qemu_put_be16s(f, &s->gprr); |
686 |
} |
687 |
|
688 |
static int scoop_load(QEMUFile *f, void *opaque, int version_id) |
689 |
{ |
690 |
struct scoop_info_s *s = (struct scoop_info_s *) opaque; |
691 |
qemu_get_be16s(f, &s->status); |
692 |
qemu_get_be16s(f, &s->power); |
693 |
qemu_get_be32s(f, &s->gpio_level); |
694 |
qemu_get_be32s(f, &s->gpio_dir); |
695 |
qemu_get_be32s(f, &s->prev_level); |
696 |
qemu_get_be16s(f, &s->mcr); |
697 |
qemu_get_be16s(f, &s->cdr); |
698 |
qemu_get_be16s(f, &s->ccr); |
699 |
qemu_get_be16s(f, &s->irr); |
700 |
qemu_get_be16s(f, &s->imr); |
701 |
qemu_get_be16s(f, &s->isr); |
702 |
qemu_get_be16s(f, &s->gprr); |
703 |
|
704 |
return 0; |
705 |
} |
706 |
|
707 |
static struct scoop_info_s *spitz_scoop_init(struct pxa2xx_state_s *cpu, |
708 |
int count) {
|
709 |
int iomemtype;
|
710 |
struct scoop_info_s *s;
|
711 |
|
712 |
s = (struct scoop_info_s *)
|
713 |
qemu_mallocz(sizeof(struct scoop_info_s) * 2); |
714 |
memset(s, 0, sizeof(struct scoop_info_s) * count); |
715 |
s[0].target_base = 0x10800000; |
716 |
s[1].target_base = 0x08800040; |
717 |
|
718 |
/* Ready */
|
719 |
s[0].status = 0x02; |
720 |
s[1].status = 0x02; |
721 |
|
722 |
iomemtype = cpu_register_io_memory(0, scoop_readfn,
|
723 |
scoop_writefn, &s[0]);
|
724 |
cpu_register_physical_memory(s[0].target_base, 0x1000, iomemtype); |
725 |
register_savevm("scoop", 0, 0, scoop_save, scoop_load, &s[0]); |
726 |
|
727 |
if (count < 2) |
728 |
return s;
|
729 |
|
730 |
iomemtype = cpu_register_io_memory(0, scoop_readfn,
|
731 |
scoop_writefn, &s[1]);
|
732 |
cpu_register_physical_memory(s[1].target_base, 0x1000, iomemtype); |
733 |
register_savevm("scoop", 1, 0, scoop_save, scoop_load, &s[1]); |
734 |
|
735 |
return s;
|
736 |
} |
737 |
|
738 |
/* LCD backlight controller */
|
739 |
|
740 |
#define LCDTG_RESCTL 0x00 |
741 |
#define LCDTG_PHACTRL 0x01 |
742 |
#define LCDTG_DUTYCTRL 0x02 |
743 |
#define LCDTG_POWERREG0 0x03 |
744 |
#define LCDTG_POWERREG1 0x04 |
745 |
#define LCDTG_GPOR3 0x05 |
746 |
#define LCDTG_PICTRL 0x06 |
747 |
#define LCDTG_POLCTRL 0x07 |
748 |
|
749 |
static int bl_intensity, bl_power; |
750 |
|
751 |
static void spitz_bl_update(struct pxa2xx_state_s *s) |
752 |
{ |
753 |
if (bl_power && bl_intensity)
|
754 |
spitz_printf("LCD Backlight now at %i/63\n", bl_intensity);
|
755 |
else
|
756 |
spitz_printf("LCD Backlight now off\n");
|
757 |
} |
758 |
|
759 |
static void spitz_bl_bit5(int line, int level, void *opaque) |
760 |
{ |
761 |
int prev = bl_intensity;
|
762 |
|
763 |
if (level)
|
764 |
bl_intensity &= ~0x20;
|
765 |
else
|
766 |
bl_intensity |= 0x20;
|
767 |
|
768 |
if (bl_power && prev != bl_intensity)
|
769 |
spitz_bl_update((struct pxa2xx_state_s *) opaque);
|
770 |
} |
771 |
|
772 |
static void spitz_bl_power(int line, int level, void *opaque) |
773 |
{ |
774 |
bl_power = !!level; |
775 |
spitz_bl_update((struct pxa2xx_state_s *) opaque);
|
776 |
} |
777 |
|
778 |
static void spitz_lcdtg_dac_put(void *opaque, uint8_t cmd) |
779 |
{ |
780 |
int addr, value;
|
781 |
addr = cmd >> 5;
|
782 |
value = cmd & 0x1f;
|
783 |
|
784 |
switch (addr) {
|
785 |
case LCDTG_RESCTL:
|
786 |
if (value)
|
787 |
spitz_printf("LCD in QVGA mode\n");
|
788 |
else
|
789 |
spitz_printf("LCD in VGA mode\n");
|
790 |
break;
|
791 |
|
792 |
case LCDTG_DUTYCTRL:
|
793 |
bl_intensity &= ~0x1f;
|
794 |
bl_intensity |= value; |
795 |
if (bl_power)
|
796 |
spitz_bl_update((struct pxa2xx_state_s *) opaque);
|
797 |
break;
|
798 |
|
799 |
case LCDTG_POWERREG0:
|
800 |
/* Set common voltage to M62332FP */
|
801 |
break;
|
802 |
} |
803 |
} |
804 |
|
805 |
/* SSP devices */
|
806 |
|
807 |
#define CORGI_SSP_PORT 2 |
808 |
|
809 |
#define SPITZ_GPIO_LCDCON_CS 53 |
810 |
#define SPITZ_GPIO_ADS7846_CS 14 |
811 |
#define SPITZ_GPIO_MAX1111_CS 20 |
812 |
#define SPITZ_GPIO_TP_INT 11 |
813 |
|
814 |
static int lcd_en, ads_en, max_en; |
815 |
static struct max111x_s *max1111; |
816 |
static struct ads7846_state_s *ads7846; |
817 |
|
818 |
/* "Demux" the signal based on current chipselect */
|
819 |
static uint32_t corgi_ssp_read(void *opaque) |
820 |
{ |
821 |
if (lcd_en)
|
822 |
return 0; |
823 |
if (ads_en)
|
824 |
return ads7846_read(ads7846);
|
825 |
if (max_en)
|
826 |
return max111x_read(max1111);
|
827 |
return 0; |
828 |
} |
829 |
|
830 |
static void corgi_ssp_write(void *opaque, uint32_t value) |
831 |
{ |
832 |
if (lcd_en)
|
833 |
spitz_lcdtg_dac_put(opaque, value); |
834 |
if (ads_en)
|
835 |
ads7846_write(ads7846, value); |
836 |
if (max_en)
|
837 |
max111x_write(max1111, value); |
838 |
} |
839 |
|
840 |
static void corgi_ssp_gpio_cs(int line, int level, struct pxa2xx_state_s *s) |
841 |
{ |
842 |
if (line == SPITZ_GPIO_LCDCON_CS)
|
843 |
lcd_en = !level; |
844 |
else if (line == SPITZ_GPIO_ADS7846_CS) |
845 |
ads_en = !level; |
846 |
else if (line == SPITZ_GPIO_MAX1111_CS) |
847 |
max_en = !level; |
848 |
} |
849 |
|
850 |
#define MAX1111_BATT_VOLT 1 |
851 |
#define MAX1111_BATT_TEMP 2 |
852 |
#define MAX1111_ACIN_VOLT 3 |
853 |
|
854 |
#define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */ |
855 |
#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */ |
856 |
#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */ |
857 |
|
858 |
static void spitz_adc_temp_on(int line, int level, void *opaque) |
859 |
{ |
860 |
if (!max1111)
|
861 |
return;
|
862 |
|
863 |
if (level)
|
864 |
max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP); |
865 |
else
|
866 |
max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
|
867 |
} |
868 |
|
869 |
static void spitz_pendown_set(void *opaque, int line, int level) |
870 |
{ |
871 |
struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque; |
872 |
pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_TP_INT, level); |
873 |
} |
874 |
|
875 |
static void spitz_ssp_save(QEMUFile *f, void *opaque) |
876 |
{ |
877 |
qemu_put_be32(f, lcd_en); |
878 |
qemu_put_be32(f, ads_en); |
879 |
qemu_put_be32(f, max_en); |
880 |
qemu_put_be32(f, bl_intensity); |
881 |
qemu_put_be32(f, bl_power); |
882 |
} |
883 |
|
884 |
static int spitz_ssp_load(QEMUFile *f, void *opaque, int version_id) |
885 |
{ |
886 |
lcd_en = qemu_get_be32(f); |
887 |
ads_en = qemu_get_be32(f); |
888 |
max_en = qemu_get_be32(f); |
889 |
bl_intensity = qemu_get_be32(f); |
890 |
bl_power = qemu_get_be32(f); |
891 |
|
892 |
return 0; |
893 |
} |
894 |
|
895 |
static void spitz_ssp_attach(struct pxa2xx_state_s *cpu) |
896 |
{ |
897 |
lcd_en = ads_en = max_en = 0;
|
898 |
|
899 |
ads7846 = ads7846_init(qemu_allocate_irqs(spitz_pendown_set, cpu, 1)[0]); |
900 |
|
901 |
max1111 = max1111_init(0);
|
902 |
max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT); |
903 |
max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
|
904 |
max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN); |
905 |
|
906 |
pxa2xx_ssp_attach(cpu->ssp[CORGI_SSP_PORT - 1], corgi_ssp_read,
|
907 |
corgi_ssp_write, cpu); |
908 |
|
909 |
pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_LCDCON_CS, |
910 |
(gpio_handler_t) corgi_ssp_gpio_cs, cpu); |
911 |
pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_ADS7846_CS, |
912 |
(gpio_handler_t) corgi_ssp_gpio_cs, cpu); |
913 |
pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_MAX1111_CS, |
914 |
(gpio_handler_t) corgi_ssp_gpio_cs, cpu); |
915 |
|
916 |
bl_intensity = 0x20;
|
917 |
bl_power = 0;
|
918 |
|
919 |
register_savevm("spitz_ssp", 0, 0, spitz_ssp_save, spitz_ssp_load, cpu); |
920 |
} |
921 |
|
922 |
/* CF Microdrive */
|
923 |
|
924 |
static void spitz_microdrive_attach(struct pxa2xx_state_s *cpu) |
925 |
{ |
926 |
struct pcmcia_card_s *md;
|
927 |
BlockDriverState *bs = bs_table[0];
|
928 |
|
929 |
if (bs && bdrv_is_inserted(bs) && !bdrv_is_removable(bs)) {
|
930 |
md = dscm1xxxx_init(bs); |
931 |
pxa2xx_pcmcia_attach(cpu->pcmcia[1], md);
|
932 |
} |
933 |
} |
934 |
|
935 |
/* Wm8750 and Max7310 on I2C */
|
936 |
|
937 |
#define AKITA_MAX_ADDR 0x18 |
938 |
#define SPITZ_WM_ADDRL 0x1b |
939 |
#define SPITZ_WM_ADDRH 0x1a |
940 |
|
941 |
#define SPITZ_GPIO_WM 5 |
942 |
|
943 |
#ifdef HAS_AUDIO
|
944 |
static void spitz_wm8750_addr(int line, int level, void *opaque) |
945 |
{ |
946 |
i2c_slave *wm = (i2c_slave *) opaque; |
947 |
if (level)
|
948 |
i2c_set_slave_address(wm, SPITZ_WM_ADDRH); |
949 |
else
|
950 |
i2c_set_slave_address(wm, SPITZ_WM_ADDRL); |
951 |
} |
952 |
#endif
|
953 |
|
954 |
static void spitz_i2c_setup(struct pxa2xx_state_s *cpu) |
955 |
{ |
956 |
/* Attach the CPU on one end of our I2C bus. */
|
957 |
i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
|
958 |
|
959 |
#ifdef HAS_AUDIO
|
960 |
AudioState *audio; |
961 |
i2c_slave *wm; |
962 |
|
963 |
audio = AUD_init(); |
964 |
if (!audio)
|
965 |
return;
|
966 |
/* Attach a WM8750 to the bus */
|
967 |
wm = wm8750_init(bus, audio); |
968 |
|
969 |
spitz_wm8750_addr(0, 0, wm); |
970 |
pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_WM, spitz_wm8750_addr, wm); |
971 |
/* .. and to the sound interface. */
|
972 |
cpu->i2s->opaque = wm; |
973 |
cpu->i2s->codec_out = wm8750_dac_dat; |
974 |
cpu->i2s->codec_in = wm8750_adc_dat; |
975 |
wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s); |
976 |
#endif
|
977 |
} |
978 |
|
979 |
static void spitz_akita_i2c_setup(struct pxa2xx_state_s *cpu) |
980 |
{ |
981 |
/* Attach a Max7310 to Akita I2C bus. */
|
982 |
i2c_set_slave_address(max7310_init(pxa2xx_i2c_bus(cpu->i2c[0])),
|
983 |
AKITA_MAX_ADDR); |
984 |
} |
985 |
|
986 |
/* Other peripherals */
|
987 |
|
988 |
static void spitz_charge_switch(int line, int level, void *opaque) |
989 |
{ |
990 |
spitz_printf("Charging %s.\n", level ? "off" : "on"); |
991 |
} |
992 |
|
993 |
static void spitz_discharge_switch(int line, int level, void *opaque) |
994 |
{ |
995 |
spitz_printf("Discharging %s.\n", level ? "on" : "off"); |
996 |
} |
997 |
|
998 |
static void spitz_greenled_switch(int line, int level, void *opaque) |
999 |
{ |
1000 |
spitz_printf("Green LED %s.\n", level ? "on" : "off"); |
1001 |
} |
1002 |
|
1003 |
static void spitz_orangeled_switch(int line, int level, void *opaque) |
1004 |
{ |
1005 |
spitz_printf("Orange LED %s.\n", level ? "on" : "off"); |
1006 |
} |
1007 |
|
1008 |
#define SPITZ_SCP_LED_GREEN 1 |
1009 |
#define SPITZ_SCP_JK_B 2 |
1010 |
#define SPITZ_SCP_CHRG_ON 3 |
1011 |
#define SPITZ_SCP_MUTE_L 4 |
1012 |
#define SPITZ_SCP_MUTE_R 5 |
1013 |
#define SPITZ_SCP_CF_POWER 6 |
1014 |
#define SPITZ_SCP_LED_ORANGE 7 |
1015 |
#define SPITZ_SCP_JK_A 8 |
1016 |
#define SPITZ_SCP_ADC_TEMP_ON 9 |
1017 |
#define SPITZ_SCP2_IR_ON 1 |
1018 |
#define SPITZ_SCP2_AKIN_PULLUP 2 |
1019 |
#define SPITZ_SCP2_BACKLIGHT_CONT 7 |
1020 |
#define SPITZ_SCP2_BACKLIGHT_ON 8 |
1021 |
#define SPITZ_SCP2_MIC_BIAS 9 |
1022 |
|
1023 |
static void spitz_scoop_gpio_setup(struct pxa2xx_state_s *cpu, |
1024 |
struct scoop_info_s *scp, int num) |
1025 |
{ |
1026 |
scoop_gpio_handler_set(&scp[0], SPITZ_SCP_CHRG_ON,
|
1027 |
spitz_charge_switch, cpu); |
1028 |
scoop_gpio_handler_set(&scp[0], SPITZ_SCP_JK_B,
|
1029 |
spitz_discharge_switch, cpu); |
1030 |
scoop_gpio_handler_set(&scp[0], SPITZ_SCP_LED_GREEN,
|
1031 |
spitz_greenled_switch, cpu); |
1032 |
scoop_gpio_handler_set(&scp[0], SPITZ_SCP_LED_ORANGE,
|
1033 |
spitz_orangeled_switch, cpu); |
1034 |
|
1035 |
if (num >= 2) { |
1036 |
scoop_gpio_handler_set(&scp[1], SPITZ_SCP2_BACKLIGHT_CONT,
|
1037 |
spitz_bl_bit5, cpu); |
1038 |
scoop_gpio_handler_set(&scp[1], SPITZ_SCP2_BACKLIGHT_ON,
|
1039 |
spitz_bl_power, cpu); |
1040 |
} |
1041 |
|
1042 |
scoop_gpio_handler_set(&scp[0], SPITZ_SCP_ADC_TEMP_ON,
|
1043 |
spitz_adc_temp_on, cpu); |
1044 |
} |
1045 |
|
1046 |
#define SPITZ_GPIO_HSYNC 22 |
1047 |
#define SPITZ_GPIO_SD_DETECT 9 |
1048 |
#define SPITZ_GPIO_SD_WP 81 |
1049 |
#define SPITZ_GPIO_ON_RESET 89 |
1050 |
#define SPITZ_GPIO_BAT_COVER 90 |
1051 |
#define SPITZ_GPIO_CF1_IRQ 105 |
1052 |
#define SPITZ_GPIO_CF1_CD 94 |
1053 |
#define SPITZ_GPIO_CF2_IRQ 106 |
1054 |
#define SPITZ_GPIO_CF2_CD 93 |
1055 |
|
1056 |
int spitz_hsync;
|
1057 |
|
1058 |
static void spitz_lcd_hsync_handler(void *opaque) |
1059 |
{ |
1060 |
struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque; |
1061 |
pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_HSYNC, spitz_hsync); |
1062 |
spitz_hsync ^= 1;
|
1063 |
} |
1064 |
|
1065 |
static void spitz_mmc_coverswitch_change(void *opaque, int in) |
1066 |
{ |
1067 |
struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque; |
1068 |
pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_SD_DETECT, in); |
1069 |
} |
1070 |
|
1071 |
static void spitz_mmc_writeprotect_change(void *opaque, int wp) |
1072 |
{ |
1073 |
struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque; |
1074 |
pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_SD_WP, wp); |
1075 |
} |
1076 |
|
1077 |
static void spitz_pcmcia_cb(void *opaque, int line, int level) |
1078 |
{ |
1079 |
struct pxa2xx_state_s *cpu = (struct pxa2xx_state_s *) opaque; |
1080 |
static const int gpio_map[] = { |
1081 |
SPITZ_GPIO_CF1_IRQ, SPITZ_GPIO_CF1_CD, |
1082 |
SPITZ_GPIO_CF2_IRQ, SPITZ_GPIO_CF2_CD, |
1083 |
}; |
1084 |
pxa2xx_gpio_set(cpu->gpio, gpio_map[line], level); |
1085 |
} |
1086 |
|
1087 |
static void spitz_gpio_setup(struct pxa2xx_state_s *cpu, int slots) |
1088 |
{ |
1089 |
qemu_irq *pcmcia_cb; |
1090 |
/*
|
1091 |
* Bad hack: We toggle the LCD hsync GPIO on every GPIO status
|
1092 |
* read to satisfy broken guests that poll-wait for hsync.
|
1093 |
* Simulating a real hsync event would be less practical and
|
1094 |
* wouldn't guarantee that a guest ever exits the loop.
|
1095 |
*/
|
1096 |
spitz_hsync = 0;
|
1097 |
pxa2xx_gpio_read_notifier(cpu->gpio, spitz_lcd_hsync_handler, cpu); |
1098 |
pxa2xx_lcd_vsync_cb(cpu->lcd, spitz_lcd_hsync_handler, cpu); |
1099 |
|
1100 |
/* MMC/SD host */
|
1101 |
pxa2xx_mmci_handlers(cpu->mmc, cpu, spitz_mmc_writeprotect_change, |
1102 |
spitz_mmc_coverswitch_change); |
1103 |
|
1104 |
/* Battery lock always closed */
|
1105 |
pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_BAT_COVER, 1);
|
1106 |
|
1107 |
/* Handle reset */
|
1108 |
pxa2xx_gpio_handler_set(cpu->gpio, SPITZ_GPIO_ON_RESET, pxa2xx_reset, cpu); |
1109 |
|
1110 |
/* PCMCIA signals: card's IRQ and Card-Detect */
|
1111 |
pcmcia_cb = qemu_allocate_irqs(spitz_pcmcia_cb, cpu, slots * 2);
|
1112 |
if (slots >= 1) |
1113 |
pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0], pcmcia_cb[0], pcmcia_cb[1]); |
1114 |
if (slots >= 2) |
1115 |
pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1], pcmcia_cb[2], pcmcia_cb[3]); |
1116 |
|
1117 |
/* Initialise the screen rotation related signals */
|
1118 |
spitz_gpio_invert[3] = 0; /* Always open */ |
1119 |
if (graphic_rotate) { /* Tablet mode */ |
1120 |
spitz_gpio_invert[4] = 0; |
1121 |
} else { /* Portrait mode */ |
1122 |
spitz_gpio_invert[4] = 1; |
1123 |
} |
1124 |
pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_SWA, spitz_gpio_invert[3]);
|
1125 |
pxa2xx_gpio_set(cpu->gpio, SPITZ_GPIO_SWB, spitz_gpio_invert[4]);
|
1126 |
} |
1127 |
|
1128 |
/* Write the bootloader parameters memory area. */
|
1129 |
|
1130 |
#define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a) |
1131 |
|
1132 |
struct __attribute__ ((__packed__)) sl_param_info {
|
1133 |
uint32_t comadj_keyword; |
1134 |
int32_t comadj; |
1135 |
|
1136 |
uint32_t uuid_keyword; |
1137 |
char uuid[16]; |
1138 |
|
1139 |
uint32_t touch_keyword; |
1140 |
int32_t touch_xp; |
1141 |
int32_t touch_yp; |
1142 |
int32_t touch_xd; |
1143 |
int32_t touch_yd; |
1144 |
|
1145 |
uint32_t adadj_keyword; |
1146 |
int32_t adadj; |
1147 |
|
1148 |
uint32_t phad_keyword; |
1149 |
int32_t phadadj; |
1150 |
} spitz_bootparam = { |
1151 |
.comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'), |
1152 |
.comadj = 125,
|
1153 |
.uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'), |
1154 |
.uuid = { -1 },
|
1155 |
.touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'), |
1156 |
.touch_xp = -1,
|
1157 |
.adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'), |
1158 |
.adadj = -1,
|
1159 |
.phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'), |
1160 |
.phadadj = 0x01,
|
1161 |
}; |
1162 |
|
1163 |
static void sl_bootparam_write(uint32_t ptr) |
1164 |
{ |
1165 |
memcpy(phys_ram_base + ptr, &spitz_bootparam, |
1166 |
sizeof(struct sl_param_info)); |
1167 |
} |
1168 |
|
1169 |
#define SL_PXA_PARAM_BASE 0xa0000a00 |
1170 |
|
1171 |
/* Board init. */
|
1172 |
enum spitz_model_e { spitz, akita, borzoi, terrier };
|
1173 |
|
1174 |
static void spitz_common_init(int ram_size, int vga_ram_size, |
1175 |
DisplayState *ds, const char *kernel_filename, |
1176 |
const char *kernel_cmdline, const char *initrd_filename, |
1177 |
const char *cpu_model, enum spitz_model_e model, int arm_id) |
1178 |
{ |
1179 |
uint32_t spitz_ram = 0x04000000;
|
1180 |
uint32_t spitz_rom = 0x00800000;
|
1181 |
struct pxa2xx_state_s *cpu;
|
1182 |
struct scoop_info_s *scp;
|
1183 |
|
1184 |
if (!cpu_model)
|
1185 |
cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0"; |
1186 |
|
1187 |
/* Setup CPU & memory */
|
1188 |
if (ram_size < spitz_ram + spitz_rom + PXA2XX_INTERNAL_SIZE) {
|
1189 |
fprintf(stderr, "This platform requires %i bytes of memory\n",
|
1190 |
spitz_ram + spitz_rom + PXA2XX_INTERNAL_SIZE); |
1191 |
exit(1);
|
1192 |
} |
1193 |
cpu = pxa270_init(spitz_ram, ds, cpu_model); |
1194 |
|
1195 |
sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M); |
1196 |
|
1197 |
cpu_register_physical_memory(0, spitz_rom,
|
1198 |
qemu_ram_alloc(spitz_rom) | IO_MEM_ROM); |
1199 |
|
1200 |
/* Setup peripherals */
|
1201 |
spitz_keyboard_register(cpu); |
1202 |
|
1203 |
spitz_ssp_attach(cpu); |
1204 |
|
1205 |
scp = spitz_scoop_init(cpu, (model == akita) ? 1 : 2); |
1206 |
|
1207 |
spitz_scoop_gpio_setup(cpu, scp, (model == akita) ? 1 : 2); |
1208 |
|
1209 |
spitz_gpio_setup(cpu, (model == akita) ? 1 : 2); |
1210 |
|
1211 |
spitz_i2c_setup(cpu); |
1212 |
|
1213 |
if (model == akita)
|
1214 |
spitz_akita_i2c_setup(cpu); |
1215 |
|
1216 |
if (model == terrier)
|
1217 |
/* A 6.0 GB microdrive is permanently sitting in CF slot 1. */
|
1218 |
spitz_microdrive_attach(cpu); |
1219 |
else if (model != akita) |
1220 |
/* A 4.0 GB microdrive is permanently sitting in CF slot 1. */
|
1221 |
spitz_microdrive_attach(cpu); |
1222 |
|
1223 |
/* Setup initial (reset) machine state */
|
1224 |
cpu->env->regs[15] = PXA2XX_SDRAM_BASE;
|
1225 |
|
1226 |
arm_load_kernel(cpu->env, spitz_ram, kernel_filename, kernel_cmdline, |
1227 |
initrd_filename, arm_id, PXA2XX_SDRAM_BASE); |
1228 |
sl_bootparam_write(SL_PXA_PARAM_BASE - PXA2XX_SDRAM_BASE); |
1229 |
} |
1230 |
|
1231 |
static void spitz_init(int ram_size, int vga_ram_size, |
1232 |
const char *boot_device, DisplayState *ds, |
1233 |
const char **fd_filename, int snapshot, |
1234 |
const char *kernel_filename, const char *kernel_cmdline, |
1235 |
const char *initrd_filename, const char *cpu_model) |
1236 |
{ |
1237 |
spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename, |
1238 |
kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
|
1239 |
} |
1240 |
|
1241 |
static void borzoi_init(int ram_size, int vga_ram_size, |
1242 |
const char *boot_device, DisplayState *ds, |
1243 |
const char **fd_filename, int snapshot, |
1244 |
const char *kernel_filename, const char *kernel_cmdline, |
1245 |
const char *initrd_filename, const char *cpu_model) |
1246 |
{ |
1247 |
spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename, |
1248 |
kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
|
1249 |
} |
1250 |
|
1251 |
static void akita_init(int ram_size, int vga_ram_size, |
1252 |
const char *boot_device, DisplayState *ds, |
1253 |
const char **fd_filename, int snapshot, |
1254 |
const char *kernel_filename, const char *kernel_cmdline, |
1255 |
const char *initrd_filename, const char *cpu_model) |
1256 |
{ |
1257 |
spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename, |
1258 |
kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
|
1259 |
} |
1260 |
|
1261 |
static void terrier_init(int ram_size, int vga_ram_size, |
1262 |
const char *boot_device, DisplayState *ds, |
1263 |
const char **fd_filename, int snapshot, |
1264 |
const char *kernel_filename, const char *kernel_cmdline, |
1265 |
const char *initrd_filename, const char *cpu_model) |
1266 |
{ |
1267 |
spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename, |
1268 |
kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
|
1269 |
} |
1270 |
|
1271 |
QEMUMachine akitapda_machine = { |
1272 |
"akita",
|
1273 |
"Akita PDA (PXA270)",
|
1274 |
akita_init, |
1275 |
}; |
1276 |
|
1277 |
QEMUMachine spitzpda_machine = { |
1278 |
"spitz",
|
1279 |
"Spitz PDA (PXA270)",
|
1280 |
spitz_init, |
1281 |
}; |
1282 |
|
1283 |
QEMUMachine borzoipda_machine = { |
1284 |
"borzoi",
|
1285 |
"Borzoi PDA (PXA270)",
|
1286 |
borzoi_init, |
1287 |
}; |
1288 |
|
1289 |
QEMUMachine terrierpda_machine = { |
1290 |
"terrier",
|
1291 |
"Terrier PDA (PXA270)",
|
1292 |
terrier_init, |
1293 |
}; |