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1
/*
2
 * QEMU USB OHCI Emulation
3
 * Copyright (c) 2004 Gianni Tedesco
4
 * Copyright (c) 2006 CodeSourcery
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 * Copyright (c) 2006 Openedhand Ltd.
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 *
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 * This library is free software; you can redistribute it and/or
8
 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 *
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 * TODO:
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 *  o Isochronous transfers
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 *  o Allocate bandwidth in frames properly
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 *  o Disable timers when nothing needs to be done, or remove timer usage
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 *    all together.
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 *  o Handle unrecoverable errors properly
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 *  o BIOS work to boot from USB storage
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*/
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#include "hw.h"
30
#include "qemu-timer.h"
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#include "usb.h"
32
#include "pci.h"
33
#include "usb-ohci.h"
34
#include "sysbus.h"
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#include "qdev-addr.h"
36

    
37
//#define DEBUG_OHCI
38
/* Dump packet contents.  */
39
//#define DEBUG_PACKET
40
//#define DEBUG_ISOCH
41
/* This causes frames to occur 1000x slower */
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//#define OHCI_TIME_WARP 1
43

    
44
#ifdef DEBUG_OHCI
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#define DPRINTF printf
46
#else
47
#define DPRINTF(...)
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#endif
49

    
50
/* Number of Downstream Ports on the root hub.  */
51

    
52
#define OHCI_MAX_PORTS 15
53

    
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static int64_t usb_frame_time;
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static int64_t usb_bit_time;
56

    
57
typedef struct OHCIPort {
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    USBPort port;
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    uint32_t ctrl;
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} OHCIPort;
61

    
62
typedef struct {
63
    USBBus bus;
64
    qemu_irq irq;
65
    int mem;
66
    int num_ports;
67
    const char *name;
68

    
69
    QEMUTimer *eof_timer;
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    int64_t sof_time;
71

    
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    /* OHCI state */
73
    /* Control partition */
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    uint32_t ctl, status;
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    uint32_t intr_status;
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    uint32_t intr;
77

    
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    /* memory pointer partition */
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    uint32_t hcca;
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    uint32_t ctrl_head, ctrl_cur;
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    uint32_t bulk_head, bulk_cur;
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    uint32_t per_cur;
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    uint32_t done;
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    int done_count;
85

    
86
    /* Frame counter partition */
87
    uint32_t fsmps:15;
88
    uint32_t fit:1;
89
    uint32_t fi:14;
90
    uint32_t frt:1;
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    uint16_t frame_number;
92
    uint16_t padding;
93
    uint32_t pstart;
94
    uint32_t lst;
95

    
96
    /* Root Hub partition */
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    uint32_t rhdesc_a, rhdesc_b;
98
    uint32_t rhstatus;
99
    OHCIPort rhport[OHCI_MAX_PORTS];
100

    
101
    /* PXA27x Non-OHCI events */
102
    uint32_t hstatus;
103
    uint32_t hmask;
104
    uint32_t hreset;
105
    uint32_t htest;
106

    
107
    /* SM501 local memory offset */
108
    target_phys_addr_t localmem_base;
109

    
110
    /* Active packets.  */
111
    uint32_t old_ctl;
112
    USBPacket usb_packet;
113
    uint8_t usb_buf[8192];
114
    uint32_t async_td;
115
    int async_complete;
116

    
117
} OHCIState;
118

    
119
/* Host Controller Communications Area */
120
struct ohci_hcca {
121
    uint32_t intr[32];
122
    uint16_t frame, pad;
123
    uint32_t done;
124
};
125

    
126
static void ohci_bus_stop(OHCIState *ohci);
127

    
128
/* Bitfields for the first word of an Endpoint Desciptor.  */
129
#define OHCI_ED_FA_SHIFT  0
130
#define OHCI_ED_FA_MASK   (0x7f<<OHCI_ED_FA_SHIFT)
131
#define OHCI_ED_EN_SHIFT  7
132
#define OHCI_ED_EN_MASK   (0xf<<OHCI_ED_EN_SHIFT)
133
#define OHCI_ED_D_SHIFT   11
134
#define OHCI_ED_D_MASK    (3<<OHCI_ED_D_SHIFT)
135
#define OHCI_ED_S         (1<<13)
136
#define OHCI_ED_K         (1<<14)
137
#define OHCI_ED_F         (1<<15)
138
#define OHCI_ED_MPS_SHIFT 16
139
#define OHCI_ED_MPS_MASK  (0x7ff<<OHCI_ED_MPS_SHIFT)
140

    
141
/* Flags in the head field of an Endpoint Desciptor.  */
142
#define OHCI_ED_H         1
143
#define OHCI_ED_C         2
144

    
145
/* Bitfields for the first word of a Transfer Desciptor.  */
146
#define OHCI_TD_R         (1<<18)
147
#define OHCI_TD_DP_SHIFT  19
148
#define OHCI_TD_DP_MASK   (3<<OHCI_TD_DP_SHIFT)
149
#define OHCI_TD_DI_SHIFT  21
150
#define OHCI_TD_DI_MASK   (7<<OHCI_TD_DI_SHIFT)
151
#define OHCI_TD_T0        (1<<24)
152
#define OHCI_TD_T1        (1<<24)
153
#define OHCI_TD_EC_SHIFT  26
154
#define OHCI_TD_EC_MASK   (3<<OHCI_TD_EC_SHIFT)
155
#define OHCI_TD_CC_SHIFT  28
156
#define OHCI_TD_CC_MASK   (0xf<<OHCI_TD_CC_SHIFT)
157

    
158
/* Bitfields for the first word of an Isochronous Transfer Desciptor.  */
159
/* CC & DI - same as in the General Transfer Desciptor */
160
#define OHCI_TD_SF_SHIFT  0
161
#define OHCI_TD_SF_MASK   (0xffff<<OHCI_TD_SF_SHIFT)
162
#define OHCI_TD_FC_SHIFT  24
163
#define OHCI_TD_FC_MASK   (7<<OHCI_TD_FC_SHIFT)
164

    
165
/* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
166
#define OHCI_TD_PSW_CC_SHIFT 12
167
#define OHCI_TD_PSW_CC_MASK  (0xf<<OHCI_TD_PSW_CC_SHIFT)
168
#define OHCI_TD_PSW_SIZE_SHIFT 0
169
#define OHCI_TD_PSW_SIZE_MASK  (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
170

    
171
#define OHCI_PAGE_MASK    0xfffff000
172
#define OHCI_OFFSET_MASK  0xfff
173

    
174
#define OHCI_DPTR_MASK    0xfffffff0
175

    
176
#define OHCI_BM(val, field) \
177
  (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
178

    
179
#define OHCI_SET_BM(val, field, newval) do { \
180
    val &= ~OHCI_##field##_MASK; \
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    val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
182
    } while(0)
183

    
184
/* endpoint descriptor */
185
struct ohci_ed {
186
    uint32_t flags;
187
    uint32_t tail;
188
    uint32_t head;
189
    uint32_t next;
190
};
191

    
192
/* General transfer descriptor */
193
struct ohci_td {
194
    uint32_t flags;
195
    uint32_t cbp;
196
    uint32_t next;
197
    uint32_t be;
198
};
199

    
200
/* Isochronous transfer descriptor */
201
struct ohci_iso_td {
202
    uint32_t flags;
203
    uint32_t bp;
204
    uint32_t next;
205
    uint32_t be;
206
    uint16_t offset[8];
207
};
208

    
209
#define USB_HZ                      12000000
210

    
211
/* OHCI Local stuff */
212
#define OHCI_CTL_CBSR         ((1<<0)|(1<<1))
213
#define OHCI_CTL_PLE          (1<<2)
214
#define OHCI_CTL_IE           (1<<3)
215
#define OHCI_CTL_CLE          (1<<4)
216
#define OHCI_CTL_BLE          (1<<5)
217
#define OHCI_CTL_HCFS         ((1<<6)|(1<<7))
218
#define  OHCI_USB_RESET       0x00
219
#define  OHCI_USB_RESUME      0x40
220
#define  OHCI_USB_OPERATIONAL 0x80
221
#define  OHCI_USB_SUSPEND     0xc0
222
#define OHCI_CTL_IR           (1<<8)
223
#define OHCI_CTL_RWC          (1<<9)
224
#define OHCI_CTL_RWE          (1<<10)
225

    
226
#define OHCI_STATUS_HCR       (1<<0)
227
#define OHCI_STATUS_CLF       (1<<1)
228
#define OHCI_STATUS_BLF       (1<<2)
229
#define OHCI_STATUS_OCR       (1<<3)
230
#define OHCI_STATUS_SOC       ((1<<6)|(1<<7))
231

    
232
#define OHCI_INTR_SO          (1<<0) /* Scheduling overrun */
233
#define OHCI_INTR_WD          (1<<1) /* HcDoneHead writeback */
234
#define OHCI_INTR_SF          (1<<2) /* Start of frame */
235
#define OHCI_INTR_RD          (1<<3) /* Resume detect */
236
#define OHCI_INTR_UE          (1<<4) /* Unrecoverable error */
237
#define OHCI_INTR_FNO         (1<<5) /* Frame number overflow */
238
#define OHCI_INTR_RHSC        (1<<6) /* Root hub status change */
239
#define OHCI_INTR_OC          (1<<30) /* Ownership change */
240
#define OHCI_INTR_MIE         (1<<31) /* Master Interrupt Enable */
241

    
242
#define OHCI_HCCA_SIZE        0x100
243
#define OHCI_HCCA_MASK        0xffffff00
244

    
245
#define OHCI_EDPTR_MASK       0xfffffff0
246

    
247
#define OHCI_FMI_FI           0x00003fff
248
#define OHCI_FMI_FSMPS        0xffff0000
249
#define OHCI_FMI_FIT          0x80000000
250

    
251
#define OHCI_FR_RT            (1<<31)
252

    
253
#define OHCI_LS_THRESH        0x628
254

    
255
#define OHCI_RHA_RW_MASK      0x00000000 /* Mask of supported features.  */
256
#define OHCI_RHA_PSM          (1<<8)
257
#define OHCI_RHA_NPS          (1<<9)
258
#define OHCI_RHA_DT           (1<<10)
259
#define OHCI_RHA_OCPM         (1<<11)
260
#define OHCI_RHA_NOCP         (1<<12)
261
#define OHCI_RHA_POTPGT_MASK  0xff000000
262

    
263
#define OHCI_RHS_LPS          (1<<0)
264
#define OHCI_RHS_OCI          (1<<1)
265
#define OHCI_RHS_DRWE         (1<<15)
266
#define OHCI_RHS_LPSC         (1<<16)
267
#define OHCI_RHS_OCIC         (1<<17)
268
#define OHCI_RHS_CRWE         (1<<31)
269

    
270
#define OHCI_PORT_CCS         (1<<0)
271
#define OHCI_PORT_PES         (1<<1)
272
#define OHCI_PORT_PSS         (1<<2)
273
#define OHCI_PORT_POCI        (1<<3)
274
#define OHCI_PORT_PRS         (1<<4)
275
#define OHCI_PORT_PPS         (1<<8)
276
#define OHCI_PORT_LSDA        (1<<9)
277
#define OHCI_PORT_CSC         (1<<16)
278
#define OHCI_PORT_PESC        (1<<17)
279
#define OHCI_PORT_PSSC        (1<<18)
280
#define OHCI_PORT_OCIC        (1<<19)
281
#define OHCI_PORT_PRSC        (1<<20)
282
#define OHCI_PORT_WTC         (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
283
                               |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
284

    
285
#define OHCI_TD_DIR_SETUP     0x0
286
#define OHCI_TD_DIR_OUT       0x1
287
#define OHCI_TD_DIR_IN        0x2
288
#define OHCI_TD_DIR_RESERVED  0x3
289

    
290
#define OHCI_CC_NOERROR             0x0
291
#define OHCI_CC_CRC                 0x1
292
#define OHCI_CC_BITSTUFFING         0x2
293
#define OHCI_CC_DATATOGGLEMISMATCH  0x3
294
#define OHCI_CC_STALL               0x4
295
#define OHCI_CC_DEVICENOTRESPONDING 0x5
296
#define OHCI_CC_PIDCHECKFAILURE     0x6
297
#define OHCI_CC_UNDEXPETEDPID       0x7
298
#define OHCI_CC_DATAOVERRUN         0x8
299
#define OHCI_CC_DATAUNDERRUN        0x9
300
#define OHCI_CC_BUFFEROVERRUN       0xc
301
#define OHCI_CC_BUFFERUNDERRUN      0xd
302

    
303
#define OHCI_HRESET_FSBIR       (1 << 0)
304

    
305
/* Update IRQ levels */
306
static inline void ohci_intr_update(OHCIState *ohci)
307
{
308
    int level = 0;
309

    
310
    if ((ohci->intr & OHCI_INTR_MIE) &&
311
        (ohci->intr_status & ohci->intr))
312
        level = 1;
313

    
314
    qemu_set_irq(ohci->irq, level);
315
}
316

    
317
/* Set an interrupt */
318
static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr)
319
{
320
    ohci->intr_status |= intr;
321
    ohci_intr_update(ohci);
322
}
323

    
324
/* Attach or detach a device on a root hub port.  */
325
static void ohci_attach(USBPort *port1, USBDevice *dev)
326
{
327
    OHCIState *s = port1->opaque;
328
    OHCIPort *port = &s->rhport[port1->index];
329
    uint32_t old_state = port->ctrl;
330

    
331
    if (dev) {
332
        if (port->port.dev) {
333
            usb_attach(port1, NULL);
334
        }
335
        /* set connect status */
336
        port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC;
337

    
338
        /* update speed */
339
        if (dev->speed == USB_SPEED_LOW)
340
            port->ctrl |= OHCI_PORT_LSDA;
341
        else
342
            port->ctrl &= ~OHCI_PORT_LSDA;
343
        port->port.dev = dev;
344

    
345
        /* notify of remote-wakeup */
346
        if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND)
347
            ohci_set_interrupt(s, OHCI_INTR_RD);
348

    
349
        /* send the attach message */
350
        usb_send_msg(dev, USB_MSG_ATTACH);
351
        DPRINTF("usb-ohci: Attached port %d\n", port1->index);
352
    } else {
353
        /* set connect status */
354
        if (port->ctrl & OHCI_PORT_CCS) {
355
            port->ctrl &= ~OHCI_PORT_CCS;
356
            port->ctrl |= OHCI_PORT_CSC;
357
        }
358
        /* disable port */
359
        if (port->ctrl & OHCI_PORT_PES) {
360
            port->ctrl &= ~OHCI_PORT_PES;
361
            port->ctrl |= OHCI_PORT_PESC;
362
        }
363
        dev = port->port.dev;
364
        if (dev) {
365
            /* send the detach message */
366
            usb_send_msg(dev, USB_MSG_DETACH);
367
        }
368
        port->port.dev = NULL;
369
        DPRINTF("usb-ohci: Detached port %d\n", port1->index);
370
    }
371

    
372
    if (old_state != port->ctrl)
373
        ohci_set_interrupt(s, OHCI_INTR_RHSC);
374
}
375

    
376
/* Reset the controller */
377
static void ohci_reset(void *opaque)
378
{
379
    OHCIState *ohci = opaque;
380
    OHCIPort *port;
381
    int i;
382

    
383
    ohci_bus_stop(ohci);
384
    ohci->ctl = 0;
385
    ohci->old_ctl = 0;
386
    ohci->status = 0;
387
    ohci->intr_status = 0;
388
    ohci->intr = OHCI_INTR_MIE;
389

    
390
    ohci->hcca = 0;
391
    ohci->ctrl_head = ohci->ctrl_cur = 0;
392
    ohci->bulk_head = ohci->bulk_cur = 0;
393
    ohci->per_cur = 0;
394
    ohci->done = 0;
395
    ohci->done_count = 7;
396

    
397
    /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
398
     * I took the value linux sets ...
399
     */
400
    ohci->fsmps = 0x2778;
401
    ohci->fi = 0x2edf;
402
    ohci->fit = 0;
403
    ohci->frt = 0;
404
    ohci->frame_number = 0;
405
    ohci->pstart = 0;
406
    ohci->lst = OHCI_LS_THRESH;
407

    
408
    ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
409
    ohci->rhdesc_b = 0x0; /* Impl. specific */
410
    ohci->rhstatus = 0;
411

    
412
    for (i = 0; i < ohci->num_ports; i++)
413
      {
414
        port = &ohci->rhport[i];
415
        port->ctrl = 0;
416
        if (port->port.dev)
417
            ohci_attach(&port->port, port->port.dev);
418
      }
419
    if (ohci->async_td) {
420
        usb_cancel_packet(&ohci->usb_packet);
421
        ohci->async_td = 0;
422
    }
423
    DPRINTF("usb-ohci: Reset %s\n", ohci->name);
424
}
425

    
426
/* Get an array of dwords from main memory */
427
static inline int get_dwords(OHCIState *ohci,
428
                             uint32_t addr, uint32_t *buf, int num)
429
{
430
    int i;
431

    
432
    addr += ohci->localmem_base;
433

    
434
    for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
435
        cpu_physical_memory_rw(addr, (uint8_t *)buf, sizeof(*buf), 0);
436
        *buf = le32_to_cpu(*buf);
437
    }
438

    
439
    return 1;
440
}
441

    
442
/* Put an array of dwords in to main memory */
443
static inline int put_dwords(OHCIState *ohci,
444
                             uint32_t addr, uint32_t *buf, int num)
445
{
446
    int i;
447

    
448
    addr += ohci->localmem_base;
449

    
450
    for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
451
        uint32_t tmp = cpu_to_le32(*buf);
452
        cpu_physical_memory_rw(addr, (uint8_t *)&tmp, sizeof(tmp), 1);
453
    }
454

    
455
    return 1;
456
}
457

    
458
/* Get an array of words from main memory */
459
static inline int get_words(OHCIState *ohci,
460
                            uint32_t addr, uint16_t *buf, int num)
461
{
462
    int i;
463

    
464
    addr += ohci->localmem_base;
465

    
466
    for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
467
        cpu_physical_memory_rw(addr, (uint8_t *)buf, sizeof(*buf), 0);
468
        *buf = le16_to_cpu(*buf);
469
    }
470

    
471
    return 1;
472
}
473

    
474
/* Put an array of words in to main memory */
475
static inline int put_words(OHCIState *ohci,
476
                            uint32_t addr, uint16_t *buf, int num)
477
{
478
    int i;
479

    
480
    addr += ohci->localmem_base;
481

    
482
    for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
483
        uint16_t tmp = cpu_to_le16(*buf);
484
        cpu_physical_memory_rw(addr, (uint8_t *)&tmp, sizeof(tmp), 1);
485
    }
486

    
487
    return 1;
488
}
489

    
490
static inline int ohci_read_ed(OHCIState *ohci,
491
                               uint32_t addr, struct ohci_ed *ed)
492
{
493
    return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
494
}
495

    
496
static inline int ohci_read_td(OHCIState *ohci,
497
                               uint32_t addr, struct ohci_td *td)
498
{
499
    return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
500
}
501

    
502
static inline int ohci_read_iso_td(OHCIState *ohci,
503
                                   uint32_t addr, struct ohci_iso_td *td)
504
{
505
    return (get_dwords(ohci, addr, (uint32_t *)td, 4) &&
506
            get_words(ohci, addr + 16, td->offset, 8));
507
}
508

    
509
static inline int ohci_read_hcca(OHCIState *ohci,
510
                                 uint32_t addr, struct ohci_hcca *hcca)
511
{
512
    cpu_physical_memory_rw(addr + ohci->localmem_base,
513
                           (uint8_t *)hcca, sizeof(*hcca), 0);
514
    return 1;
515
}
516

    
517
static inline int ohci_put_ed(OHCIState *ohci,
518
                              uint32_t addr, struct ohci_ed *ed)
519
{
520
    return put_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
521
}
522

    
523
static inline int ohci_put_td(OHCIState *ohci,
524
                              uint32_t addr, struct ohci_td *td)
525
{
526
    return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
527
}
528

    
529
static inline int ohci_put_iso_td(OHCIState *ohci,
530
                                  uint32_t addr, struct ohci_iso_td *td)
531
{
532
    return (put_dwords(ohci, addr, (uint32_t *)td, 4) &&
533
            put_words(ohci, addr + 16, td->offset, 8));
534
}
535

    
536
static inline int ohci_put_hcca(OHCIState *ohci,
537
                                uint32_t addr, struct ohci_hcca *hcca)
538
{
539
    cpu_physical_memory_rw(addr + ohci->localmem_base,
540
                           (uint8_t *)hcca, sizeof(*hcca), 1);
541
    return 1;
542
}
543

    
544
/* Read/Write the contents of a TD from/to main memory.  */
545
static void ohci_copy_td(OHCIState *ohci, struct ohci_td *td,
546
                         uint8_t *buf, int len, int write)
547
{
548
    uint32_t ptr;
549
    uint32_t n;
550

    
551
    ptr = td->cbp;
552
    n = 0x1000 - (ptr & 0xfff);
553
    if (n > len)
554
        n = len;
555
    cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
556
    if (n == len)
557
        return;
558
    ptr = td->be & ~0xfffu;
559
    buf += n;
560
    cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
561
}
562

    
563
/* Read/Write the contents of an ISO TD from/to main memory.  */
564
static void ohci_copy_iso_td(OHCIState *ohci,
565
                             uint32_t start_addr, uint32_t end_addr,
566
                             uint8_t *buf, int len, int write)
567
{
568
    uint32_t ptr;
569
    uint32_t n;
570

    
571
    ptr = start_addr;
572
    n = 0x1000 - (ptr & 0xfff);
573
    if (n > len)
574
        n = len;
575
    cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
576
    if (n == len)
577
        return;
578
    ptr = end_addr & ~0xfffu;
579
    buf += n;
580
    cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
581
}
582

    
583
static void ohci_process_lists(OHCIState *ohci, int completion);
584

    
585
static void ohci_async_complete_packet(USBPacket *packet, void *opaque)
586
{
587
    OHCIState *ohci = opaque;
588
#ifdef DEBUG_PACKET
589
    DPRINTF("Async packet complete\n");
590
#endif
591
    ohci->async_complete = 1;
592
    ohci_process_lists(ohci, 1);
593
}
594

    
595
#define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
596

    
597
static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed,
598
                               int completion)
599
{
600
    int dir;
601
    size_t len = 0;
602
    const char *str = NULL;
603
    int pid;
604
    int ret;
605
    int i;
606
    USBDevice *dev;
607
    struct ohci_iso_td iso_td;
608
    uint32_t addr;
609
    uint16_t starting_frame;
610
    int16_t relative_frame_number;
611
    int frame_count;
612
    uint32_t start_offset, next_offset, end_offset = 0;
613
    uint32_t start_addr, end_addr;
614

    
615
    addr = ed->head & OHCI_DPTR_MASK;
616

    
617
    if (!ohci_read_iso_td(ohci, addr, &iso_td)) {
618
        printf("usb-ohci: ISO_TD read error at %x\n", addr);
619
        return 0;
620
    }
621

    
622
    starting_frame = OHCI_BM(iso_td.flags, TD_SF);
623
    frame_count = OHCI_BM(iso_td.flags, TD_FC);
624
    relative_frame_number = USUB(ohci->frame_number, starting_frame); 
625

    
626
#ifdef DEBUG_ISOCH
627
    printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n"
628
           "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
629
           "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
630
           "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
631
           "frame_number 0x%.8x starting_frame 0x%.8x\n"
632
           "frame_count  0x%.8x relative %d\n"
633
           "di 0x%.8x cc 0x%.8x\n",
634
           ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK,
635
           iso_td.flags, iso_td.bp, iso_td.next, iso_td.be,
636
           iso_td.offset[0], iso_td.offset[1], iso_td.offset[2], iso_td.offset[3],
637
           iso_td.offset[4], iso_td.offset[5], iso_td.offset[6], iso_td.offset[7],
638
           ohci->frame_number, starting_frame, 
639
           frame_count, relative_frame_number,         
640
           OHCI_BM(iso_td.flags, TD_DI), OHCI_BM(iso_td.flags, TD_CC));
641
#endif
642

    
643
    if (relative_frame_number < 0) {
644
        DPRINTF("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number);
645
        return 1;
646
    } else if (relative_frame_number > frame_count) {
647
        /* ISO TD expired - retire the TD to the Done Queue and continue with
648
           the next ISO TD of the same ED */
649
        DPRINTF("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number, 
650
               frame_count);
651
        OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
652
        ed->head &= ~OHCI_DPTR_MASK;
653
        ed->head |= (iso_td.next & OHCI_DPTR_MASK);
654
        iso_td.next = ohci->done;
655
        ohci->done = addr;
656
        i = OHCI_BM(iso_td.flags, TD_DI);
657
        if (i < ohci->done_count)
658
            ohci->done_count = i;
659
        ohci_put_iso_td(ohci, addr, &iso_td);
660
        return 0;
661
    }
662

    
663
    dir = OHCI_BM(ed->flags, ED_D);
664
    switch (dir) {
665
    case OHCI_TD_DIR_IN:
666
        str = "in";
667
        pid = USB_TOKEN_IN;
668
        break;
669
    case OHCI_TD_DIR_OUT:
670
        str = "out";
671
        pid = USB_TOKEN_OUT;
672
        break;
673
    case OHCI_TD_DIR_SETUP:
674
        str = "setup";
675
        pid = USB_TOKEN_SETUP;
676
        break;
677
    default:
678
        printf("usb-ohci: Bad direction %d\n", dir);
679
        return 1;
680
    }
681

    
682
    if (!iso_td.bp || !iso_td.be) {
683
        printf("usb-ohci: ISO_TD bp 0x%.8x be 0x%.8x\n", iso_td.bp, iso_td.be);
684
        return 1;
685
    }
686

    
687
    start_offset = iso_td.offset[relative_frame_number];
688
    next_offset = iso_td.offset[relative_frame_number + 1];
689

    
690
    if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) || 
691
        ((relative_frame_number < frame_count) && 
692
         !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
693
        printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n",
694
               start_offset, next_offset);
695
        return 1;
696
    }
697

    
698
    if ((relative_frame_number < frame_count) && (start_offset > next_offset)) {
699
        printf("usb-ohci: ISO_TD start_offset=0x%.8x > next_offset=0x%.8x\n",
700
                start_offset, next_offset);
701
        return 1;
702
    }
703

    
704
    if ((start_offset & 0x1000) == 0) {
705
        start_addr = (iso_td.bp & OHCI_PAGE_MASK) |
706
            (start_offset & OHCI_OFFSET_MASK);
707
    } else {
708
        start_addr = (iso_td.be & OHCI_PAGE_MASK) |
709
            (start_offset & OHCI_OFFSET_MASK);
710
    }
711

    
712
    if (relative_frame_number < frame_count) {
713
        end_offset = next_offset - 1;
714
        if ((end_offset & 0x1000) == 0) {
715
            end_addr = (iso_td.bp & OHCI_PAGE_MASK) |
716
                (end_offset & OHCI_OFFSET_MASK);
717
        } else {
718
            end_addr = (iso_td.be & OHCI_PAGE_MASK) |
719
                (end_offset & OHCI_OFFSET_MASK);
720
        }
721
    } else {
722
        /* Last packet in the ISO TD */
723
        end_addr = iso_td.be;
724
    }
725

    
726
    if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) {
727
        len = (end_addr & OHCI_OFFSET_MASK) + 0x1001
728
            - (start_addr & OHCI_OFFSET_MASK);
729
    } else {
730
        len = end_addr - start_addr + 1;
731
    }
732

    
733
    if (len && dir != OHCI_TD_DIR_IN) {
734
        ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, 0);
735
    }
736

    
737
    if (completion) {
738
        ret = ohci->usb_packet.len;
739
    } else {
740
        ret = USB_RET_NODEV;
741
        for (i = 0; i < ohci->num_ports; i++) {
742
            dev = ohci->rhport[i].port.dev;
743
            if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
744
                continue;
745
            ohci->usb_packet.pid = pid;
746
            ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
747
            ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
748
            ohci->usb_packet.data = ohci->usb_buf;
749
            ohci->usb_packet.len = len;
750
            ohci->usb_packet.complete_cb = ohci_async_complete_packet;
751
            ohci->usb_packet.complete_opaque = ohci;
752
            ret = dev->info->handle_packet(dev, &ohci->usb_packet);
753
            if (ret != USB_RET_NODEV)
754
                break;
755
        }
756
    
757
        if (ret == USB_RET_ASYNC) {
758
            return 1;
759
        }
760
    }
761

    
762
#ifdef DEBUG_ISOCH
763
    printf("so 0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d\n",
764
           start_offset, end_offset, start_addr, end_addr, str, len, ret);
765
#endif
766

    
767
    /* Writeback */
768
    if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) {
769
        /* IN transfer succeeded */
770
        ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, 1);
771
        OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
772
                    OHCI_CC_NOERROR);
773
        OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret);
774
    } else if (dir == OHCI_TD_DIR_OUT && ret == len) {
775
        /* OUT transfer succeeded */
776
        OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
777
                    OHCI_CC_NOERROR);
778
        OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0);
779
    } else {
780
        if (ret > (ssize_t) len) {
781
            printf("usb-ohci: DataOverrun %d > %zu\n", ret, len);
782
            OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
783
                        OHCI_CC_DATAOVERRUN);
784
            OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
785
                        len);
786
        } else if (ret >= 0) {
787
            printf("usb-ohci: DataUnderrun %d\n", ret);
788
            OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
789
                        OHCI_CC_DATAUNDERRUN);
790
        } else {
791
            switch (ret) {
792
            case USB_RET_NODEV:
793
                OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
794
                            OHCI_CC_DEVICENOTRESPONDING);
795
                OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
796
                            0);
797
                break;
798
            case USB_RET_NAK:
799
            case USB_RET_STALL:
800
                printf("usb-ohci: got NAK/STALL %d\n", ret);
801
                OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
802
                            OHCI_CC_STALL);
803
                OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
804
                            0);
805
                break;
806
            default:
807
                printf("usb-ohci: Bad device response %d\n", ret);
808
                OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
809
                            OHCI_CC_UNDEXPETEDPID);
810
                break;
811
            }
812
        }
813
    }
814

    
815
    if (relative_frame_number == frame_count) {
816
        /* Last data packet of ISO TD - retire the TD to the Done Queue */
817
        OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR);
818
        ed->head &= ~OHCI_DPTR_MASK;
819
        ed->head |= (iso_td.next & OHCI_DPTR_MASK);
820
        iso_td.next = ohci->done;
821
        ohci->done = addr;
822
        i = OHCI_BM(iso_td.flags, TD_DI);
823
        if (i < ohci->done_count)
824
            ohci->done_count = i;
825
    }
826
    ohci_put_iso_td(ohci, addr, &iso_td);
827
    return 1;
828
}
829

    
830
/* Service a transport descriptor.
831
   Returns nonzero to terminate processing of this endpoint.  */
832

    
833
static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
834
{
835
    int dir;
836
    size_t len = 0;
837
    const char *str = NULL;
838
    int pid;
839
    int ret;
840
    int i;
841
    USBDevice *dev;
842
    struct ohci_td td;
843
    uint32_t addr;
844
    int flag_r;
845
    int completion;
846

    
847
    addr = ed->head & OHCI_DPTR_MASK;
848
    /* See if this TD has already been submitted to the device.  */
849
    completion = (addr == ohci->async_td);
850
    if (completion && !ohci->async_complete) {
851
#ifdef DEBUG_PACKET
852
        DPRINTF("Skipping async TD\n");
853
#endif
854
        return 1;
855
    }
856
    if (!ohci_read_td(ohci, addr, &td)) {
857
        fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
858
        return 0;
859
    }
860

    
861
    dir = OHCI_BM(ed->flags, ED_D);
862
    switch (dir) {
863
    case OHCI_TD_DIR_OUT:
864
    case OHCI_TD_DIR_IN:
865
        /* Same value.  */
866
        break;
867
    default:
868
        dir = OHCI_BM(td.flags, TD_DP);
869
        break;
870
    }
871

    
872
    switch (dir) {
873
    case OHCI_TD_DIR_IN:
874
        str = "in";
875
        pid = USB_TOKEN_IN;
876
        break;
877
    case OHCI_TD_DIR_OUT:
878
        str = "out";
879
        pid = USB_TOKEN_OUT;
880
        break;
881
    case OHCI_TD_DIR_SETUP:
882
        str = "setup";
883
        pid = USB_TOKEN_SETUP;
884
        break;
885
    default:
886
        fprintf(stderr, "usb-ohci: Bad direction\n");
887
        return 1;
888
    }
889
    if (td.cbp && td.be) {
890
        if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) {
891
            len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff);
892
        } else {
893
            len = (td.be - td.cbp) + 1;
894
        }
895

    
896
        if (len && dir != OHCI_TD_DIR_IN && !completion) {
897
            ohci_copy_td(ohci, &td, ohci->usb_buf, len, 0);
898
        }
899
    }
900

    
901
    flag_r = (td.flags & OHCI_TD_R) != 0;
902
#ifdef DEBUG_PACKET
903
    DPRINTF(" TD @ 0x%.8x %" PRId64 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
904
            addr, (int64_t)len, str, flag_r, td.cbp, td.be);
905

    
906
    if (len > 0 && dir != OHCI_TD_DIR_IN) {
907
        DPRINTF("  data:");
908
        for (i = 0; i < len; i++)
909
            printf(" %.2x", ohci->usb_buf[i]);
910
        DPRINTF("\n");
911
    }
912
#endif
913
    if (completion) {
914
        ret = ohci->usb_packet.len;
915
        ohci->async_td = 0;
916
        ohci->async_complete = 0;
917
    } else {
918
        ret = USB_RET_NODEV;
919
        for (i = 0; i < ohci->num_ports; i++) {
920
            dev = ohci->rhport[i].port.dev;
921
            if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
922
                continue;
923

    
924
            if (ohci->async_td) {
925
                /* ??? The hardware should allow one active packet per
926
                   endpoint.  We only allow one active packet per controller.
927
                   This should be sufficient as long as devices respond in a
928
                   timely manner.
929
                 */
930
#ifdef DEBUG_PACKET
931
                DPRINTF("Too many pending packets\n");
932
#endif
933
                return 1;
934
            }
935
            ohci->usb_packet.pid = pid;
936
            ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
937
            ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
938
            ohci->usb_packet.data = ohci->usb_buf;
939
            ohci->usb_packet.len = len;
940
            ohci->usb_packet.complete_cb = ohci_async_complete_packet;
941
            ohci->usb_packet.complete_opaque = ohci;
942
            ret = dev->info->handle_packet(dev, &ohci->usb_packet);
943
            if (ret != USB_RET_NODEV)
944
                break;
945
        }
946
#ifdef DEBUG_PACKET
947
        DPRINTF("ret=%d\n", ret);
948
#endif
949
        if (ret == USB_RET_ASYNC) {
950
            ohci->async_td = addr;
951
            return 1;
952
        }
953
    }
954
    if (ret >= 0) {
955
        if (dir == OHCI_TD_DIR_IN) {
956
            ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1);
957
#ifdef DEBUG_PACKET
958
            DPRINTF("  data:");
959
            for (i = 0; i < ret; i++)
960
                printf(" %.2x", ohci->usb_buf[i]);
961
            DPRINTF("\n");
962
#endif
963
        } else {
964
            ret = len;
965
        }
966
    }
967

    
968
    /* Writeback */
969
    if (ret == len || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
970
        /* Transmission succeeded.  */
971
        if (ret == len) {
972
            td.cbp = 0;
973
        } else {
974
            td.cbp += ret;
975
            if ((td.cbp & 0xfff) + ret > 0xfff) {
976
                td.cbp &= 0xfff;
977
                td.cbp |= td.be & ~0xfff;
978
            }
979
        }
980
        td.flags |= OHCI_TD_T1;
981
        td.flags ^= OHCI_TD_T0;
982
        OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR);
983
        OHCI_SET_BM(td.flags, TD_EC, 0);
984

    
985
        ed->head &= ~OHCI_ED_C;
986
        if (td.flags & OHCI_TD_T0)
987
            ed->head |= OHCI_ED_C;
988
    } else {
989
        if (ret >= 0) {
990
            DPRINTF("usb-ohci: Underrun\n");
991
            OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
992
        } else {
993
            switch (ret) {
994
            case USB_RET_NODEV:
995
                OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
996
            case USB_RET_NAK:
997
                DPRINTF("usb-ohci: got NAK\n");
998
                return 1;
999
            case USB_RET_STALL:
1000
                DPRINTF("usb-ohci: got STALL\n");
1001
                OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
1002
                break;
1003
            case USB_RET_BABBLE:
1004
                DPRINTF("usb-ohci: got BABBLE\n");
1005
                OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
1006
                break;
1007
            default:
1008
                fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);
1009
                OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID);
1010
                OHCI_SET_BM(td.flags, TD_EC, 3);
1011
                break;
1012
            }
1013
        }
1014
        ed->head |= OHCI_ED_H;
1015
    }
1016

    
1017
    /* Retire this TD */
1018
    ed->head &= ~OHCI_DPTR_MASK;
1019
    ed->head |= td.next & OHCI_DPTR_MASK;
1020
    td.next = ohci->done;
1021
    ohci->done = addr;
1022
    i = OHCI_BM(td.flags, TD_DI);
1023
    if (i < ohci->done_count)
1024
        ohci->done_count = i;
1025
    ohci_put_td(ohci, addr, &td);
1026
    return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
1027
}
1028

    
1029
/* Service an endpoint list.  Returns nonzero if active TD were found.  */
1030
static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion)
1031
{
1032
    struct ohci_ed ed;
1033
    uint32_t next_ed;
1034
    uint32_t cur;
1035
    int active;
1036

    
1037
    active = 0;
1038

    
1039
    if (head == 0)
1040
        return 0;
1041

    
1042
    for (cur = head; cur; cur = next_ed) {
1043
        if (!ohci_read_ed(ohci, cur, &ed)) {
1044
            fprintf(stderr, "usb-ohci: ED read error at %x\n", cur);
1045
            return 0;
1046
        }
1047

    
1048
        next_ed = ed.next & OHCI_DPTR_MASK;
1049

    
1050
        if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
1051
            uint32_t addr;
1052
            /* Cancel pending packets for ED that have been paused.  */
1053
            addr = ed.head & OHCI_DPTR_MASK;
1054
            if (ohci->async_td && addr == ohci->async_td) {
1055
                usb_cancel_packet(&ohci->usb_packet);
1056
                ohci->async_td = 0;
1057
            }
1058
            continue;
1059
        }
1060

    
1061
        while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
1062
#ifdef DEBUG_PACKET
1063
            DPRINTF("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
1064
                    "h=%u c=%u\n  head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
1065
                    OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
1066
                    OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
1067
                    (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0,
1068
                    OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0,
1069
                    (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
1070
                    ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK);
1071
#endif
1072
            active = 1;
1073

    
1074
            if ((ed.flags & OHCI_ED_F) == 0) {
1075
                if (ohci_service_td(ohci, &ed))
1076
                    break;
1077
            } else {
1078
                /* Handle isochronous endpoints */
1079
                if (ohci_service_iso_td(ohci, &ed, completion))
1080
                    break;
1081
            }
1082
        }
1083

    
1084
        ohci_put_ed(ohci, cur, &ed);
1085
    }
1086

    
1087
    return active;
1088
}
1089

    
1090
/* Generate a SOF event, and set a timer for EOF */
1091
static void ohci_sof(OHCIState *ohci)
1092
{
1093
    ohci->sof_time = qemu_get_clock(vm_clock);
1094
    qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time);
1095
    ohci_set_interrupt(ohci, OHCI_INTR_SF);
1096
}
1097

    
1098
/* Process Control and Bulk lists.  */
1099
static void ohci_process_lists(OHCIState *ohci, int completion)
1100
{
1101
    if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
1102
        if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) {
1103
            DPRINTF("usb-ohci: head %x, cur %x\n",
1104
                    ohci->ctrl_head, ohci->ctrl_cur);
1105
        }
1106
        if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) {
1107
            ohci->ctrl_cur = 0;
1108
            ohci->status &= ~OHCI_STATUS_CLF;
1109
        }
1110
    }
1111

    
1112
    if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
1113
        if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) {
1114
            ohci->bulk_cur = 0;
1115
            ohci->status &= ~OHCI_STATUS_BLF;
1116
        }
1117
    }
1118
}
1119

    
1120
/* Do frame processing on frame boundary */
1121
static void ohci_frame_boundary(void *opaque)
1122
{
1123
    OHCIState *ohci = opaque;
1124
    struct ohci_hcca hcca;
1125

    
1126
    ohci_read_hcca(ohci, ohci->hcca, &hcca);
1127

    
1128
    /* Process all the lists at the end of the frame */
1129
    if (ohci->ctl & OHCI_CTL_PLE) {
1130
        int n;
1131

    
1132
        n = ohci->frame_number & 0x1f;
1133
        ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0);
1134
    }
1135

    
1136
    /* Cancel all pending packets if either of the lists has been disabled.  */
1137
    if (ohci->async_td &&
1138
        ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
1139
        usb_cancel_packet(&ohci->usb_packet);
1140
        ohci->async_td = 0;
1141
    }
1142
    ohci->old_ctl = ohci->ctl;
1143
    ohci_process_lists(ohci, 0);
1144

    
1145
    /* Frame boundary, so do EOF stuf here */
1146
    ohci->frt = ohci->fit;
1147

    
1148
    /* Increment frame number and take care of endianness. */
1149
    ohci->frame_number = (ohci->frame_number + 1) & 0xffff;
1150
    hcca.frame = cpu_to_le16(ohci->frame_number);
1151

    
1152
    if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) {
1153
        if (!ohci->done)
1154
            abort();
1155
        if (ohci->intr & ohci->intr_status)
1156
            ohci->done |= 1;
1157
        hcca.done = cpu_to_le32(ohci->done);
1158
        ohci->done = 0;
1159
        ohci->done_count = 7;
1160
        ohci_set_interrupt(ohci, OHCI_INTR_WD);
1161
    }
1162

    
1163
    if (ohci->done_count != 7 && ohci->done_count != 0)
1164
        ohci->done_count--;
1165

    
1166
    /* Do SOF stuff here */
1167
    ohci_sof(ohci);
1168

    
1169
    /* Writeback HCCA */
1170
    ohci_put_hcca(ohci, ohci->hcca, &hcca);
1171
}
1172

    
1173
/* Start sending SOF tokens across the USB bus, lists are processed in
1174
 * next frame
1175
 */
1176
static int ohci_bus_start(OHCIState *ohci)
1177
{
1178
    ohci->eof_timer = qemu_new_timer(vm_clock,
1179
                    ohci_frame_boundary,
1180
                    ohci);
1181

    
1182
    if (ohci->eof_timer == NULL) {
1183
        fprintf(stderr, "usb-ohci: %s: qemu_new_timer failed\n", ohci->name);
1184
        /* TODO: Signal unrecoverable error */
1185
        return 0;
1186
    }
1187

    
1188
    DPRINTF("usb-ohci: %s: USB Operational\n", ohci->name);
1189

    
1190
    ohci_sof(ohci);
1191

    
1192
    return 1;
1193
}
1194

    
1195
/* Stop sending SOF tokens on the bus */
1196
static void ohci_bus_stop(OHCIState *ohci)
1197
{
1198
    if (ohci->eof_timer)
1199
        qemu_del_timer(ohci->eof_timer);
1200
    ohci->eof_timer = NULL;
1201
}
1202

    
1203
/* Sets a flag in a port status register but only set it if the port is
1204
 * connected, if not set ConnectStatusChange flag. If flag is enabled
1205
 * return 1.
1206
 */
1207
static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
1208
{
1209
    int ret = 1;
1210

    
1211
    /* writing a 0 has no effect */
1212
    if (val == 0)
1213
        return 0;
1214

    
1215
    /* If CurrentConnectStatus is cleared we set
1216
     * ConnectStatusChange
1217
     */
1218
    if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
1219
        ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
1220
        if (ohci->rhstatus & OHCI_RHS_DRWE) {
1221
            /* TODO: CSC is a wakeup event */
1222
        }
1223
        return 0;
1224
    }
1225

    
1226
    if (ohci->rhport[i].ctrl & val)
1227
        ret = 0;
1228

    
1229
    /* set the bit */
1230
    ohci->rhport[i].ctrl |= val;
1231

    
1232
    return ret;
1233
}
1234

    
1235
/* Set the frame interval - frame interval toggle is manipulated by the hcd only */
1236
static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
1237
{
1238
    val &= OHCI_FMI_FI;
1239

    
1240
    if (val != ohci->fi) {
1241
        DPRINTF("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
1242
            ohci->name, ohci->fi, ohci->fi);
1243
    }
1244

    
1245
    ohci->fi = val;
1246
}
1247

    
1248
static void ohci_port_power(OHCIState *ohci, int i, int p)
1249
{
1250
    if (p) {
1251
        ohci->rhport[i].ctrl |= OHCI_PORT_PPS;
1252
    } else {
1253
        ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS|
1254
                    OHCI_PORT_CCS|
1255
                    OHCI_PORT_PSS|
1256
                    OHCI_PORT_PRS);
1257
    }
1258
}
1259

    
1260
/* Set HcControlRegister */
1261
static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
1262
{
1263
    uint32_t old_state;
1264
    uint32_t new_state;
1265

    
1266
    old_state = ohci->ctl & OHCI_CTL_HCFS;
1267
    ohci->ctl = val;
1268
    new_state = ohci->ctl & OHCI_CTL_HCFS;
1269

    
1270
    /* no state change */
1271
    if (old_state == new_state)
1272
        return;
1273

    
1274
    switch (new_state) {
1275
    case OHCI_USB_OPERATIONAL:
1276
        ohci_bus_start(ohci);
1277
        break;
1278
    case OHCI_USB_SUSPEND:
1279
        ohci_bus_stop(ohci);
1280
        DPRINTF("usb-ohci: %s: USB Suspended\n", ohci->name);
1281
        break;
1282
    case OHCI_USB_RESUME:
1283
        DPRINTF("usb-ohci: %s: USB Resume\n", ohci->name);
1284
        break;
1285
    case OHCI_USB_RESET:
1286
        ohci_reset(ohci);
1287
        DPRINTF("usb-ohci: %s: USB Reset\n", ohci->name);
1288
        break;
1289
    }
1290
}
1291

    
1292
static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
1293
{
1294
    uint16_t fr;
1295
    int64_t tks;
1296

    
1297
    if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
1298
        return (ohci->frt << 31);
1299

    
1300
    /* Being in USB operational state guarnatees sof_time was
1301
     * set already.
1302
     */
1303
    tks = qemu_get_clock(vm_clock) - ohci->sof_time;
1304

    
1305
    /* avoid muldiv if possible */
1306
    if (tks >= usb_frame_time)
1307
        return (ohci->frt << 31);
1308

    
1309
    tks = muldiv64(1, tks, usb_bit_time);
1310
    fr = (uint16_t)(ohci->fi - tks);
1311

    
1312
    return (ohci->frt << 31) | fr;
1313
}
1314

    
1315

    
1316
/* Set root hub status */
1317
static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
1318
{
1319
    uint32_t old_state;
1320

    
1321
    old_state = ohci->rhstatus;
1322

    
1323
    /* write 1 to clear OCIC */
1324
    if (val & OHCI_RHS_OCIC)
1325
        ohci->rhstatus &= ~OHCI_RHS_OCIC;
1326

    
1327
    if (val & OHCI_RHS_LPS) {
1328
        int i;
1329

    
1330
        for (i = 0; i < ohci->num_ports; i++)
1331
            ohci_port_power(ohci, i, 0);
1332
        DPRINTF("usb-ohci: powered down all ports\n");
1333
    }
1334

    
1335
    if (val & OHCI_RHS_LPSC) {
1336
        int i;
1337

    
1338
        for (i = 0; i < ohci->num_ports; i++)
1339
            ohci_port_power(ohci, i, 1);
1340
        DPRINTF("usb-ohci: powered up all ports\n");
1341
    }
1342

    
1343
    if (val & OHCI_RHS_DRWE)
1344
        ohci->rhstatus |= OHCI_RHS_DRWE;
1345

    
1346
    if (val & OHCI_RHS_CRWE)
1347
        ohci->rhstatus &= ~OHCI_RHS_DRWE;
1348

    
1349
    if (old_state != ohci->rhstatus)
1350
        ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1351
}
1352

    
1353
/* Set root hub port status */
1354
static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
1355
{
1356
    uint32_t old_state;
1357
    OHCIPort *port;
1358

    
1359
    port = &ohci->rhport[portnum];
1360
    old_state = port->ctrl;
1361

    
1362
    /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1363
    if (val & OHCI_PORT_WTC)
1364
        port->ctrl &= ~(val & OHCI_PORT_WTC);
1365

    
1366
    if (val & OHCI_PORT_CCS)
1367
        port->ctrl &= ~OHCI_PORT_PES;
1368

    
1369
    ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
1370

    
1371
    if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) {
1372
        DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum);
1373
    }
1374

    
1375
    if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
1376
        DPRINTF("usb-ohci: port %d: RESET\n", portnum);
1377
        usb_send_msg(port->port.dev, USB_MSG_RESET);
1378
        port->ctrl &= ~OHCI_PORT_PRS;
1379
        /* ??? Should this also set OHCI_PORT_PESC.  */
1380
        port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
1381
    }
1382

    
1383
    /* Invert order here to ensure in ambiguous case, device is
1384
     * powered up...
1385
     */
1386
    if (val & OHCI_PORT_LSDA)
1387
        ohci_port_power(ohci, portnum, 0);
1388
    if (val & OHCI_PORT_PPS)
1389
        ohci_port_power(ohci, portnum, 1);
1390

    
1391
    if (old_state != port->ctrl)
1392
        ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1393

    
1394
    return;
1395
}
1396

    
1397
static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr)
1398
{
1399
    OHCIState *ohci = ptr;
1400
    uint32_t retval;
1401

    
1402
    /* Only aligned reads are allowed on OHCI */
1403
    if (addr & 3) {
1404
        fprintf(stderr, "usb-ohci: Mis-aligned read\n");
1405
        return 0xffffffff;
1406
    } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1407
        /* HcRhPortStatus */
1408
        retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
1409
    } else {
1410
        switch (addr >> 2) {
1411
        case 0: /* HcRevision */
1412
            retval = 0x10;
1413
            break;
1414

    
1415
        case 1: /* HcControl */
1416
            retval = ohci->ctl;
1417
            break;
1418

    
1419
        case 2: /* HcCommandStatus */
1420
            retval = ohci->status;
1421
            break;
1422

    
1423
        case 3: /* HcInterruptStatus */
1424
            retval = ohci->intr_status;
1425
            break;
1426

    
1427
        case 4: /* HcInterruptEnable */
1428
        case 5: /* HcInterruptDisable */
1429
            retval = ohci->intr;
1430
            break;
1431

    
1432
        case 6: /* HcHCCA */
1433
            retval = ohci->hcca;
1434
            break;
1435

    
1436
        case 7: /* HcPeriodCurrentED */
1437
            retval = ohci->per_cur;
1438
            break;
1439

    
1440
        case 8: /* HcControlHeadED */
1441
            retval = ohci->ctrl_head;
1442
            break;
1443

    
1444
        case 9: /* HcControlCurrentED */
1445
            retval = ohci->ctrl_cur;
1446
            break;
1447

    
1448
        case 10: /* HcBulkHeadED */
1449
            retval = ohci->bulk_head;
1450
            break;
1451

    
1452
        case 11: /* HcBulkCurrentED */
1453
            retval = ohci->bulk_cur;
1454
            break;
1455

    
1456
        case 12: /* HcDoneHead */
1457
            retval = ohci->done;
1458
            break;
1459

    
1460
        case 13: /* HcFmInterretval */
1461
            retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
1462
            break;
1463

    
1464
        case 14: /* HcFmRemaining */
1465
            retval = ohci_get_frame_remaining(ohci);
1466
            break;
1467

    
1468
        case 15: /* HcFmNumber */
1469
            retval = ohci->frame_number;
1470
            break;
1471

    
1472
        case 16: /* HcPeriodicStart */
1473
            retval = ohci->pstart;
1474
            break;
1475

    
1476
        case 17: /* HcLSThreshold */
1477
            retval = ohci->lst;
1478
            break;
1479

    
1480
        case 18: /* HcRhDescriptorA */
1481
            retval = ohci->rhdesc_a;
1482
            break;
1483

    
1484
        case 19: /* HcRhDescriptorB */
1485
            retval = ohci->rhdesc_b;
1486
            break;
1487

    
1488
        case 20: /* HcRhStatus */
1489
            retval = ohci->rhstatus;
1490
            break;
1491

    
1492
        /* PXA27x specific registers */
1493
        case 24: /* HcStatus */
1494
            retval = ohci->hstatus & ohci->hmask;
1495
            break;
1496

    
1497
        case 25: /* HcHReset */
1498
            retval = ohci->hreset;
1499
            break;
1500

    
1501
        case 26: /* HcHInterruptEnable */
1502
            retval = ohci->hmask;
1503
            break;
1504

    
1505
        case 27: /* HcHInterruptTest */
1506
            retval = ohci->htest;
1507
            break;
1508

    
1509
        default:
1510
            fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr);
1511
            retval = 0xffffffff;
1512
        }
1513
    }
1514

    
1515
#ifdef TARGET_WORDS_BIGENDIAN
1516
    retval = bswap32(retval);
1517
#endif
1518
    return retval;
1519
}
1520

    
1521
static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val)
1522
{
1523
    OHCIState *ohci = ptr;
1524

    
1525
#ifdef TARGET_WORDS_BIGENDIAN
1526
    val = bswap32(val);
1527
#endif
1528

    
1529
    /* Only aligned reads are allowed on OHCI */
1530
    if (addr & 3) {
1531
        fprintf(stderr, "usb-ohci: Mis-aligned write\n");
1532
        return;
1533
    }
1534

    
1535
    if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1536
        /* HcRhPortStatus */
1537
        ohci_port_set_status(ohci, (addr - 0x54) >> 2, val);
1538
        return;
1539
    }
1540

    
1541
    switch (addr >> 2) {
1542
    case 1: /* HcControl */
1543
        ohci_set_ctl(ohci, val);
1544
        break;
1545

    
1546
    case 2: /* HcCommandStatus */
1547
        /* SOC is read-only */
1548
        val = (val & ~OHCI_STATUS_SOC);
1549

    
1550
        /* Bits written as '0' remain unchanged in the register */
1551
        ohci->status |= val;
1552

    
1553
        if (ohci->status & OHCI_STATUS_HCR)
1554
            ohci_reset(ohci);
1555
        break;
1556

    
1557
    case 3: /* HcInterruptStatus */
1558
        ohci->intr_status &= ~val;
1559
        ohci_intr_update(ohci);
1560
        break;
1561

    
1562
    case 4: /* HcInterruptEnable */
1563
        ohci->intr |= val;
1564
        ohci_intr_update(ohci);
1565
        break;
1566

    
1567
    case 5: /* HcInterruptDisable */
1568
        ohci->intr &= ~val;
1569
        ohci_intr_update(ohci);
1570
        break;
1571

    
1572
    case 6: /* HcHCCA */
1573
        ohci->hcca = val & OHCI_HCCA_MASK;
1574
        break;
1575

    
1576
    case 8: /* HcControlHeadED */
1577
        ohci->ctrl_head = val & OHCI_EDPTR_MASK;
1578
        break;
1579

    
1580
    case 9: /* HcControlCurrentED */
1581
        ohci->ctrl_cur = val & OHCI_EDPTR_MASK;
1582
        break;
1583

    
1584
    case 10: /* HcBulkHeadED */
1585
        ohci->bulk_head = val & OHCI_EDPTR_MASK;
1586
        break;
1587

    
1588
    case 11: /* HcBulkCurrentED */
1589
        ohci->bulk_cur = val & OHCI_EDPTR_MASK;
1590
        break;
1591

    
1592
    case 13: /* HcFmInterval */
1593
        ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
1594
        ohci->fit = (val & OHCI_FMI_FIT) >> 31;
1595
        ohci_set_frame_interval(ohci, val);
1596
        break;
1597

    
1598
    case 15: /* HcFmNumber */
1599
        break;
1600

    
1601
    case 16: /* HcPeriodicStart */
1602
        ohci->pstart = val & 0xffff;
1603
        break;
1604

    
1605
    case 17: /* HcLSThreshold */
1606
        ohci->lst = val & 0xffff;
1607
        break;
1608

    
1609
    case 18: /* HcRhDescriptorA */
1610
        ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK;
1611
        ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK;
1612
        break;
1613

    
1614
    case 19: /* HcRhDescriptorB */
1615
        break;
1616

    
1617
    case 20: /* HcRhStatus */
1618
        ohci_set_hub_status(ohci, val);
1619
        break;
1620

    
1621
    /* PXA27x specific registers */
1622
    case 24: /* HcStatus */
1623
        ohci->hstatus &= ~(val & ohci->hmask);
1624

    
1625
    case 25: /* HcHReset */
1626
        ohci->hreset = val & ~OHCI_HRESET_FSBIR;
1627
        if (val & OHCI_HRESET_FSBIR)
1628
            ohci_reset(ohci);
1629
        break;
1630

    
1631
    case 26: /* HcHInterruptEnable */
1632
        ohci->hmask = val;
1633
        break;
1634

    
1635
    case 27: /* HcHInterruptTest */
1636
        ohci->htest = val;
1637
        break;
1638

    
1639
    default:
1640
        fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr);
1641
        break;
1642
    }
1643
}
1644

    
1645
/* Only dword reads are defined on OHCI register space */
1646
static CPUReadMemoryFunc * const ohci_readfn[3]={
1647
    ohci_mem_read,
1648
    ohci_mem_read,
1649
    ohci_mem_read
1650
};
1651

    
1652
/* Only dword writes are defined on OHCI register space */
1653
static CPUWriteMemoryFunc * const ohci_writefn[3]={
1654
    ohci_mem_write,
1655
    ohci_mem_write,
1656
    ohci_mem_write
1657
};
1658

    
1659
static void usb_ohci_init(OHCIState *ohci, DeviceState *dev,
1660
                          int num_ports, uint32_t localmem_base)
1661
{
1662
    int i;
1663

    
1664
    if (usb_frame_time == 0) {
1665
#ifdef OHCI_TIME_WARP
1666
        usb_frame_time = get_ticks_per_sec();
1667
        usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ/1000);
1668
#else
1669
        usb_frame_time = muldiv64(1, get_ticks_per_sec(), 1000);
1670
        if (get_ticks_per_sec() >= USB_HZ) {
1671
            usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ);
1672
        } else {
1673
            usb_bit_time = 1;
1674
        }
1675
#endif
1676
        DPRINTF("usb-ohci: usb_bit_time=%" PRId64 " usb_frame_time=%" PRId64 "\n",
1677
                usb_frame_time, usb_bit_time);
1678
    }
1679

    
1680
    ohci->mem = cpu_register_io_memory(ohci_readfn, ohci_writefn, ohci);
1681
    ohci->localmem_base = localmem_base;
1682

    
1683
    ohci->name = dev->info->name;
1684

    
1685
    usb_bus_new(&ohci->bus, dev);
1686
    ohci->num_ports = num_ports;
1687
    for (i = 0; i < num_ports; i++) {
1688
        usb_register_port(&ohci->bus, &ohci->rhport[i].port, ohci, i, ohci_attach);
1689
    }
1690

    
1691
    ohci->async_td = 0;
1692
    qemu_register_reset(ohci_reset, ohci);
1693
}
1694

    
1695
typedef struct {
1696
    PCIDevice pci_dev;
1697
    OHCIState state;
1698
} OHCIPCIState;
1699

    
1700
static void ohci_mapfunc(PCIDevice *pci_dev, int i,
1701
            pcibus_t addr, pcibus_t size, int type)
1702
{
1703
    OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, pci_dev);
1704
    cpu_register_physical_memory(addr, size, ohci->state.mem);
1705
}
1706

    
1707
static int usb_ohci_initfn_pci(struct PCIDevice *dev)
1708
{
1709
    OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev);
1710
    int num_ports = 3;
1711

    
1712
    pci_config_set_vendor_id(ohci->pci_dev.config, PCI_VENDOR_ID_APPLE);
1713
    pci_config_set_device_id(ohci->pci_dev.config,
1714
                             PCI_DEVICE_ID_APPLE_IPID_USB);
1715
    ohci->pci_dev.config[PCI_CLASS_PROG] = 0x10; /* OHCI */
1716
    pci_config_set_class(ohci->pci_dev.config, PCI_CLASS_SERIAL_USB);
1717
    /* TODO: RST# value should be 0. */
1718
    ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
1719

    
1720
    usb_ohci_init(&ohci->state, &dev->qdev, num_ports, 0);
1721
    ohci->state.irq = ohci->pci_dev.irq[0];
1722

    
1723
    /* TODO: avoid cast below by using dev */
1724
    pci_register_bar((struct PCIDevice *)ohci, 0, 256,
1725
                           PCI_BASE_ADDRESS_SPACE_MEMORY, ohci_mapfunc);
1726
    return 0;
1727
}
1728

    
1729
void usb_ohci_init_pci(struct PCIBus *bus, int devfn)
1730
{
1731
    pci_create_simple(bus, devfn, "pci-ohci");
1732
}
1733

    
1734
typedef struct {
1735
    SysBusDevice busdev;
1736
    OHCIState ohci;
1737
    uint32_t num_ports;
1738
    target_phys_addr_t dma_offset;
1739
} OHCISysBusState;
1740

    
1741
static int ohci_init_pxa(SysBusDevice *dev)
1742
{
1743
    OHCISysBusState *s = FROM_SYSBUS(OHCISysBusState, dev);
1744

    
1745
    usb_ohci_init(&s->ohci, &dev->qdev, s->num_ports, s->dma_offset);
1746
    sysbus_init_irq(dev, &s->ohci.irq);
1747
    sysbus_init_mmio(dev, 0x1000, s->ohci.mem);
1748

    
1749
    return 0;
1750
}
1751

    
1752
static PCIDeviceInfo ohci_pci_info = {
1753
    .qdev.name    = "pci-ohci",
1754
    .qdev.desc    = "Apple USB Controller",
1755
    .qdev.size    = sizeof(OHCIPCIState),
1756
    .init         = usb_ohci_initfn_pci,
1757
};
1758

    
1759
static SysBusDeviceInfo ohci_sysbus_info = {
1760
    .init         = ohci_init_pxa,
1761
    .qdev.name    = "sysbus-ohci",
1762
    .qdev.desc    = "OHCI USB Controller",
1763
    .qdev.size    = sizeof(OHCISysBusState),
1764
    .qdev.props = (Property[]) {
1765
        DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
1766
        DEFINE_PROP_TADDR("dma-offset", OHCISysBusState, dma_offset, 3),
1767
        DEFINE_PROP_END_OF_LIST(),
1768
    }
1769
};
1770

    
1771
static void ohci_register(void)
1772
{
1773
    pci_qdev_register(&ohci_pci_info);
1774
    sysbus_register_withprop(&ohci_sysbus_info);
1775
}
1776
device_init(ohci_register);