Statistics
| Branch: | Revision:

root / hw / mips_r4k.c @ 6ae81775

History | View | Annotate | Download (7.9 kB)

1
#include "vl.h"
2

    
3
#define BIOS_FILENAME "mips_bios.bin"
4
//#define BIOS_FILENAME "system.bin"
5
#define KERNEL_LOAD_ADDR 0x80010000
6
#define INITRD_LOAD_ADDR 0x80800000
7

    
8
#define VIRT_TO_PHYS_ADDEND (-0x80000000LL)
9

    
10
static const int ide_iobase[2] = { 0x1f0, 0x170 };
11
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
12
static const int ide_irq[2] = { 14, 15 };
13

    
14
extern FILE *logfile;
15

    
16
static PITState *pit;
17

    
18
static void pic_irq_request(void *opaque, int level)
19
{
20
    CPUState *env = first_cpu;
21
    if (level) {
22
        env->CP0_Cause |= 0x00000400;
23
        cpu_interrupt(env, CPU_INTERRUPT_HARD);
24
    } else {
25
        env->CP0_Cause &= ~0x00000400;
26
        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
27
    }
28
}
29

    
30
void cpu_mips_irqctrl_init (void)
31
{
32
}
33

    
34
/* XXX: do not use a global */
35
uint32_t cpu_mips_get_random (CPUState *env)
36
{
37
    static uint32_t seed = 0;
38
    uint32_t idx;
39
    seed = seed * 314159 + 1;
40
    idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
41
    return idx;
42
}
43

    
44
/* MIPS R4K timer */
45
uint32_t cpu_mips_get_count (CPUState *env)
46
{
47
    return env->CP0_Count +
48
        (uint32_t)muldiv64(qemu_get_clock(vm_clock),
49
                           100 * 1000 * 1000, ticks_per_sec);
50
}
51

    
52
static void cpu_mips_update_count (CPUState *env, uint32_t count,
53
                                   uint32_t compare)
54
{
55
    uint64_t now, next;
56
    uint32_t tmp;
57
    
58
    tmp = count;
59
    if (count == compare)
60
        tmp++;
61
    now = qemu_get_clock(vm_clock);
62
    next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000);
63
    if (next == now)
64
        next++;
65
#if 0
66
    if (logfile) {
67
        fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n",
68
                __func__, now, count, compare, next - now);
69
    }
70
#endif
71
    /* Store new count and compare registers */
72
    env->CP0_Compare = compare;
73
    env->CP0_Count =
74
        count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec);
75
    /* Adjust timer */
76
    qemu_mod_timer(env->timer, next);
77
}
78

    
79
void cpu_mips_store_count (CPUState *env, uint32_t value)
80
{
81
    cpu_mips_update_count(env, value, env->CP0_Compare);
82
}
83

    
84
void cpu_mips_store_compare (CPUState *env, uint32_t value)
85
{
86
    cpu_mips_update_count(env, cpu_mips_get_count(env), value);
87
    env->CP0_Cause &= ~0x00008000;
88
    cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
89
}
90

    
91
static void mips_timer_cb (void *opaque)
92
{
93
    CPUState *env;
94

    
95
    env = opaque;
96
#if 0
97
    if (logfile) {
98
        fprintf(logfile, "%s\n", __func__);
99
    }
100
#endif
101
    cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
102
    env->CP0_Cause |= 0x00008000;
103
    cpu_interrupt(env, CPU_INTERRUPT_HARD);
104
}
105

    
106
void cpu_mips_clock_init (CPUState *env)
107
{
108
    env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);
109
    env->CP0_Compare = 0;
110
    cpu_mips_update_count(env, 1, 0);
111
}
112

    
113
static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
114
                              uint32_t val)
115
{
116
    if ((addr & 0xffff) == 0 && val == 42)
117
        qemu_system_reset_request ();
118
    else if ((addr & 0xffff) == 4 && val == 42)
119
        qemu_system_shutdown_request ();
120
}
121

    
122
static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
123
{
124
    return 0;
125
}
126

    
127
static CPUWriteMemoryFunc *mips_qemu_write[] = {
128
    &mips_qemu_writel,
129
    &mips_qemu_writel,
130
    &mips_qemu_writel,
131
};
132

    
133
static CPUReadMemoryFunc *mips_qemu_read[] = {
134
    &mips_qemu_readl,
135
    &mips_qemu_readl,
136
    &mips_qemu_readl,
137
};
138

    
139
static int mips_qemu_iomemtype = 0;
140

    
141
void load_kernel (CPUState *env, int ram_size, const char *kernel_filename,
142
                  const char *kernel_cmdline,
143
                  const char *initrd_filename)
144
{
145
    int64_t entry = 0;
146
    long kernel_size, initrd_size;
147

    
148
    kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry);
149
    if (kernel_size >= 0)
150
        env->PC = entry;
151
    else {
152
        kernel_size = load_image(kernel_filename,
153
                                 phys_ram_base + KERNEL_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
154
        if (kernel_size < 0) {
155
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
156
                    kernel_filename);
157
            exit(1);
158
        }
159
        env->PC = KERNEL_LOAD_ADDR;
160
    }
161

    
162
    /* load initrd */
163
    initrd_size = 0;
164
    if (initrd_filename) {
165
        initrd_size = load_image(initrd_filename,
166
                                 phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
167
        if (initrd_size == (target_ulong) -1) {
168
            fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
169
                    initrd_filename);
170
            exit(1);
171
        }
172
    }
173

    
174
    /* Store command line.  */
175
    if (initrd_size > 0) {
176
        int ret;
177
        ret = sprintf(phys_ram_base + (16 << 20) - 256,
178
                      "rd_start=0x%08x rd_size=%li ",
179
                      INITRD_LOAD_ADDR,
180
                      initrd_size);
181
        strcpy (phys_ram_base + (16 << 20) - 256 + ret, kernel_cmdline);
182
    }
183
    else {
184
        strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline);
185
    }
186

    
187
    *(int *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678);
188
    *(int *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size);
189
}
190

    
191
static void main_cpu_reset(void *opaque)
192
{
193
    CPUState *env = opaque;
194
    cpu_reset(env);
195

    
196
    if (env->kernel_filename)
197
        load_kernel (env, env->ram_size, env->kernel_filename,
198
                     env->kernel_cmdline, env->initrd_filename);
199
}
200

    
201
void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
202
                    DisplayState *ds, const char **fd_filename, int snapshot,
203
                    const char *kernel_filename, const char *kernel_cmdline,
204
                    const char *initrd_filename)
205
{
206
    char buf[1024];
207
    unsigned long bios_offset;
208
    int ret;
209
    CPUState *env;
210
    int i;
211

    
212
    env = cpu_init();
213
    register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
214
    qemu_register_reset(main_cpu_reset, env);
215

    
216
    /* allocate RAM */
217
    cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
218

    
219
    if (!mips_qemu_iomemtype) {
220
        mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read,
221
                                                     mips_qemu_write, NULL);
222
    }
223
    cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);
224

    
225
    /* Try to load a BIOS image. If this fails, we continue regardless,
226
       but initialize the hardware ourselves. When a kernel gets
227
       preloaded we also initialize the hardware, since the BIOS wasn't
228
       run. */
229
    bios_offset = ram_size + vga_ram_size;
230
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
231
    ret = load_image(buf, phys_ram_base + bios_offset);
232
    if (ret == BIOS_SIZE) {
233
        cpu_register_physical_memory((uint32_t)(0x1fc00000),
234
                                     BIOS_SIZE, bios_offset | IO_MEM_ROM);
235
    } else {
236
        /* not fatal */
237
        fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
238
                buf);
239
    }
240

    
241
    if (kernel_filename) {
242
        load_kernel (env, ram_size, kernel_filename, kernel_cmdline,
243
                     initrd_filename);
244
        env->ram_size = ram_size;
245
        env->kernel_filename = kernel_filename;
246
        env->kernel_cmdline = kernel_cmdline;
247
        env->initrd_filename = initrd_filename;
248
    }
249

    
250
    /* Init internal devices */
251
    cpu_mips_clock_init(env);
252
    cpu_mips_irqctrl_init();
253

    
254
    /* Register 64 KB of ISA IO space at 0x14000000 */
255
    isa_mmio_init(0x14000000, 0x00010000);
256
    isa_mem_base = 0x10000000;
257

    
258
    isa_pic = pic_init(pic_irq_request, env);
259
    pit = pit_init(0x40, 0);
260
    serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
261
    isa_vga_init(ds, phys_ram_base + ram_size, ram_size, 
262
                 vga_ram_size);
263

    
264
    if (nd_table[0].vlan) {
265
        if (nd_table[0].model == NULL
266
            || strcmp(nd_table[0].model, "ne2k_isa") == 0) {
267
            isa_ne2000_init(0x300, 9, &nd_table[0]);
268
        } else {
269
            fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
270
            exit (1);
271
        }
272
    }
273

    
274
    for(i = 0; i < 2; i++)
275
        isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
276
                     bs_table[2 * i], bs_table[2 * i + 1]);
277
}
278

    
279
QEMUMachine mips_machine = {
280
    "mips",
281
    "mips r4k platform",
282
    mips_r4k_init,
283
};