Archipelago » qemu

endif # TARGET_ARCH = ppc

ifeq ($(TARGET_ARCH), mips)

endif # TARGET_ARCH = mips

ifeq ($(TARGET_ARCH), mips)

LIBOBJS+= op_helper.o helper.o

endif

ifeq ($(findstring mips, $(TARGET_ARCH) $(ARCH)),mips)

LIBOBJS+=mips-dis.o

endif

ifeq ($(TARGET_ARCH), mips)

VL_OBJS+= mips.o mips_r4k.o dma.o vga.o serial.o #ide.o ne2000.o pckbd.o

VL_OBJS+= #i8259.o i8254.o fdc.o m48t59.o

endif

ifeq ($(TARGET_ARCH), mips)

op.o: op.c op_template.c op_mem.c

op_helper.o: op_helper_mem.c

endif

#elif defined(TARGET_MIPS)

#define CPUState CPUMIPSState

#define cpu_init cpu_mips_init

#define cpu_exec cpu_mips_exec

#define cpu_gen_code cpu_mips_gen_code

#define cpu_signal_handler cpu_mips_signal_handler

#elif defined(TARGET_MIPS)

#elif defined(TARGET_MIPS)

                    do_interrupt(env);

#elif defined(TARGET_MIPS)

                    if ((interrupt_request & CPU_INTERRUPT_HARD) &&

                        (env->CP0_Status & (1 << CP0St_IE)) &&

                        (env->CP0_Cause & 0x0000FC00) &&

                        !(env->hflags & MIPS_HFLAG_EXL) &&

                        !(env->hflags & MIPS_HFLAG_ERL) &&

                        !(env->hflags & MIPS_HFLAG_DM)) {

                        /* Raise it */

                        env->exception_index = EXCP_EXT_INTERRUPT;

                        env->error_code = 0;

                        do_interrupt(env);

                        env->interrupt_request &= ~CPU_INTERRUPT_HARD;

                    }

#elif defined(TARGET_MIPS)

                    cpu_dump_state(env, logfile, fprintf, 0);

#elif defined(TARGET_MIPS)

                flags = env->hflags & MIPS_HFLAGS_TMASK;

                cs_base = NULL;

                pc = env->PC;

#elif defined(TARGET_MIPS)

#elif defined (TARGET_MIPS)

static inline int handle_cpu_signal(unsigned long pc, unsigned long address,

                                    int is_write, sigset_t *old_set,

                                    void *puc)

{

    TranslationBlock *tb;

    int ret;

    if (cpu_single_env)

        env = cpu_single_env; /* XXX: find a correct solution for multithread */

#if defined(DEBUG_SIGNAL)

    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", 

           pc, address, is_write, *(unsigned long *)old_set);

#endif

    /* XXX: locking issue */

    if (is_write && page_unprotect(address, pc, puc)) {

        return 1;

    }

    /* see if it is an MMU fault */

    ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);

    if (ret < 0)

        return 0; /* not an MMU fault */

    if (ret == 0)

        return 1; /* the MMU fault was handled without causing real CPU fault */

    /* now we have a real cpu fault */

    tb = tb_find_pc(pc);

    if (tb) {

        /* the PC is inside the translated code. It means that we have

           a virtual CPU fault */

        cpu_restore_state(tb, env, pc, puc);

    }

    if (ret == 1) {

#if 0

        printf("PF exception: NIP=0x%08x error=0x%x %p\n", 

               env->nip, env->error_code, tb);

#endif

    /* we restore the process signal mask as the sigreturn should

       do it (XXX: use sigsetjmp) */

        sigprocmask(SIG_SETMASK, old_set, NULL);

        do_raise_exception_err(env->exception_index, env->error_code);

    } else {

        /* activate soft MMU for this block */

        cpu_resume_from_signal(env, puc);

    }

    /* never comes here */

    return 1;

}

bfd_vma bfd_getl16 (const bfd_byte *addr);

bfd_vma bfd_getb16 (const bfd_byte *addr);

bfd_vma bfd_getl16 (const bfd_byte *addr)

{

  unsigned long v;

  v = (unsigned long) addr[0];

  v |= (unsigned long) addr[1] << 8;

  return (bfd_vma) v;

}

bfd_vma bfd_getb16 (const bfd_byte *addr)

{

  unsigned long v;

  v = (unsigned long) addr[0] << 24;

  v |= (unsigned long) addr[1] << 16;

  return (bfd_vma) v;

}

#elif defined(TARGET_MIPS)

    print_insn = print_insn_big_mips;

#elif defined(__MIPSEB__)

    print_insn = print_insn_big_mips;

#elif defined(__MIPSEL__)

    print_insn = print_insn_little_mips;

#elif defined(TARGET_MIPS)

    print_insn = print_insn_big_mips;

#define PT_MIPS_OPTIONS		0x70000001

/* MIPS architecture level. */

#define EF_MIPS_ARCH_1		0x00000000	/* -mips1 code.  */

#define EF_MIPS_ARCH_2		0x10000000	/* -mips2 code.  */

#define EF_MIPS_ARCH_3		0x20000000	/* -mips3 code.  */

#define EF_MIPS_ARCH_4		0x30000000	/* -mips4 code.  */

#define EF_MIPS_ARCH_5		0x40000000	/* -mips5 code.  */

#define EF_MIPS_ARCH_32		0x50000000	/* MIPS32 code.  */

#define EF_MIPS_ARCH_64		0x60000000	/* MIPS64 code.  */

/* The ABI of a file. */

#define EF_MIPS_ABI_O32		0x00001000	/* O32 ABI.  */

#define EF_MIPS_ABI_O64		0x00002000	/* O32 extended for 64 bit.  */

#define EF_MIPS_ABI2		0x00000020

#define EF_MIPS_OPTIONS_FIRST	0x00000080

#define EF_MIPS_32BITMODE	0x00000100

#define EF_MIPS_ABI		0x0000f000

#elif defined (TARGET_MIPS)

    is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);

#include "vl.h"

#define DEBUG_IRQ_COUNT

#define BIOS_FILENAME "mips_bios.bin"

//#define BIOS_FILENAME "system.bin"

#define KERNEL_LOAD_ADDR 0x80010000

#define INITRD_LOAD_ADDR 0x80800000

/* MIPS R4K IRQ controler */

#if defined(DEBUG_IRQ_COUNT)

static uint64_t irq_count[16];

#endif

extern FILE *logfile;

void mips_set_irq (int n_IRQ, int level)

{

    uint32_t mask;

    if (n_IRQ < 0 || n_IRQ >= 8)

        return;

    mask = 0x100 << n_IRQ;

    if (level != 0) {

#if 1

        if (logfile) {

            fprintf(logfile, "%s n %d l %d mask %08x %08x\n",

                    __func__, n_IRQ, level, mask, cpu_single_env->CP0_Status);

        }

#endif

        cpu_single_env->CP0_Cause |= mask;

        if ((cpu_single_env->CP0_Status & 0x00000001) &&

            (cpu_single_env->CP0_Status & mask)) {

#if defined(DEBUG_IRQ_COUNT)

            irq_count[n_IRQ]++;

#endif

#if 1

            if (logfile)

                fprintf(logfile, "%s raise IRQ\n", __func__);

#endif

            cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);

        }

    } else {

        cpu_single_env->CP0_Cause &= ~mask;

    }

}

void pic_set_irq (int n_IRQ, int level)

{

    mips_set_irq(n_IRQ + 2, level);

}

void pic_info (void)

{

    term_printf("IRQ asserted: %02x mask: %02x\n",

                (cpu_single_env->CP0_Cause >> 8) & 0xFF,

                (cpu_single_env->CP0_Status >> 8) & 0xFF);

}

void irq_info (void)

{

#if !defined(DEBUG_IRQ_COUNT)

    term_printf("irq statistic code not compiled.\n");

#else

    int i;

    int64_t count;

    term_printf("IRQ statistics:\n");

    for (i = 0; i < 8; i++) {

        count = irq_count[i];

        if (count > 0)

            term_printf("%2d: %lld\n", i, count);

    }

#endif

}

void cpu_mips_irqctrl_init (void)

{

}

/* MIPS R4K timer */

uint32_t cpu_mips_get_random (CPUState *env)

{

    uint64_t now = qemu_get_clock(vm_clock);

    return (uint32_t)now & 0x0000000F;

}

uint32_t cpu_mips_get_count (CPUState *env)

{

    return env->CP0_Count +

        (uint32_t)muldiv64(qemu_get_clock(vm_clock),

                           100 * 1000 * 1000, ticks_per_sec);

}

static void cpu_mips_update_count (CPUState *env, uint32_t count,

                                   uint32_t compare)

{

    uint64_t now, next;

    uint32_t tmp;

    tmp = count;

    if (count == compare)

        tmp++;

    now = qemu_get_clock(vm_clock);

    next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000);

    if (next == now)

	next++;

#if 1

    if (logfile) {

        fprintf(logfile, "%s: 0x%08llx %08x %08x => 0x%08llx\n",

                __func__, now, count, compare, next - now);

    }

#endif

    /* Store new count and compare registers */

    env->CP0_Compare = compare;

    env->CP0_Count =

        count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec);

    /* Adjust timer */

    qemu_mod_timer(env->timer, next);

}

void cpu_mips_store_count (CPUState *env, uint32_t value)

{

    cpu_mips_update_count(env, value, env->CP0_Compare);

}

void cpu_mips_store_compare (CPUState *env, uint32_t value)

{

    cpu_mips_update_count(env, cpu_mips_get_count(env), value);

    pic_set_irq(5, 0);

}

static void mips_timer_cb (void *opaque)

{

    CPUState *env;

    env = opaque;

#if 1

    if (logfile) {

        fprintf(logfile, "%s\n", __func__);

    }

#endif

    cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);

    pic_set_irq(5, 1);

}

void cpu_mips_clock_init (CPUState *env)

{

    env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);

    env->CP0_Compare = 0;

    cpu_mips_update_count(env, 1, 0);

}

static void io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)

{

    if (logfile)

        fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);

    cpu_outb(NULL, addr & 0xffff, value);

}

static uint32_t io_readb (void *opaque, target_phys_addr_t addr)

{

    uint32_t ret = cpu_inb(NULL, addr & 0xffff);

    if (logfile)

        fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);

    return ret;

}

static void io_writew (void *opaque, target_phys_addr_t addr, uint32_t value)

{

    if (logfile)

        fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);

#ifdef TARGET_WORDS_BIGENDIAN

    value = bswap16(value);

#endif

    cpu_outw(NULL, addr & 0xffff, value);

}

static uint32_t io_readw (void *opaque, target_phys_addr_t addr)

{

    uint32_t ret = cpu_inw(NULL, addr & 0xffff);

#ifdef TARGET_WORDS_BIGENDIAN

    ret = bswap16(ret);

#endif

    if (logfile)

        fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);

    return ret;

}

static void io_writel (void *opaque, target_phys_addr_t addr, uint32_t value)

{

    if (logfile)

        fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);

#ifdef TARGET_WORDS_BIGENDIAN

    value = bswap32(value);

#endif

    cpu_outl(NULL, addr & 0xffff, value);

}

static uint32_t io_readl (void *opaque, target_phys_addr_t addr)

{

    uint32_t ret = cpu_inl(NULL, addr & 0xffff);

#ifdef TARGET_WORDS_BIGENDIAN

    ret = bswap32(ret);

#endif

    if (logfile)

        fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);

    return ret;

}

CPUWriteMemoryFunc *io_write[] = {

    &io_writeb,

    &io_writew,

    &io_writel,

};

CPUReadMemoryFunc *io_read[] = {

    &io_readb,

    &io_readw,

    &io_readl,

};

void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,

                    DisplayState *ds, const char **fd_filename, int snapshot,

                    const char *kernel_filename, const char *kernel_cmdline,

                    const char *initrd_filename)

{

    char buf[1024];

    target_ulong kernel_base, kernel_size, initrd_base, initrd_size;

    unsigned long bios_offset;

    int io_memory;

    int linux_boot;

    int ret;

    printf("%s: start\n", __func__);

    linux_boot = (kernel_filename != NULL);

    /* allocate RAM */

    cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);

    bios_offset = ram_size + vga_ram_size;

    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);

    printf("%s: load BIOS '%s' size %d\n", __func__, buf, BIOS_SIZE);

    ret = load_image(buf, phys_ram_base + bios_offset);

    if (ret != BIOS_SIZE) {

        fprintf(stderr, "qemu: could not load MIPS bios '%s'\n", buf);

        exit(1);

    }

    cpu_register_physical_memory((uint32_t)(0x1fc00000),

                                 BIOS_SIZE, bios_offset | IO_MEM_ROM);

#if 0

    memcpy(phys_ram_base + 0x10000, phys_ram_base + bios_offset, BIOS_SIZE);

    cpu_single_env->PC = 0x80010004;

#else

    cpu_single_env->PC = 0xBFC00004;

#endif

    if (linux_boot) {

        kernel_base = KERNEL_LOAD_ADDR;

        /* now we can load the kernel */

        kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);

        if (kernel_size < 0) {

            fprintf(stderr, "qemu: could not load kernel '%s'\n", 

                    kernel_filename);

            exit(1);

        }

        /* load initrd */

        if (initrd_filename) {

            initrd_base = INITRD_LOAD_ADDR;

            initrd_size = load_image(initrd_filename,

                                     phys_ram_base + initrd_base);

            if (initrd_size < 0) {

                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 

                        initrd_filename);

                exit(1);

            }

        } else {

            initrd_base = 0;

            initrd_size = 0;

        }

        cpu_single_env->PC = KERNEL_LOAD_ADDR;

    } else {

        kernel_base = 0;

        kernel_size = 0;

        initrd_base = 0;

        initrd_size = 0;

    }

    /* XXX: should not be ! */

    printf("%s: init VGA\n", __func__);

    vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size, 

                   vga_ram_size);

    /* Init internal devices */

    cpu_mips_clock_init(cpu_single_env);

    cpu_mips_irqctrl_init();

    isa_mem_base = 0x78000000;

    /* Register 64 KB of ISA IO space at random address */

    io_memory = cpu_register_io_memory(0, io_read, io_write, NULL);

    cpu_register_physical_memory(0x70000000, 0x00010000, io_memory);

    serial_init(0x3f8, 4, serial_hds[0]);

    printf("%s: done\n", __func__);

}

QEMUMachine mips_machine = {

    "mips",

    "mips r4k platform",

    mips_r4k_init,

};

#elif defined (TARGET_MIPS)

#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)

#elif defined (TARGET_MIPS)

#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)

#if !defined (__MIPS_CPU_H__)

#define __MIPS_CPU_H__

#include "mips-defs.h"

#include "cpu-defs.h"

#include "config.h"

#include "softfloat.h"

typedef union fpr_t fpr_t;

union fpr_t {

    double d;

    float  f;

    uint32_t u[2];

};

#if defined(MIPS_USES_R4K_TLB)

typedef struct tlb_t tlb_t;

struct tlb_t {

    target_ulong VPN;

    target_ulong end;

    uint8_t ASID;

    uint8_t G;

    uint8_t C[2];

    uint8_t V[2];

    uint8_t D[2];

    target_ulong PFN[2];

};

#endif

typedef struct CPUMIPSState CPUMIPSState;

struct CPUMIPSState {

    /* General integer registers */

    target_ulong gpr[32];

    /* Special registers */

    target_ulong PC;

    uint32_t HI, LO;

    uint32_t DCR; /* ? */

#if defined(MIPS_USES_FPU)

    /* Floating point registers */

    fpr_t fpr[16];

    /* Floating point special purpose registers */

    uint32_t fcr0;

    uint32_t fcr25;

    uint32_t fcr26;

    uint32_t fcr28;

    uint32_t fcsr;

#endif

#if defined(MIPS_USES_R4K_TLB)

    tlb_t tlb[16];

#endif

    uint32_t CP0_index;

    uint32_t CP0_random;

    uint32_t CP0_EntryLo0;

    uint32_t CP0_EntryLo1;

    uint32_t CP0_Context;

    uint32_t CP0_PageMask;

    uint32_t CP0_Wired;

    uint32_t CP0_BadVAddr;

    uint32_t CP0_Count;

    uint32_t CP0_EntryHi;

    uint32_t CP0_Compare;

    uint32_t CP0_Status;

#define CP0St_CU3   31

#define CP0St_CU2   30

#define CP0St_CU1   29

#define CP0St_CU0   28

#define CP0St_RP    27

#define CP0St_RE    25

#define CP0St_BEV   22

#define CP0St_TS    21

#define CP0St_SR    20

#define CP0St_NMI   19

#define CP0St_IM    8

#define CP0St_UM    4

#define CP0St_ERL   2

#define CP0St_EXL   1

#define CP0St_IE    0

    uint32_t CP0_Cause;

#define CP0Ca_IV   23

    uint32_t CP0_EPC;

    uint32_t CP0_PRid;

    uint32_t CP0_Config0;

#define CP0C0_M    31

#define CP0C0_K23  28

#define CP0C0_KU   25

#define CP0C0_MDU  20

#define CP0C0_MM   17

#define CP0C0_BM   16

#define CP0C0_BE   15

#define CP0C0_AT   13

#define CP0C0_AR   10

#define CP0C0_MT   7

#define CP0C0_K0   0

    uint32_t CP0_Config1;

#define CP0C1_MMU  25

#define CP0C1_IS   22

#define CP0C1_IL   19

#define CP0C1_IA   16

#define CP0C1_DS   13

#define CP0C1_DL   10

#define CP0C1_DA   7

#define CP0C1_PC   4

#define CP0C1_WR   3

#define CP0C1_CA   2

#define CP0C1_EP   1

#define CP0C1_FP   0

    uint32_t CP0_LLAddr;

    uint32_t CP0_WatchLo;

    uint32_t CP0_WatchHi;

    uint32_t CP0_Debug;

#define CPDB_DBD   31

#define CP0DB_DM   30

#define CP0DB_LSNM 28

#define CP0DB_Doze 27

#define CP0DB_Halt 26

#define CP0DB_CNT  25

#define CP0DB_IBEP 24

#define CP0DB_DBEP 21

#define CP0DB_IEXI 20

#define CP0DB_VER  15

#define CP0DB_DEC  10

#define CP0DB_SSt  8

#define CP0DB_DINT 5

#define CP0DB_DIB  4

#define CP0DB_DDBS 3

#define CP0DB_DDBL 2

#define CP0DB_DBp  1

#define CP0DB_DSS  0

    uint32_t CP0_DEPC;

    uint32_t CP0_TagLo;

    uint32_t CP0_DataLo;

    uint32_t CP0_ErrorEPC;

    uint32_t CP0_DESAVE;

    /* Qemu */

#if defined (USE_HOST_FLOAT_REGS) && defined(MIPS_USES_FPU)

    double ft0, ft1, ft2;

#endif

    struct QEMUTimer *timer; /* Internal timer */

    int interrupt_request;

    jmp_buf jmp_env;

    int exception_index;

    int error_code;

    int user_mode_only; /* user mode only simulation */

    uint32_t hflags;    /* CPU State */

    /* TMASK defines different execution modes */

#define MIPS_HFLAGS_TMASK 0x00FF

#define MIPS_HFLAG_MODE   0x001F /* execution modes                    */

#define MIPS_HFLAG_UM     0x0001 /* user mode                          */

#define MIPS_HFLAG_ERL    0x0002 /* Error mode                         */

#define MIPS_HFLAG_EXL    0x0004 /* Exception mode                     */

#define MIPS_HFLAG_DM     0x0008 /* Debug mode                         */

#define MIPS_HFLAG_SM     0x0010 /* Supervisor mode                    */

#define MIPS_HFLAG_RE     0x0040 /* Reversed endianness                */

#define MIPS_HFLAG_DS     0x0080 /* In / out of delay slot             */

    /* Those flags keep the branch state if the translation is interrupted

     * between the branch instruction and the delay slot

     */

#define MIPS_HFLAG_BMASK  0x0F00

#define MIPS_HFLAG_B      0x0100 /* Unconditional branch               */

#define MIPS_HFLAG_BC     0x0200 /* Conditional branch                 */

#define MIPS_HFLAG_BL     0x0400 /* Likely branch                      */

#define MIPS_HFLAG_BR     0x0800 /* branch to register (can't link TB) */

    target_ulong btarget;        /* Jump / branch target               */

    int bcond;                   /* Branch condition (if needed)       */

    struct TranslationBlock *current_tb; /* currently executing TB  */

    /* soft mmu support */

    /* in order to avoid passing too many arguments to the memory

       write helpers, we store some rarely used information in the CPU

       context) */

    target_ulong mem_write_pc; /* host pc at which the memory was

                                   written */

    unsigned long mem_write_vaddr; /* target virtual addr at which the

                                      memory was written */

    /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */

    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];

    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];

    /* ice debug support */

    target_ulong breakpoints[MAX_BREAKPOINTS];

    int nb_breakpoints;

    int singlestep_enabled; /* XXX: should use CPU single step mode instead */

    /* user data */

    void *opaque;

};

#include "cpu-all.h"

/* Memory access type :

 * may be needed for precise access rights control and precise exceptions.

 */

enum {

    /* 1 bit to define user level / supervisor access */

    ACCESS_USER  = 0x00,

    ACCESS_SUPER = 0x01,

    /* 1 bit to indicate direction */

    ACCESS_STORE = 0x02,

    /* Type of instruction that generated the access */

    ACCESS_CODE  = 0x10, /* Code fetch access                */

    ACCESS_INT   = 0x20, /* Integer load/store access        */

    ACCESS_FLOAT = 0x30, /* floating point load/store access */

};

/* Exceptions */

enum {

    EXCP_NONE          = -1,

    EXCP_RESET         = 0,

    EXCP_SRESET,

    EXCP_DSS,

    EXCP_DINT,

    EXCP_NMI,

    EXCP_MCHECK,

    EXCP_EXT_INTERRUPT,

    EXCP_DFWATCH,

    EXCP_DIB, /* 8 */

    EXCP_IWATCH,

    EXCP_AdEL,

    EXCP_AdES,

    EXCP_TLBF,

    EXCP_IBE,

    EXCP_DBp,

    EXCP_SYSCALL,

    EXCP_BREAK,

    EXCP_CpU, /* 16 */

    EXCP_RI,

    EXCP_OVERFLOW,

    EXCP_TRAP,

    EXCP_DDBS,

    EXCP_DWATCH,

    EXCP_LAE, /* 22 */

    EXCP_SAE,

    EXCP_LTLBL,

    EXCP_TLBL,

    EXCP_TLBS,

    EXCP_DBE,

    EXCP_DDBL,

    EXCP_MTCP0         = 0x104, /* mtmsr instruction:               */

                                /* may change privilege level       */

    EXCP_BRANCH        = 0x108, /* branch instruction               */

    EXCP_ERET          = 0x10C, /* return from interrupt            */

    EXCP_SYSCALL_USER  = 0x110, /* System call in user mode only    */

    EXCP_FLUSH         = 0x109,

};

/* MIPS opcodes */

#define EXT_SPECIAL  0x100

#define EXT_SPECIAL2 0x200

#define EXT_REGIMM   0x300

#define EXT_CP0      0x400

#define EXT_CP1      0x500

#define EXT_CP2      0x600

#define EXT_CP3      0x700

enum {

    /* indirect opcode tables */

    OPC_SPECIAL  = 0x00,

    OPC_BREGIMM  = 0x01,

    OPC_CP0      = 0x10,

    OPC_CP1      = 0x11,

    OPC_CP2      = 0x12,

    OPC_CP3      = 0x13,

    OPC_SPECIAL2 = 0x1C,

    /* arithmetic with immediate */

    OPC_ADDI     = 0x08,

    OPC_ADDIU    = 0x09,

    OPC_SLTI     = 0x0A,

    OPC_SLTIU    = 0x0B,

    OPC_ANDI     = 0x0C,

    OPC_ORI      = 0x0D,

    OPC_XORI     = 0x0E,

    OPC_LUI      = 0x0F,

    /* Jump and branches */

    OPC_J        = 0x02,

    OPC_JAL      = 0x03,

    OPC_BEQ      = 0x04,  /* Unconditional if rs = rt = 0 (B) */

    OPC_BEQL     = 0x14,

    OPC_BNE      = 0x05,

    OPC_BNEL     = 0x15,

    OPC_BLEZ     = 0x06,

    OPC_BLEZL    = 0x16,

    OPC_BGTZ     = 0x07,

    OPC_BGTZL    = 0x17,

    OPC_JALX     = 0x1D,  /* MIPS 16 only */

    /* Load and stores */

    OPC_LB       = 0x20,

    OPC_LH       = 0x21,

    OPC_LWL      = 0x22,

    OPC_LW       = 0x23,

    OPC_LBU      = 0x24,

    OPC_LHU      = 0x25,

    OPC_LWR      = 0x26,

    OPC_SB       = 0x28,

    OPC_SH       = 0x29,

    OPC_SWL      = 0x2A,

    OPC_SW       = 0x2B,

    OPC_SWR      = 0x2E,

    OPC_LL       = 0x30,

    OPC_SC       = 0x38,

    /* Floating point load/store */

    OPC_LWC1     = 0x31,

    OPC_LWC2     = 0x32,

    OPC_LDC1     = 0x35,

    OPC_LDC2     = 0x36,

    OPC_SWC1     = 0x39,

    OPC_SWC2     = 0x3A,

    OPC_SDC1     = 0x3D,

    OPC_SDC2     = 0x3E,

    /* Cache and prefetch */

    OPC_CACHE    = 0x2F,

    OPC_PREF     = 0x33,

};

/* MIPS special opcodes */

enum {

    /* Shifts */

    OPC_SLL      = 0x00 | EXT_SPECIAL,

    /* NOP is SLL r0, r0, 0   */

    /* SSNOP is SLL r0, r0, 1 */

    OPC_SRL      = 0x02 | EXT_SPECIAL,

    OPC_SRA      = 0x03 | EXT_SPECIAL,

    OPC_SLLV     = 0x04 | EXT_SPECIAL,

    OPC_SRLV     = 0x06 | EXT_SPECIAL,

    OPC_SRAV     = 0x07 | EXT_SPECIAL,

    /* Multiplication / division */

    OPC_MULT     = 0x18 | EXT_SPECIAL,

    OPC_MULTU    = 0x19 | EXT_SPECIAL,

    OPC_DIV      = 0x1A | EXT_SPECIAL,

    OPC_DIVU     = 0x1B | EXT_SPECIAL,

    /* 2 registers arithmetic / logic */

    OPC_ADD      = 0x20 | EXT_SPECIAL,

    OPC_ADDU     = 0x21 | EXT_SPECIAL,

    OPC_SUB      = 0x22 | EXT_SPECIAL,

    OPC_SUBU     = 0x23 | EXT_SPECIAL,

    OPC_AND      = 0x24 | EXT_SPECIAL,

    OPC_OR       = 0x25 | EXT_SPECIAL,

    OPC_XOR      = 0x26 | EXT_SPECIAL,

    OPC_NOR      = 0x27 | EXT_SPECIAL,

    OPC_SLT      = 0x2A | EXT_SPECIAL,

    OPC_SLTU     = 0x2B | EXT_SPECIAL,

    /* Jumps */

    OPC_JR       = 0x08 | EXT_SPECIAL,

    OPC_JALR     = 0x09 | EXT_SPECIAL,

    /* Traps */

    OPC_TGE      = 0x30 | EXT_SPECIAL,

    OPC_TGEU     = 0x31 | EXT_SPECIAL,

    OPC_TLT      = 0x32 | EXT_SPECIAL,

    OPC_TLTU     = 0x33 | EXT_SPECIAL,

    OPC_TEQ      = 0x34 | EXT_SPECIAL,

    OPC_TNE      = 0x36 | EXT_SPECIAL,

    /* HI / LO registers load & stores */

    OPC_MFHI     = 0x10 | EXT_SPECIAL,

    OPC_MTHI     = 0x11 | EXT_SPECIAL,

    OPC_MFLO     = 0x12 | EXT_SPECIAL,

    OPC_MTLO     = 0x13 | EXT_SPECIAL,

    /* Conditional moves */

    OPC_MOVZ     = 0x0A | EXT_SPECIAL,

    OPC_MOVN     = 0x0B | EXT_SPECIAL,

    OPC_MOVCI    = 0x01 | EXT_SPECIAL,

    /* Special */

    OPC_PMON     = 0x05 | EXT_SPECIAL,

    OPC_SYSCALL  = 0x0C | EXT_SPECIAL,

    OPC_BREAK    = 0x0D | EXT_SPECIAL,

    OPC_SYNC     = 0x0F | EXT_SPECIAL,

};

enum {

    /* Mutiply & xxx operations */

    OPC_MADD     = 0x00 | EXT_SPECIAL2,

    OPC_MADDU    = 0x01 | EXT_SPECIAL2,

    OPC_MUL      = 0x02 | EXT_SPECIAL2,

    OPC_MSUB     = 0x04 | EXT_SPECIAL2,

    OPC_MSUBU    = 0x05 | EXT_SPECIAL2,

    /* Misc */

    OPC_CLZ      = 0x20 | EXT_SPECIAL2,

    OPC_CLO      = 0x21 | EXT_SPECIAL2,

    /* Special */

    OPC_SDBBP    = 0x3F | EXT_SPECIAL2,

};

/* Branch REGIMM */

enum {

    OPC_BLTZ     = 0x00 | EXT_REGIMM,

    OPC_BLTZL    = 0x02 | EXT_REGIMM,

    OPC_BGEZ     = 0x01 | EXT_REGIMM,

    OPC_BGEZL    = 0x03 | EXT_REGIMM,

    OPC_BLTZAL   = 0x10 | EXT_REGIMM,

    OPC_BLTZALL  = 0x12 | EXT_REGIMM,

    OPC_BGEZAL   = 0x11 | EXT_REGIMM,

    OPC_BGEZALL  = 0x13 | EXT_REGIMM,

    OPC_TGEI     = 0x08 | EXT_REGIMM,

    OPC_TGEIU    = 0x09 | EXT_REGIMM,

    OPC_TLTI     = 0x0A | EXT_REGIMM,

    OPC_TLTIU    = 0x0B | EXT_REGIMM,

    OPC_TEQI     = 0x0C | EXT_REGIMM,

    OPC_TNEI     = 0x0E | EXT_REGIMM,

};

enum {

    /* Coprocessor 0 (MMU) */

    OPC_MFC0     = 0x00 | EXT_CP0,

    OPC_MTC0     = 0x04 | EXT_CP0,

    OPC_TLBR     = 0x01 | EXT_CP0,

    OPC_TLBWI    = 0x02 | EXT_CP0,

    OPC_TLBWR    = 0x06 | EXT_CP0,

    OPC_TLBP     = 0x08 | EXT_CP0,

    OPC_ERET     = 0x18 | EXT_CP0,

    OPC_DERET    = 0x1F | EXT_CP0,

    OPC_WAIT     = 0x20 | EXT_CP0,

};

int cpu_mips_exec(CPUMIPSState *s);

CPUMIPSState *cpu_mips_init(void);

uint32_t cpu_mips_get_clock (void);

#endif /* !defined (__MIPS_CPU_H__) */

#if !defined(__QEMU_MIPS_EXEC_H__)

#define __QEMU_MIPS_EXEC_H__

#define DEBUG_OP

#include "mips-defs.h"

#include "dyngen-exec.h"

register struct CPUMIPSState *env asm(AREG0);

#if defined (USE_64BITS_REGS)

typedef int64_t host_int_t;

typedef uint64_t host_uint_t;

#else

typedef int32_t host_int_t;

typedef uint32_t host_uint_t;

#endif

register host_uint_t T0 asm(AREG1);

register host_uint_t T1 asm(AREG2);

register host_uint_t T2 asm(AREG3);

register host_int_t Ts0 asm(AREG1);

register host_int_t Ts1 asm(AREG2);

register host_int_t Ts2 asm(AREG3);

#define PARAM(n) ((uint32_t)PARAM##n)

#define SPARAM(n) ((int32_t)PARAM##n)

#if defined (USE_HOST_FLOAT_REGS)

register double FT0 asm(FREG0);

register double FT1 asm(FREG1);

register double FT2 asm(FREG2);

register float FTS0 asm(FREG0);

register float FTS1 asm(FREG1);

register float FTS2 asm(FREG2);

#else

#define FT0 (env->ft0.d)

#define FT1 (env->ft1.d)

#define FT2 (env->ft2.d)

#define FTS0 (env->ft0.f)

#define FTS1 (env->ft1.f)

#define FTS2 (env->ft2.f)

#endif

#if defined (DEBUG_OP)

#define RETURN() __asm__ __volatile__("nop");

#else

#define RETURN() __asm__ __volatile__("");

#endif

#include "cpu.h"

#include "exec-all.h"

#if !defined(CONFIG_USER_ONLY)

#define ldul_user ldl_user

#define ldul_kernel ldl_kernel

#define ACCESS_TYPE 0

#define MEMSUFFIX _kernel

#define DATA_SIZE 1

#include "softmmu_header.h"

#define DATA_SIZE 2

#include "softmmu_header.h"

#define DATA_SIZE 4

#include "softmmu_header.h"

#define DATA_SIZE 8

#include "softmmu_header.h"

#undef ACCESS_TYPE

#undef MEMSUFFIX

#define ACCESS_TYPE 1

#define MEMSUFFIX _user

#define DATA_SIZE 1

#include "softmmu_header.h"

#define DATA_SIZE 2

#include "softmmu_header.h"

#define DATA_SIZE 4

#include "softmmu_header.h"

#define DATA_SIZE 8

#include "softmmu_header.h"

#undef ACCESS_TYPE

#undef MEMSUFFIX

/* these access are slower, they must be as rare as possible */

#define ACCESS_TYPE 2

#define MEMSUFFIX _data

#define DATA_SIZE 1

#include "softmmu_header.h"

#define DATA_SIZE 2

#include "softmmu_header.h"

#define DATA_SIZE 4

#include "softmmu_header.h"

#define DATA_SIZE 8

#include "softmmu_header.h"

#undef ACCESS_TYPE

#undef MEMSUFFIX

#define ldub(p) ldub_data(p)

#define ldsb(p) ldsb_data(p)

#define lduw(p) lduw_data(p)

#define ldsw(p) ldsw_data(p)

#define ldl(p) ldl_data(p)

#define ldq(p) ldq_data(p)

#define stb(p, v) stb_data(p, v)

#define stw(p, v) stw_data(p, v)

#define stl(p, v) stl_data(p, v)

#define stq(p, v) stq_data(p, v)

#endif /* !defined(CONFIG_USER_ONLY) */

static inline void env_to_regs(void)

{

}

static inline void regs_to_env(void)

{

}

#if (HOST_LONG_BITS == 32)

void do_mult (void);

void do_multu (void);

void do_madd (void);

void do_maddu (void);

void do_msub (void);

void do_msubu (void);

#endif

__attribute__ (( regparm(2) ))

void do_mfc0(int reg, int sel);

__attribute__ (( regparm(2) ))

void do_mtc0(int reg, int sel);

void do_tlbwi (void);

void do_tlbwr (void);

void do_tlbp (void);

void do_tlbr (void);

void do_lwl_raw (void);

void do_lwr_raw (void);

void do_swl_raw (void);

void do_swr_raw (void);

#if !defined(CONFIG_USER_ONLY)

void do_lwl_user (void);

void do_lwl_kernel (void);

void do_lwr_user (void);

void do_lwr_kernel (void);

void do_swl_user (void);

void do_swl_kernel (void);

void do_swr_user (void);

void do_swr_kernel (void);

#endif

__attribute__ (( regparm(1) ))

void do_pmon (int function);

int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,

                               int is_user, int is_softmmu);

void do_interrupt (CPUState *env);

void cpu_loop_exit(void);

__attribute__ (( regparm(2) ))

void do_raise_exception_err (uint32_t exception, int error_code);

__attribute__ (( regparm(1) ))

void do_raise_exception (uint32_t exception);

void cpu_dump_state(CPUState *env, FILE *f, 

                    int (*cpu_fprintf)(FILE *f, const char *fmt, ...),

                    int flags);

void cpu_mips_irqctrl_init (void);

uint32_t cpu_mips_get_random (CPUState *env);

uint32_t cpu_mips_get_count (CPUState *env);

void cpu_mips_store_count (CPUState *env, uint32_t value);

void cpu_mips_store_compare (CPUState *env, uint32_t value);

void cpu_mips_clock_init (CPUState *env);

#endif /* !defined(__QEMU_MIPS_EXEC_H__) */

/*

 *  MIPS emulation helpers for qemu.

 * 

 *  Copyright (c) 2004-2005 Jocelyn Mayer

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#include "exec.h"

/* MIPS32 4K MMU emulation */

#if MIPS_USES_4K_TLB

static int map_address (CPUState *env, target_ulong *physical, int *prot,

                        target_ulong address, int rw, int access_type)

{

    tlb_t *tlb;

    target_ulong tag;

    uint8_t ASID;

    int i, n;

    int ret;

    ret = -2;

    tag = (address & 0xFFFFE000);

    ASID = env->CP0_EntryHi & 0x000000FF;

    for (i = 0; i < 16; i++) {

        tlb = &env->tlb[i];

        /* Check ASID, virtual page number & size */

        if ((tlb->G == 1 || tlb->ASID == ASID) &&

            tlb->VPN == tag && address < tlb->end) {

            /* TLB match */

            n = (address >> 12) & 1;

            /* Check access rights */

            if ((tlb->V[n] & 2) && (rw == 0 || (tlb->D[n] & 4))) {

                *physical = tlb->PFN[n] | (address & 0xFFF);

                *prot = PROT_READ;

                if (tlb->D[n])

                    *prot |= PROT_WRITE;

                return 0;

            } else if (!(tlb->V[n] & 2)) {

                return -3;

            } else {

                return -4;

            }

        }

    }

    return ret;

}

#endif

int get_physical_address (CPUState *env, target_ulong *physical, int *prot,

                          target_ulong address, int rw, int access_type)

{

    int user_mode;

    int ret;

    /* User mode can only access useg */

    user_mode = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM) ? 1 : 0;

#if 0

    if (logfile) {

        fprintf(logfile, "user mode %d h %08x\n",

                user_mode, env->hflags);

    }

#endif

    if (user_mode && address > 0x7FFFFFFFUL)

        return -1;

    ret = 0;

    if (address < 0x80000000UL) {

        if (user_mode || !(env->hflags & MIPS_HFLAG_ERL)) {

#if MIPS_USES_4K_TLB

            ret = map_address(env, physical, prot, address, rw);

#else

            *physical = address + 0x40000000UL;

            *prot = PAGE_READ | PAGE_WRITE;

#endif

        } else {

            *physical = address;

            *prot = PAGE_READ | PAGE_WRITE;

        }

    } else if (address < 0xA0000000UL) {

        /* kseg0 */

        /* XXX: check supervisor mode */

        *physical = address - 0x80000000UL;

        *prot = PAGE_READ | PAGE_WRITE;

    } else if (address < 0xC0000000UL) {

        /* kseg1 */

        /* XXX: check supervisor mode */

        *physical = address - 0xA0000000UL;

        *prot = PAGE_READ | PAGE_WRITE;

    } else if (address < 0xE0000000UL) {

        /* kseg2 */

#if MIPS_USES_4K_TLB

        ret = map_address(env, physical, prot, address, rw);

#else

        *physical = address;

        *prot = PAGE_READ | PAGE_WRITE;

#endif

    } else {

        /* kseg3 */

        /* XXX: check supervisor mode */

        /* XXX: debug segment is not emulated */

#if MIPS_USES_4K_TLB

        ret = map_address(env, physical, prot, address, rw);

#else

        *physical = address;

        *prot = PAGE_READ | PAGE_WRITE;

#endif

    }

#if 0

    if (logfile) {

        fprintf(logfile, "%08x %d %d => %08x %d (%d)\n", address, rw,

                access_type, *physical, *prot, ret);

    }

#endif

    return ret;

}

#if defined(CONFIG_USER_ONLY) 

target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)

{

    return addr;

}

#else

target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)

{

    target_ulong phys_addr;

    int prot;

    if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)

        return -1;

    return phys_addr;

}

#endif

#if !defined(CONFIG_USER_ONLY) 

#define MMUSUFFIX _mmu

#define GETPC() (__builtin_return_address(0))

#define SHIFT 0

#include "softmmu_template.h"

#define SHIFT 1

#include "softmmu_template.h"

#define SHIFT 2

#include "softmmu_template.h"

#define SHIFT 3

#include "softmmu_template.h"

void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)

{

    TranslationBlock *tb;

    CPUState *saved_env;

    unsigned long pc;

    int ret;

    /* XXX: hack to restore env in all cases, even if not called from

       generated code */

    saved_env = env;

    env = cpu_single_env;

    ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);

    if (ret) {

        if (retaddr) {

            /* now we have a real cpu fault */

            pc = (unsigned long)retaddr;

            tb = tb_find_pc(pc);

            if (tb) {

                /* the PC is inside the translated code. It means that we have

                   a virtual CPU fault */

                cpu_restore_state(tb, env, pc, NULL);

            }

        }

        do_raise_exception_err(env->exception_index, env->error_code);

    }

    env = saved_env;

}

void cpu_mips_init_mmu (CPUState *env)

{

}

#endif /* !defined(CONFIG_USER_ONLY) */

int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,

                               int is_user, int is_softmmu)

{

    target_ulong physical;

    int prot;

    int exception = 0, error_code = 0;

    int access_type;

    int ret = 0;

    if (logfile) {