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1
/*
2
 * internal execution defines for qemu
3
 * 
4
 *  Copyright (c) 2003 Fabrice Bellard
5
 *
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 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
20

    
21
/* allow to see translation results - the slowdown should be negligible, so we leave it */
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#define DEBUG_DISAS
23

    
24
#ifndef glue
25
#define xglue(x, y) x ## y
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#define glue(x, y) xglue(x, y)
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#define stringify(s)        tostring(s)
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#define tostring(s)        #s
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#endif
30

    
31
#if __GNUC__ < 3
32
#define __builtin_expect(x, n) (x)
33
#endif
34

    
35
#ifdef __i386__
36
#define REGPARM(n) __attribute((regparm(n)))
37
#else
38
#define REGPARM(n)
39
#endif
40

    
41
/* is_jmp field values */
42
#define DISAS_NEXT    0 /* next instruction can be analyzed */
43
#define DISAS_JUMP    1 /* only pc was modified dynamically */
44
#define DISAS_UPDATE  2 /* cpu state was modified dynamically */
45
#define DISAS_TB_JUMP 3 /* only pc was modified statically */
46

    
47
struct TranslationBlock;
48

    
49
/* XXX: make safe guess about sizes */
50
#define MAX_OP_PER_INSTR 32
51
#define OPC_BUF_SIZE 512
52
#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
53

    
54
#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
55

    
56
extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
57
extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
58
extern long gen_labels[OPC_BUF_SIZE];
59
extern int nb_gen_labels;
60
extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
61
extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
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extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
63
extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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extern target_ulong gen_opc_jump_pc[2];
65

    
66
typedef void (GenOpFunc)(void);
67
typedef void (GenOpFunc1)(long);
68
typedef void (GenOpFunc2)(long, long);
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typedef void (GenOpFunc3)(long, long, long);
70
                    
71
#if defined(TARGET_I386)
72

    
73
void optimize_flags_init(void);
74

    
75
#endif
76

    
77
extern FILE *logfile;
78
extern int loglevel;
79

    
80
int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
81
int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
82
void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
83
int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
84
                 int max_code_size, int *gen_code_size_ptr);
85
int cpu_restore_state(struct TranslationBlock *tb, 
86
                      CPUState *env, unsigned long searched_pc,
87
                      void *puc);
88
int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
89
                      int max_code_size, int *gen_code_size_ptr);
90
int cpu_restore_state_copy(struct TranslationBlock *tb, 
91
                           CPUState *env, unsigned long searched_pc,
92
                           void *puc);
93
void cpu_resume_from_signal(CPUState *env1, void *puc);
94
void cpu_exec_init(void);
95
int page_unprotect(unsigned long address, unsigned long pc, void *puc);
96
void tb_invalidate_phys_page_range(target_ulong start, target_ulong end, 
97
                                   int is_cpu_write_access);
98
void tb_invalidate_page_range(target_ulong start, target_ulong end);
99
void tlb_flush_page(CPUState *env, target_ulong addr);
100
void tlb_flush(CPUState *env, int flush_global);
101
int tlb_set_page(CPUState *env, target_ulong vaddr, 
102
                 target_phys_addr_t paddr, int prot, 
103
                 int is_user, int is_softmmu);
104

    
105
#define CODE_GEN_MAX_SIZE        65536
106
#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
107

    
108
#define CODE_GEN_HASH_BITS     15
109
#define CODE_GEN_HASH_SIZE     (1 << CODE_GEN_HASH_BITS)
110

    
111
#define CODE_GEN_PHYS_HASH_BITS     15
112
#define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
113

    
114
/* maximum total translate dcode allocated */
115

    
116
/* NOTE: the translated code area cannot be too big because on some
117
   archs the range of "fast" function calls is limited. Here is a
118
   summary of the ranges:
119

120
   i386  : signed 32 bits
121
   arm   : signed 26 bits
122
   ppc   : signed 24 bits
123
   sparc : signed 32 bits
124
   alpha : signed 23 bits
125
*/
126

    
127
#if defined(__alpha__)
128
#define CODE_GEN_BUFFER_SIZE     (2 * 1024 * 1024)
129
#elif defined(__ia64)
130
#define CODE_GEN_BUFFER_SIZE     (4 * 1024 * 1024)        /* range of addl */
131
#elif defined(__powerpc__)
132
#define CODE_GEN_BUFFER_SIZE     (6 * 1024 * 1024)
133
#else
134
#define CODE_GEN_BUFFER_SIZE     (16 * 1024 * 1024)
135
#endif
136

    
137
//#define CODE_GEN_BUFFER_SIZE     (128 * 1024)
138

    
139
/* estimated block size for TB allocation */
140
/* XXX: use a per code average code fragment size and modulate it
141
   according to the host CPU */
142
#if defined(CONFIG_SOFTMMU)
143
#define CODE_GEN_AVG_BLOCK_SIZE 128
144
#else
145
#define CODE_GEN_AVG_BLOCK_SIZE 64
146
#endif
147

    
148
#define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
149

    
150
#if defined(__powerpc__) 
151
#define USE_DIRECT_JUMP
152
#endif
153
#if defined(__i386__) && !defined(_WIN32)
154
#define USE_DIRECT_JUMP
155
#endif
156

    
157
typedef struct TranslationBlock {
158
    target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
159
    target_ulong cs_base; /* CS base for this block */
160
    unsigned int flags; /* flags defining in which context the code was generated */
161
    uint16_t size;      /* size of target code for this block (1 <=
162
                           size <= TARGET_PAGE_SIZE) */
163
    uint16_t cflags;    /* compile flags */
164
#define CF_CODE_COPY   0x0001 /* block was generated in code copy mode */
165
#define CF_TB_FP_USED  0x0002 /* fp ops are used in the TB */
166
#define CF_FP_USED     0x0004 /* fp ops are used in the TB or in a chained TB */
167
#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
168

    
169
    uint8_t *tc_ptr;    /* pointer to the translated code */
170
    struct TranslationBlock *hash_next; /* next matching tb for virtual address */
171
    /* next matching tb for physical address. */
172
    struct TranslationBlock *phys_hash_next; 
173
    /* first and second physical page containing code. The lower bit
174
       of the pointer tells the index in page_next[] */
175
    struct TranslationBlock *page_next[2]; 
176
    target_ulong page_addr[2]; 
177

    
178
    /* the following data are used to directly call another TB from
179
       the code of this one. */
180
    uint16_t tb_next_offset[2]; /* offset of original jump target */
181
#ifdef USE_DIRECT_JUMP
182
    uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
183
#else
184
    uint32_t tb_next[2]; /* address of jump generated code */
185
#endif
186
    /* list of TBs jumping to this one. This is a circular list using
187
       the two least significant bits of the pointers to tell what is
188
       the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
189
       jmp_first */
190
    struct TranslationBlock *jmp_next[2]; 
191
    struct TranslationBlock *jmp_first;
192
} TranslationBlock;
193

    
194
static inline unsigned int tb_hash_func(target_ulong pc)
195
{
196
    return pc & (CODE_GEN_HASH_SIZE - 1);
197
}
198

    
199
static inline unsigned int tb_phys_hash_func(unsigned long pc)
200
{
201
    return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
202
}
203

    
204
TranslationBlock *tb_alloc(target_ulong pc);
205
void tb_flush(CPUState *env);
206
void tb_link(TranslationBlock *tb);
207
void tb_link_phys(TranslationBlock *tb, 
208
                  target_ulong phys_pc, target_ulong phys_page2);
209

    
210
extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
211
extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
212

    
213
extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
214
extern uint8_t *code_gen_ptr;
215

    
216
/* find a translation block in the translation cache. If not found,
217
   return NULL and the pointer to the last element of the list in pptb */
218
static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
219
                                        target_ulong pc, 
220
                                        target_ulong cs_base,
221
                                        unsigned int flags)
222
{
223
    TranslationBlock **ptb, *tb;
224
    unsigned int h;
225
 
226
    h = tb_hash_func(pc);
227
    ptb = &tb_hash[h];
228
    for(;;) {
229
        tb = *ptb;
230
        if (!tb)
231
            break;
232
        if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
233
            return tb;
234
        ptb = &tb->hash_next;
235
    }
236
    *pptb = ptb;
237
    return NULL;
238
}
239

    
240

    
241
#if defined(USE_DIRECT_JUMP)
242

    
243
#if defined(__powerpc__)
244
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
245
{
246
    uint32_t val, *ptr;
247

    
248
    /* patch the branch destination */
249
    ptr = (uint32_t *)jmp_addr;
250
    val = *ptr;
251
    val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
252
    *ptr = val;
253
    /* flush icache */
254
    asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
255
    asm volatile ("sync" : : : "memory");
256
    asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
257
    asm volatile ("sync" : : : "memory");
258
    asm volatile ("isync" : : : "memory");
259
}
260
#elif defined(__i386__)
261
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
262
{
263
    /* patch the branch destination */
264
    *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
265
    /* no need to flush icache explicitely */
266
}
267
#endif
268

    
269
static inline void tb_set_jmp_target(TranslationBlock *tb, 
270
                                     int n, unsigned long addr)
271
{
272
    unsigned long offset;
273

    
274
    offset = tb->tb_jmp_offset[n];
275
    tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
276
    offset = tb->tb_jmp_offset[n + 2];
277
    if (offset != 0xffff)
278
        tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
279
}
280

    
281
#else
282

    
283
/* set the jump target */
284
static inline void tb_set_jmp_target(TranslationBlock *tb, 
285
                                     int n, unsigned long addr)
286
{
287
    tb->tb_next[n] = addr;
288
}
289

    
290
#endif
291

    
292
static inline void tb_add_jump(TranslationBlock *tb, int n, 
293
                               TranslationBlock *tb_next)
294
{
295
    /* NOTE: this test is only needed for thread safety */
296
    if (!tb->jmp_next[n]) {
297
        /* patch the native jump address */
298
        tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
299
        
300
        /* add in TB jmp circular list */
301
        tb->jmp_next[n] = tb_next->jmp_first;
302
        tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
303
    }
304
}
305

    
306
TranslationBlock *tb_find_pc(unsigned long pc_ptr);
307

    
308
#ifndef offsetof
309
#define offsetof(type, field) ((size_t) &((type *)0)->field)
310
#endif
311

    
312
#if defined(_WIN32)
313
#define ASM_DATA_SECTION ".section \".data\"\n"
314
#define ASM_PREVIOUS_SECTION ".section .text\n"
315
#elif defined(__APPLE__)
316
#define ASM_DATA_SECTION ".data\n"
317
#define ASM_PREVIOUS_SECTION ".text\n"
318
#else
319
#define ASM_DATA_SECTION ".section \".data\"\n"
320
#define ASM_PREVIOUS_SECTION ".previous\n"
321
#endif
322

    
323
#if defined(__powerpc__)
324

    
325
/* we patch the jump instruction directly */
326
#define GOTO_TB(opname, tbparam, n)\
327
do {\
328
    asm volatile (ASM_DATA_SECTION\
329
                  ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\
330
                  ".long 1f\n"\
331
                  ASM_PREVIOUS_SECTION \
332
                  "b " ASM_NAME(__op_jmp) #n "\n"\
333
                  "1:\n");\
334
} while (0)
335

    
336
#elif defined(__i386__) && defined(USE_DIRECT_JUMP)
337

    
338
/* we patch the jump instruction directly */
339
#define GOTO_TB(opname, tbparam, n)\
340
do {\
341
    asm volatile (".section .data\n"\
342
                  ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\
343
                  ".long 1f\n"\
344
                  ASM_PREVIOUS_SECTION \
345
                  "jmp " ASM_NAME(__op_jmp) #n "\n"\
346
                  "1:\n");\
347
} while (0)
348

    
349
#else
350

    
351
/* jump to next block operations (more portable code, does not need
352
   cache flushing, but slower because of indirect jump) */
353
#define GOTO_TB(opname, tbparam, n)\
354
do {\
355
    static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
356
    static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
357
    goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
358
label ## n: ;\
359
dummy_label ## n: ;\
360
} while (0)
361

    
362
#endif
363

    
364
/* XXX: will be suppressed */
365
#define JUMP_TB(opname, tbparam, n, eip)\
366
do {\
367
    GOTO_TB(opname, tbparam, n);\
368
    T0 = (long)(tbparam) + (n);\
369
    EIP = (int32_t)eip;\
370
    EXIT_TB();\
371
} while (0)
372

    
373
extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
374
extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
375
extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
376

    
377
#ifdef __powerpc__
378
static inline int testandset (int *p)
379
{
380
    int ret;
381
    __asm__ __volatile__ (
382
                          "0:    lwarx %0,0,%1\n"
383
                          "      xor. %0,%3,%0\n"
384
                          "      bne 1f\n"
385
                          "      stwcx. %2,0,%1\n"
386
                          "      bne- 0b\n"
387
                          "1:    "
388
                          : "=&r" (ret)
389
                          : "r" (p), "r" (1), "r" (0)
390
                          : "cr0", "memory");
391
    return ret;
392
}
393
#endif
394

    
395
#ifdef __i386__
396
static inline int testandset (int *p)
397
{
398
    long int readval = 0;
399
    
400
    __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
401
                          : "+m" (*p), "+a" (readval)
402
                          : "r" (1)
403
                          : "cc");
404
    return readval;
405
}
406
#endif
407

    
408
#ifdef __x86_64__
409
static inline int testandset (int *p)
410
{
411
    long int readval = 0;
412
    
413
    __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
414
                          : "+m" (*p), "+a" (readval)
415
                          : "r" (1)
416
                          : "cc");
417
    return readval;
418
}
419
#endif
420

    
421
#ifdef __s390__
422
static inline int testandset (int *p)
423
{
424
    int ret;
425

    
426
    __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
427
                          "   jl    0b"
428
                          : "=&d" (ret)
429
                          : "r" (1), "a" (p), "0" (*p) 
430
                          : "cc", "memory" );
431
    return ret;
432
}
433
#endif
434

    
435
#ifdef __alpha__
436
static inline int testandset (int *p)
437
{
438
    int ret;
439
    unsigned long one;
440

    
441
    __asm__ __volatile__ ("0:        mov 1,%2\n"
442
                          "        ldl_l %0,%1\n"
443
                          "        stl_c %2,%1\n"
444
                          "        beq %2,1f\n"
445
                          ".subsection 2\n"
446
                          "1:        br 0b\n"
447
                          ".previous"
448
                          : "=r" (ret), "=m" (*p), "=r" (one)
449
                          : "m" (*p));
450
    return ret;
451
}
452
#endif
453

    
454
#ifdef __sparc__
455
static inline int testandset (int *p)
456
{
457
        int ret;
458

    
459
        __asm__ __volatile__("ldstub        [%1], %0"
460
                             : "=r" (ret)
461
                             : "r" (p)
462
                             : "memory");
463

    
464
        return (ret ? 1 : 0);
465
}
466
#endif
467

    
468
#ifdef __arm__
469
static inline int testandset (int *spinlock)
470
{
471
    register unsigned int ret;
472
    __asm__ __volatile__("swp %0, %1, [%2]"
473
                         : "=r"(ret)
474
                         : "0"(1), "r"(spinlock));
475
    
476
    return ret;
477
}
478
#endif
479

    
480
#ifdef __mc68000
481
static inline int testandset (int *p)
482
{
483
    char ret;
484
    __asm__ __volatile__("tas %1; sne %0"
485
                         : "=r" (ret)
486
                         : "m" (p)
487
                         : "cc","memory");
488
    return ret;
489
}
490
#endif
491

    
492
#ifdef __ia64
493
#include <ia64intrin.h>
494

    
495
static inline int testandset (int *p)
496
{
497
    return __sync_lock_test_and_set (p, 1);
498
}
499
#endif
500

    
501
typedef int spinlock_t;
502

    
503
#define SPIN_LOCK_UNLOCKED 0
504

    
505
#if defined(CONFIG_USER_ONLY)
506
static inline void spin_lock(spinlock_t *lock)
507
{
508
    while (testandset(lock));
509
}
510

    
511
static inline void spin_unlock(spinlock_t *lock)
512
{
513
    *lock = 0;
514
}
515

    
516
static inline int spin_trylock(spinlock_t *lock)
517
{
518
    return !testandset(lock);
519
}
520
#else
521
static inline void spin_lock(spinlock_t *lock)
522
{
523
}
524

    
525
static inline void spin_unlock(spinlock_t *lock)
526
{
527
}
528

    
529
static inline int spin_trylock(spinlock_t *lock)
530
{
531
    return 1;
532
}
533
#endif
534

    
535
extern spinlock_t tb_lock;
536

    
537
extern int tb_invalidated_flag;
538

    
539
#if !defined(CONFIG_USER_ONLY)
540

    
541
void tlb_fill(target_ulong addr, int is_write, int is_user, 
542
              void *retaddr);
543

    
544
#define ACCESS_TYPE 3
545
#define MEMSUFFIX _code
546
#define env cpu_single_env
547

    
548
#define DATA_SIZE 1
549
#include "softmmu_header.h"
550

    
551
#define DATA_SIZE 2
552
#include "softmmu_header.h"
553

    
554
#define DATA_SIZE 4
555
#include "softmmu_header.h"
556

    
557
#define DATA_SIZE 8
558
#include "softmmu_header.h"
559

    
560
#undef ACCESS_TYPE
561
#undef MEMSUFFIX
562
#undef env
563

    
564
#endif
565

    
566
#if defined(CONFIG_USER_ONLY)
567
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
568
{
569
    return addr;
570
}
571
#else
572
/* NOTE: this function can trigger an exception */
573
/* NOTE2: the returned address is not exactly the physical address: it
574
   is the offset relative to phys_ram_base */
575
/* XXX: i386 target specific */
576
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
577
{
578
    int is_user, index, pd;
579

    
580
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
581
#if defined(TARGET_I386)
582
    is_user = ((env->hflags & HF_CPL_MASK) == 3);
583
#elif defined (TARGET_PPC)
584
    is_user = msr_pr;
585
#elif defined (TARGET_MIPS)
586
    is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
587
#elif defined (TARGET_SPARC)
588
    is_user = (env->psrs == 0);
589
#else
590
#error "Unimplemented !"
591
#endif
592
    if (__builtin_expect(env->tlb_read[is_user][index].address != 
593
                         (addr & TARGET_PAGE_MASK), 0)) {
594
        ldub_code(addr);
595
    }
596
    pd = env->tlb_read[is_user][index].address & ~TARGET_PAGE_MASK;
597
    if (pd > IO_MEM_ROM) {
598
        cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
599
    }
600
    return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
601
}
602
#endif
603

    
604

    
605
#ifdef USE_KQEMU
606
int kqemu_init(CPUState *env);
607
int kqemu_cpu_exec(CPUState *env);
608
void kqemu_flush_page(CPUState *env, target_ulong addr);
609
void kqemu_flush(CPUState *env, int global);
610

    
611
static inline int kqemu_is_ok(CPUState *env)
612
{
613
    return(env->kqemu_enabled &&
614
           (env->hflags & HF_CPL_MASK) == 3 &&
615
           (env->eflags & IOPL_MASK) != IOPL_MASK &&
616
           (env->cr[0] & CR0_PE_MASK) && 
617
           (env->eflags & IF_MASK) &&
618
           !(env->eflags & VM_MASK));
619
}
620

    
621
#endif