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/*
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* MIPS emulation helpers for qemu.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <math.h> |
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#include "exec.h" |
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#define MIPS_DEBUG_DISAS
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|
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/*****************************************************************************/
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/* Exceptions processing helpers */
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void cpu_loop_exit(void) |
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{ |
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longjmp(env->jmp_env, 1);
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} |
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__attribute__ (( regparm(2) ))
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void do_raise_exception_err (uint32_t exception, int error_code) |
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{ |
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#if 1 |
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if (logfile && exception < 0x100) |
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fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
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#endif
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env->exception_index = exception; |
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env->error_code = error_code; |
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T0 = 0;
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cpu_loop_exit(); |
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} |
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__attribute__ (( regparm(1) ))
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void do_raise_exception (uint32_t exception)
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{ |
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do_raise_exception_err(exception, 0);
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} |
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#define MEMSUFFIX _raw
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#include "op_helper_mem.c" |
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#undef MEMSUFFIX
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#if !defined(CONFIG_USER_ONLY)
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#define MEMSUFFIX _user
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#include "op_helper_mem.c" |
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#undef MEMSUFFIX
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#define MEMSUFFIX _kernel
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#include "op_helper_mem.c" |
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#undef MEMSUFFIX
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#endif
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/* 64 bits arithmetic for 32 bits hosts */
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#if (HOST_LONG_BITS == 32) |
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static inline uint64_t get_HILO (void) |
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{ |
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return ((uint64_t)env->HI << 32) | (uint64_t)env->LO; |
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} |
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static inline void set_HILO (uint64_t HILO) |
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{ |
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env->LO = HILO & 0xFFFFFFFF;
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env->HI = HILO >> 32;
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} |
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void do_mult (void) |
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{ |
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set_HILO((int64_t)T0 * (int64_t)T1); |
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} |
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void do_multu (void) |
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{ |
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set_HILO((uint64_t)T0 * (uint64_t)T1); |
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} |
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|
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void do_madd (void) |
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{ |
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int64_t tmp; |
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tmp = ((int64_t)T0 * (int64_t)T1); |
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set_HILO((int64_t)get_HILO() + tmp); |
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} |
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void do_maddu (void) |
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{ |
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uint64_t tmp; |
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tmp = ((uint64_t)T0 * (uint64_t)T1); |
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set_HILO(get_HILO() + tmp); |
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} |
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|
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void do_msub (void) |
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{ |
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int64_t tmp; |
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tmp = ((int64_t)T0 * (int64_t)T1); |
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set_HILO((int64_t)get_HILO() - tmp); |
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} |
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void do_msubu (void) |
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{ |
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uint64_t tmp; |
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tmp = ((uint64_t)T0 * (uint64_t)T1); |
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set_HILO(get_HILO() - tmp); |
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} |
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#endif
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/* CP0 helpers */
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__attribute__ (( regparm(2) ))
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void do_mfc0 (int reg, int sel) |
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{ |
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const unsigned char *rn; |
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if (sel != 0 && reg != 16 && reg != 28) { |
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rn = "invalid";
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goto print;
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} |
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switch (reg) {
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case 0: |
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T0 = env->CP0_index; |
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rn = "Index";
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break;
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case 1: |
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T0 = cpu_mips_get_random(env); |
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rn = "Random";
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break;
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case 2: |
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T0 = env->CP0_EntryLo0; |
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rn = "EntryLo0";
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break;
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case 3: |
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T0 = env->CP0_EntryLo1; |
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rn = "EntryLo1";
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break;
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case 4: |
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T0 = env->CP0_Context; |
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rn = "Context";
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break;
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case 5: |
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T0 = env->CP0_PageMask; |
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rn = "PageMask";
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break;
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case 6: |
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T0 = env->CP0_Wired; |
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rn = "Wired";
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break;
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case 8: |
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T0 = env->CP0_BadVAddr; |
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rn = "BadVaddr";
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break;
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case 9: |
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T0 = cpu_mips_get_count(env); |
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rn = "Count";
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break;
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case 10: |
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T0 = env->CP0_EntryHi; |
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rn = "EntryHi";
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break;
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case 11: |
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T0 = env->CP0_Compare; |
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rn = "Compare";
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break;
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case 12: |
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T0 = env->CP0_Status; |
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if (env->hflags & MIPS_HFLAG_UM)
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T0 |= CP0St_UM; |
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if (env->hflags & MIPS_HFLAG_ERL)
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T0 |= CP0St_ERL; |
180 |
if (env->hflags & MIPS_HFLAG_EXL)
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T0 |= CP0St_EXL; |
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rn = "Status";
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break;
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case 13: |
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T0 = env->CP0_Cause; |
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rn = "Cause";
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break;
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case 14: |
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T0 = env->CP0_EPC; |
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rn = "EPC";
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break;
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case 15: |
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T0 = env->CP0_PRid; |
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rn = "PRid";
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break;
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case 16: |
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switch (sel) {
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case 0: |
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T0 = env->CP0_Config0; |
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rn = "Config";
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break;
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case 1: |
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T0 = env->CP0_Config1; |
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rn = "Config1";
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break;
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default:
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rn = "Unknown config register";
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break;
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} |
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break;
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case 17: |
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T0 = env->CP0_LLAddr >> 4;
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rn = "LLAddr";
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break;
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case 18: |
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T0 = env->CP0_WatchLo; |
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rn = "WatchLo";
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break;
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case 19: |
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T0 = env->CP0_WatchHi; |
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rn = "WatchHi";
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break;
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case 23: |
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T0 = env->CP0_Debug; |
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if (env->hflags & MIPS_HFLAG_DM)
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T0 |= 1 << CP0DB_DM;
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rn = "Debug";
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break;
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case 24: |
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T0 = env->CP0_DEPC; |
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rn = "DEPC";
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break;
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case 28: |
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switch (sel) {
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case 0: |
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T0 = env->CP0_TagLo; |
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rn = "TagLo";
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break;
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case 1: |
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T0 = env->CP0_DataLo; |
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rn = "DataLo";
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break;
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default:
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rn = "unknown sel";
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break;
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} |
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break;
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case 30: |
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T0 = env->CP0_ErrorEPC; |
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rn = "ErrorEPC";
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break;
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case 31: |
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T0 = env->CP0_DESAVE; |
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rn = "DESAVE";
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break;
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default:
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rn = "unknown";
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break;
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} |
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print:
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#if defined MIPS_DEBUG_DISAS
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if (loglevel & CPU_LOG_TB_IN_ASM) {
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fprintf(logfile, "%08x mfc0 %s => %08x (%d %d)\n",
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env->PC, rn, T0, reg, sel); |
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} |
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#endif
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return;
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} |
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__attribute__ (( regparm(2) ))
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void do_mtc0 (int reg, int sel) |
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{ |
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const unsigned char *rn; |
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uint32_t val, old, mask; |
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int i, raise;
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if (sel != 0 && reg != 16 && reg != 28) { |
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val = -1;
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old = -1;
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rn = "invalid";
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goto print;
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} |
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switch (reg) {
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case 0: |
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val = (env->CP0_index & 0x80000000) | (T0 & 0x0000000F); |
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old = env->CP0_index; |
287 |
env->CP0_index = val; |
288 |
rn = "Index";
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break;
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case 2: |
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val = T0 & 0x03FFFFFFF;
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old = env->CP0_EntryLo0; |
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env->CP0_EntryLo0 = val; |
294 |
rn = "EntryLo0";
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break;
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case 3: |
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val = T0 & 0x03FFFFFFF;
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old = env->CP0_EntryLo1; |
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env->CP0_EntryLo1 = val; |
300 |
rn = "EntryLo1";
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break;
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case 4: |
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val = (env->CP0_Context & 0xFF000000) | (T0 & 0x00FFFFF0); |
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old = env->CP0_Context; |
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env->CP0_Context = val; |
306 |
rn = "Context";
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break;
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case 5: |
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val = T0 & 0x01FFE000;
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old = env->CP0_PageMask; |
311 |
env->CP0_PageMask = val; |
312 |
rn = "PageMask";
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break;
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case 6: |
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val = T0 & 0x0000000F;
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old = env->CP0_Wired; |
317 |
env->CP0_Wired = val; |
318 |
rn = "Wired";
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break;
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case 9: |
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val = T0; |
322 |
old = cpu_mips_get_count(env); |
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cpu_mips_store_count(env, val); |
324 |
rn = "Count";
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break;
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case 10: |
327 |
val = T0 & 0xFFFFF0FF;
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old = env->CP0_EntryHi; |
329 |
env->CP0_EntryHi = val; |
330 |
rn = "EntryHi";
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break;
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case 11: |
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val = T0; |
334 |
old = env->CP0_Compare; |
335 |
cpu_mips_store_compare(env, val); |
336 |
rn = "Compare";
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break;
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338 |
case 12: |
339 |
val = T0 & 0xFA78FF01;
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if (T0 & (1 << CP0St_UM)) |
341 |
env->hflags |= MIPS_HFLAG_UM; |
342 |
else
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env->hflags &= ~MIPS_HFLAG_UM; |
344 |
if (T0 & (1 << CP0St_ERL)) |
345 |
env->hflags |= MIPS_HFLAG_ERL; |
346 |
else
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347 |
env->hflags &= ~MIPS_HFLAG_ERL; |
348 |
if (T0 & (1 << CP0St_EXL)) |
349 |
env->hflags |= MIPS_HFLAG_EXL; |
350 |
else
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351 |
env->hflags &= ~MIPS_HFLAG_EXL; |
352 |
old = env->CP0_Status; |
353 |
env->CP0_Status = val; |
354 |
/* If we unmasked an asserted IRQ, raise it */
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355 |
mask = 0x0000FC00;
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356 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
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357 |
fprintf(logfile, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n",
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358 |
old, val, env->CP0_Cause, old & mask, val & mask, |
359 |
env->CP0_Cause & mask); |
360 |
} |
361 |
#if 1 |
362 |
if ((val & (1 << CP0St_IE)) && !(old & (1 << CP0St_IE)) && |
363 |
!(env->hflags & MIPS_HFLAG_EXL) && |
364 |
!(env->hflags & MIPS_HFLAG_ERL) && |
365 |
!(env->hflags & MIPS_HFLAG_DM) && |
366 |
(env->CP0_Cause & mask)) { |
367 |
if (logfile)
|
368 |
fprintf(logfile, "Raise pending IRQs\n");
|
369 |
env->interrupt_request |= CPU_INTERRUPT_HARD; |
370 |
do_raise_exception(EXCP_EXT_INTERRUPT); |
371 |
} else if (!(val & 0x00000001) && (old & 0x00000001)) { |
372 |
env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
373 |
} |
374 |
#endif
|
375 |
rn = "Status";
|
376 |
break;
|
377 |
case 13: |
378 |
val = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x000C00300); |
379 |
old = env->CP0_Cause; |
380 |
env->CP0_Cause = val; |
381 |
#if 0
|
382 |
/* Check if we ever asserted a software IRQ */
|
383 |
for (i = 0; i < 2; i++) {
|
384 |
mask = 0x100 << i;
|
385 |
if ((val & mask) & !(old & mask))
|
386 |
mips_set_irq(i);
|
387 |
}
|
388 |
#endif
|
389 |
rn = "Cause";
|
390 |
break;
|
391 |
case 14: |
392 |
val = T0; |
393 |
old = env->CP0_EPC; |
394 |
env->CP0_EPC = val; |
395 |
rn = "EPC";
|
396 |
break;
|
397 |
case 16: |
398 |
switch (sel) {
|
399 |
case 0: |
400 |
#if defined(MIPS_USES_R4K_TLB)
|
401 |
val = (env->CP0_Config0 & 0x8017FF80) | (T0 & 0x7E000001); |
402 |
#else
|
403 |
val = (env->CP0_Config0 & 0xFE17FF80) | (T0 & 0x00000001); |
404 |
#endif
|
405 |
old = env->CP0_Config0; |
406 |
env->CP0_Config0 = val; |
407 |
rn = "Config0";
|
408 |
break;
|
409 |
default:
|
410 |
val = -1;
|
411 |
old = -1;
|
412 |
rn = "bad config selector";
|
413 |
break;
|
414 |
} |
415 |
break;
|
416 |
case 18: |
417 |
val = T0; |
418 |
old = env->CP0_WatchLo; |
419 |
env->CP0_WatchLo = val; |
420 |
rn = "WatchLo";
|
421 |
break;
|
422 |
case 19: |
423 |
val = T0 & 0x40FF0FF8;
|
424 |
old = env->CP0_WatchHi; |
425 |
env->CP0_WatchHi = val; |
426 |
rn = "WatchHi";
|
427 |
break;
|
428 |
case 23: |
429 |
val = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120); |
430 |
if (T0 & (1 << CP0DB_DM)) |
431 |
env->hflags |= MIPS_HFLAG_DM; |
432 |
else
|
433 |
env->hflags &= ~MIPS_HFLAG_DM; |
434 |
old = env->CP0_Debug; |
435 |
env->CP0_Debug = val; |
436 |
rn = "Debug";
|
437 |
break;
|
438 |
case 24: |
439 |
val = T0; |
440 |
old = env->CP0_DEPC; |
441 |
env->CP0_DEPC = val; |
442 |
rn = "DEPC";
|
443 |
break;
|
444 |
case 28: |
445 |
switch (sel) {
|
446 |
case 0: |
447 |
val = T0 & 0xFFFFFCF6;
|
448 |
old = env->CP0_TagLo; |
449 |
env->CP0_TagLo = val; |
450 |
rn = "TagLo";
|
451 |
break;
|
452 |
default:
|
453 |
val = -1;
|
454 |
old = -1;
|
455 |
rn = "invalid sel";
|
456 |
break;
|
457 |
} |
458 |
break;
|
459 |
case 30: |
460 |
val = T0; |
461 |
old = env->CP0_ErrorEPC; |
462 |
env->CP0_ErrorEPC = val; |
463 |
rn = "EPC";
|
464 |
break;
|
465 |
case 31: |
466 |
val = T0; |
467 |
old = env->CP0_DESAVE; |
468 |
env->CP0_DESAVE = val; |
469 |
rn = "DESAVE";
|
470 |
break;
|
471 |
default:
|
472 |
val = -1;
|
473 |
old = -1;
|
474 |
rn = "unknown";
|
475 |
break;
|
476 |
} |
477 |
print:
|
478 |
#if defined MIPS_DEBUG_DISAS
|
479 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
480 |
fprintf(logfile, "%08x mtc0 %s %08x => %08x (%d %d %08x)\n",
|
481 |
env->PC, rn, T0, val, reg, sel, old); |
482 |
} |
483 |
#endif
|
484 |
return;
|
485 |
} |
486 |
|
487 |
/* TLB management */
|
488 |
#if defined(MIPS_USES_R4K_TLB)
|
489 |
__attribute__ (( regparm(1) ))
|
490 |
static void invalidate_tb (int idx) |
491 |
{ |
492 |
tlb_t *tlb; |
493 |
target_ulong addr, end; |
494 |
|
495 |
tlb = &env->tlb[idx]; |
496 |
if (tlb->V[0]) { |
497 |
addr = tlb->PFN[0];
|
498 |
end = addr + (tlb->end - tlb->VPN); |
499 |
tb_invalidate_page_range(addr, end); |
500 |
} |
501 |
if (tlb->V[1]) { |
502 |
addr = tlb->PFN[1];
|
503 |
end = addr + (tlb->end - tlb->VPN); |
504 |
tb_invalidate_page_range(addr, end); |
505 |
} |
506 |
} |
507 |
|
508 |
__attribute__ (( regparm(1) ))
|
509 |
static void fill_tb (int idx) |
510 |
{ |
511 |
tlb_t *tlb; |
512 |
int size;
|
513 |
|
514 |
/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
|
515 |
tlb = &env->tlb[idx]; |
516 |
tlb->VPN = env->CP0_EntryHi & 0xFFFFE000;
|
517 |
tlb->ASID = env->CP0_EntryHi & 0x000000FF;
|
518 |
size = env->CP0_PageMask >> 13;
|
519 |
size = 4 * (size + 1); |
520 |
tlb->end = tlb->VPN + (1 << (8 + size)); |
521 |
tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
|
522 |
tlb->V[0] = env->CP0_EntryLo0 & 2; |
523 |
tlb->D[0] = env->CP0_EntryLo0 & 4; |
524 |
tlb->C[0] = (env->CP0_EntryLo0 >> 3) & 0x7; |
525 |
tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
526 |
tlb->V[1] = env->CP0_EntryLo1 & 2; |
527 |
tlb->D[1] = env->CP0_EntryLo1 & 4; |
528 |
tlb->C[1] = (env->CP0_EntryLo1 >> 3) & 0x7; |
529 |
tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
530 |
} |
531 |
|
532 |
void do_tlbwi (void) |
533 |
{ |
534 |
invalidate_tb(env->CP0_index & 0xF);
|
535 |
fill_tb(env->CP0_index & 0xF);
|
536 |
} |
537 |
|
538 |
void do_tlbwr (void) |
539 |
{ |
540 |
int r = cpu_mips_get_random(env);
|
541 |
|
542 |
invalidate_tb(r); |
543 |
fill_tb(r); |
544 |
} |
545 |
|
546 |
void do_tlbp (void) |
547 |
{ |
548 |
tlb_t *tlb; |
549 |
target_ulong tag; |
550 |
uint8_t ASID; |
551 |
int i;
|
552 |
|
553 |
tag = (env->CP0_EntryHi & 0xFFFFE000);
|
554 |
ASID = env->CP0_EntryHi & 0x000000FF;
|
555 |
for (i = 0; i < 16; i++) { |
556 |
tlb = &env->tlb[i]; |
557 |
/* Check ASID, virtual page number & size */
|
558 |
if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { |
559 |
/* TLB match */
|
560 |
env->CP0_index = i; |
561 |
break;
|
562 |
} |
563 |
} |
564 |
if (i == 16) { |
565 |
env->CP0_index |= 0x80000000;
|
566 |
} |
567 |
} |
568 |
|
569 |
void do_tlbr (void) |
570 |
{ |
571 |
tlb_t *tlb; |
572 |
int size;
|
573 |
|
574 |
tlb = &env->tlb[env->CP0_index & 0xF];
|
575 |
env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
576 |
size = (tlb->end - tlb->VPN) >> 12;
|
577 |
env->CP0_PageMask = (size - 1) << 13; |
578 |
env->CP0_EntryLo0 = tlb->V[0] | tlb->D[0] | (tlb->C[0] << 3) | |
579 |
(tlb->PFN[0] >> 6); |
580 |
env->CP0_EntryLo1 = tlb->V[1] | tlb->D[1] | (tlb->C[1] << 3) | |
581 |
(tlb->PFN[1] >> 6); |
582 |
} |
583 |
#endif
|
584 |
|
585 |
__attribute__ (( regparm(1) ))
|
586 |
void op_dump_ldst (const unsigned char *func) |
587 |
{ |
588 |
if (loglevel)
|
589 |
fprintf(logfile, "%s => %08x %08x\n", __func__, T0, T1);
|
590 |
} |
591 |
|
592 |
void dump_sc (void) |
593 |
{ |
594 |
if (loglevel) {
|
595 |
fprintf(logfile, "%s %08x at %08x (%08x)\n", __func__,
|
596 |
T1, T0, env->CP0_LLAddr); |
597 |
} |
598 |
} |
599 |
|
600 |
void debug_eret (void) |
601 |
{ |
602 |
if (loglevel) {
|
603 |
fprintf(logfile, "ERET: pc %08x EPC %08x ErrorEPC %08x (%d)\n",
|
604 |
env->PC, env->CP0_EPC, env->CP0_ErrorEPC, |
605 |
env->hflags & MIPS_HFLAG_ERL ? 1 : 0); |
606 |
} |
607 |
} |
608 |
|
609 |
__attribute__ (( regparm(1) ))
|
610 |
void do_pmon (int function) |
611 |
{ |
612 |
function /= 2;
|
613 |
switch (function) {
|
614 |
case 2: /* TODO: char inbyte(int waitflag); */ |
615 |
if (env->gpr[4] == 0) |
616 |
env->gpr[2] = -1; |
617 |
/* Fall through */
|
618 |
case 11: /* TODO: char inbyte (void); */ |
619 |
env->gpr[2] = -1; |
620 |
break;
|
621 |
case 3: |
622 |
case 12: |
623 |
printf("%c", env->gpr[4] & 0xFF); |
624 |
break;
|
625 |
case 17: |
626 |
break;
|
627 |
case 158: |
628 |
{ |
629 |
unsigned char *fmt = (void *)env->gpr[4]; |
630 |
printf("%s", fmt);
|
631 |
} |
632 |
break;
|
633 |
} |
634 |
} |