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/*
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 * QEMU PC System Emulator
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 *
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 * Copyright (c) 2003-2004 Fabrice Bellard
5
 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
23
 */
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#include "hw.h"
25
#include "pc.h"
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#include "fdc.h"
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#include "pci.h"
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#include "block.h"
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#include "sysemu.h"
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#include "audio/audio.h"
31
#include "net.h"
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#include "smbus.h"
33
#include "boards.h"
34
#include "monitor.h"
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#include "fw_cfg.h"
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#include "hpet_emul.h"
37
#include "watchdog.h"
38
#include "smbios.h"
39

    
40
/* output Bochs bios info messages */
41
//#define DEBUG_BIOS
42

    
43
/* Show multiboot debug output */
44
//#define DEBUG_MULTIBOOT
45

    
46
#define BIOS_FILENAME "bios.bin"
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#define VGABIOS_FILENAME "vgabios.bin"
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#define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
49

    
50
#define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
51

    
52
/* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
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#define ACPI_DATA_SIZE       0x10000
54
#define BIOS_CFG_IOPORT 0x510
55
#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
56
#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
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#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
58

    
59
#define MAX_IDE_BUS 2
60

    
61
static fdctrl_t *floppy_controller;
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static RTCState *rtc_state;
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static PITState *pit;
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static IOAPICState *ioapic;
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static PCIDevice *i440fx_state;
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67
typedef struct rom_reset_data {
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    uint8_t *data;
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    target_phys_addr_t addr;
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    unsigned size;
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} RomResetData;
72

    
73
static void option_rom_reset(void *_rrd)
74
{
75
    RomResetData *rrd = _rrd;
76

    
77
    cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size);
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}
79

    
80
static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size)
81
{
82
    RomResetData *rrd = qemu_malloc(sizeof *rrd);
83

    
84
    rrd->data = qemu_malloc(size);
85
    cpu_physical_memory_read(addr, rrd->data, size);
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    rrd->addr = addr;
87
    rrd->size = size;
88
    qemu_register_reset(option_rom_reset, rrd);
89
}
90

    
91
static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
92
{
93
}
94

    
95
/* MSDOS compatibility mode FPU exception support */
96
static qemu_irq ferr_irq;
97
/* XXX: add IGNNE support */
98
void cpu_set_ferr(CPUX86State *s)
99
{
100
    qemu_irq_raise(ferr_irq);
101
}
102

    
103
static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
104
{
105
    qemu_irq_lower(ferr_irq);
106
}
107

    
108
/* TSC handling */
109
uint64_t cpu_get_tsc(CPUX86State *env)
110
{
111
    /* Note: when using kqemu, it is more logical to return the host TSC
112
       because kqemu does not trap the RDTSC instruction for
113
       performance reasons */
114
#ifdef CONFIG_KQEMU
115
    if (env->kqemu_enabled) {
116
        return cpu_get_real_ticks();
117
    } else
118
#endif
119
    {
120
        return cpu_get_ticks();
121
    }
122
}
123

    
124
/* SMM support */
125
void cpu_smm_update(CPUState *env)
126
{
127
    if (i440fx_state && env == first_cpu)
128
        i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
129
}
130

    
131

    
132
/* IRQ handling */
133
int cpu_get_pic_interrupt(CPUState *env)
134
{
135
    int intno;
136

    
137
    intno = apic_get_interrupt(env);
138
    if (intno >= 0) {
139
        /* set irq request if a PIC irq is still pending */
140
        /* XXX: improve that */
141
        pic_update_irq(isa_pic);
142
        return intno;
143
    }
144
    /* read the irq from the PIC */
145
    if (!apic_accept_pic_intr(env))
146
        return -1;
147

    
148
    intno = pic_read_irq(isa_pic);
149
    return intno;
150
}
151

    
152
static void pic_irq_request(void *opaque, int irq, int level)
153
{
154
    CPUState *env = first_cpu;
155

    
156
    if (env->apic_state) {
157
        while (env) {
158
            if (apic_accept_pic_intr(env))
159
                apic_deliver_pic_intr(env, level);
160
            env = env->next_cpu;
161
        }
162
    } else {
163
        if (level)
164
            cpu_interrupt(env, CPU_INTERRUPT_HARD);
165
        else
166
            cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
167
    }
168
}
169

    
170
/* PC cmos mappings */
171

    
172
#define REG_EQUIPMENT_BYTE          0x14
173

    
174
static int cmos_get_fd_drive_type(int fd0)
175
{
176
    int val;
177

    
178
    switch (fd0) {
179
    case 0:
180
        /* 1.44 Mb 3"5 drive */
181
        val = 4;
182
        break;
183
    case 1:
184
        /* 2.88 Mb 3"5 drive */
185
        val = 5;
186
        break;
187
    case 2:
188
        /* 1.2 Mb 5"5 drive */
189
        val = 2;
190
        break;
191
    default:
192
        val = 0;
193
        break;
194
    }
195
    return val;
196
}
197

    
198
static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
199
{
200
    RTCState *s = rtc_state;
201
    int cylinders, heads, sectors;
202
    bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
203
    rtc_set_memory(s, type_ofs, 47);
204
    rtc_set_memory(s, info_ofs, cylinders);
205
    rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
206
    rtc_set_memory(s, info_ofs + 2, heads);
207
    rtc_set_memory(s, info_ofs + 3, 0xff);
208
    rtc_set_memory(s, info_ofs + 4, 0xff);
209
    rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
210
    rtc_set_memory(s, info_ofs + 6, cylinders);
211
    rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
212
    rtc_set_memory(s, info_ofs + 8, sectors);
213
}
214

    
215
/* convert boot_device letter to something recognizable by the bios */
216
static int boot_device2nibble(char boot_device)
217
{
218
    switch(boot_device) {
219
    case 'a':
220
    case 'b':
221
        return 0x01; /* floppy boot */
222
    case 'c':
223
        return 0x02; /* hard drive boot */
224
    case 'd':
225
        return 0x03; /* CD-ROM boot */
226
    case 'n':
227
        return 0x04; /* Network boot */
228
    }
229
    return 0;
230
}
231

    
232
/* copy/pasted from cmos_init, should be made a general function
233
 and used there as well */
234
static int pc_boot_set(void *opaque, const char *boot_device)
235
{
236
    Monitor *mon = cur_mon;
237
#define PC_MAX_BOOT_DEVICES 3
238
    RTCState *s = (RTCState *)opaque;
239
    int nbds, bds[3] = { 0, };
240
    int i;
241

    
242
    nbds = strlen(boot_device);
243
    if (nbds > PC_MAX_BOOT_DEVICES) {
244
        monitor_printf(mon, "Too many boot devices for PC\n");
245
        return(1);
246
    }
247
    for (i = 0; i < nbds; i++) {
248
        bds[i] = boot_device2nibble(boot_device[i]);
249
        if (bds[i] == 0) {
250
            monitor_printf(mon, "Invalid boot device for PC: '%c'\n",
251
                           boot_device[i]);
252
            return(1);
253
        }
254
    }
255
    rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
256
    rtc_set_memory(s, 0x38, (bds[2] << 4));
257
    return(0);
258
}
259

    
260
/* hd_table must contain 4 block drivers */
261
static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
262
                      const char *boot_device, BlockDriverState **hd_table)
263
{
264
    RTCState *s = rtc_state;
265
    int nbds, bds[3] = { 0, };
266
    int val;
267
    int fd0, fd1, nb;
268
    int i;
269

    
270
    /* various important CMOS locations needed by PC/Bochs bios */
271

    
272
    /* memory size */
273
    val = 640; /* base memory in K */
274
    rtc_set_memory(s, 0x15, val);
275
    rtc_set_memory(s, 0x16, val >> 8);
276

    
277
    val = (ram_size / 1024) - 1024;
278
    if (val > 65535)
279
        val = 65535;
280
    rtc_set_memory(s, 0x17, val);
281
    rtc_set_memory(s, 0x18, val >> 8);
282
    rtc_set_memory(s, 0x30, val);
283
    rtc_set_memory(s, 0x31, val >> 8);
284

    
285
    if (above_4g_mem_size) {
286
        rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
287
        rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
288
        rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
289
    }
290

    
291
    if (ram_size > (16 * 1024 * 1024))
292
        val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
293
    else
294
        val = 0;
295
    if (val > 65535)
296
        val = 65535;
297
    rtc_set_memory(s, 0x34, val);
298
    rtc_set_memory(s, 0x35, val >> 8);
299

    
300
    /* set the number of CPU */
301
    rtc_set_memory(s, 0x5f, smp_cpus - 1);
302

    
303
    /* set boot devices, and disable floppy signature check if requested */
304
#define PC_MAX_BOOT_DEVICES 3
305
    nbds = strlen(boot_device);
306
    if (nbds > PC_MAX_BOOT_DEVICES) {
307
        fprintf(stderr, "Too many boot devices for PC\n");
308
        exit(1);
309
    }
310
    for (i = 0; i < nbds; i++) {
311
        bds[i] = boot_device2nibble(boot_device[i]);
312
        if (bds[i] == 0) {
313
            fprintf(stderr, "Invalid boot device for PC: '%c'\n",
314
                    boot_device[i]);
315
            exit(1);
316
        }
317
    }
318
    rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
319
    rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ?  0x0 : 0x1));
320

    
321
    /* floppy type */
322

    
323
    fd0 = fdctrl_get_drive_type(floppy_controller, 0);
324
    fd1 = fdctrl_get_drive_type(floppy_controller, 1);
325

    
326
    val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
327
    rtc_set_memory(s, 0x10, val);
328

    
329
    val = 0;
330
    nb = 0;
331
    if (fd0 < 3)
332
        nb++;
333
    if (fd1 < 3)
334
        nb++;
335
    switch (nb) {
336
    case 0:
337
        break;
338
    case 1:
339
        val |= 0x01; /* 1 drive, ready for boot */
340
        break;
341
    case 2:
342
        val |= 0x41; /* 2 drives, ready for boot */
343
        break;
344
    }
345
    val |= 0x02; /* FPU is there */
346
    val |= 0x04; /* PS/2 mouse installed */
347
    rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
348

    
349
    /* hard drives */
350

    
351
    rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
352
    if (hd_table[0])
353
        cmos_init_hd(0x19, 0x1b, hd_table[0]);
354
    if (hd_table[1])
355
        cmos_init_hd(0x1a, 0x24, hd_table[1]);
356

    
357
    val = 0;
358
    for (i = 0; i < 4; i++) {
359
        if (hd_table[i]) {
360
            int cylinders, heads, sectors, translation;
361
            /* NOTE: bdrv_get_geometry_hint() returns the physical
362
                geometry.  It is always such that: 1 <= sects <= 63, 1
363
                <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
364
                geometry can be different if a translation is done. */
365
            translation = bdrv_get_translation_hint(hd_table[i]);
366
            if (translation == BIOS_ATA_TRANSLATION_AUTO) {
367
                bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
368
                if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
369
                    /* No translation. */
370
                    translation = 0;
371
                } else {
372
                    /* LBA translation. */
373
                    translation = 1;
374
                }
375
            } else {
376
                translation--;
377
            }
378
            val |= translation << (i * 2);
379
        }
380
    }
381
    rtc_set_memory(s, 0x39, val);
382
}
383

    
384
void ioport_set_a20(int enable)
385
{
386
    /* XXX: send to all CPUs ? */
387
    cpu_x86_set_a20(first_cpu, enable);
388
}
389

    
390
int ioport_get_a20(void)
391
{
392
    return ((first_cpu->a20_mask >> 20) & 1);
393
}
394

    
395
static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
396
{
397
    ioport_set_a20((val >> 1) & 1);
398
    /* XXX: bit 0 is fast reset */
399
}
400

    
401
static uint32_t ioport92_read(void *opaque, uint32_t addr)
402
{
403
    return ioport_get_a20() << 1;
404
}
405

    
406
/***********************************************************/
407
/* Bochs BIOS debug ports */
408

    
409
static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
410
{
411
    static const char shutdown_str[8] = "Shutdown";
412
    static int shutdown_index = 0;
413

    
414
    switch(addr) {
415
        /* Bochs BIOS messages */
416
    case 0x400:
417
    case 0x401:
418
        fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
419
        exit(1);
420
    case 0x402:
421
    case 0x403:
422
#ifdef DEBUG_BIOS
423
        fprintf(stderr, "%c", val);
424
#endif
425
        break;
426
    case 0x8900:
427
        /* same as Bochs power off */
428
        if (val == shutdown_str[shutdown_index]) {
429
            shutdown_index++;
430
            if (shutdown_index == 8) {
431
                shutdown_index = 0;
432
                qemu_system_shutdown_request();
433
            }
434
        } else {
435
            shutdown_index = 0;
436
        }
437
        break;
438

    
439
        /* LGPL'ed VGA BIOS messages */
440
    case 0x501:
441
    case 0x502:
442
        fprintf(stderr, "VGA BIOS panic, line %d\n", val);
443
        exit(1);
444
    case 0x500:
445
    case 0x503:
446
#ifdef DEBUG_BIOS
447
        fprintf(stderr, "%c", val);
448
#endif
449
        break;
450
    }
451
}
452

    
453
extern uint64_t node_cpumask[MAX_NODES];
454

    
455
static void *bochs_bios_init(void)
456
{
457
    void *fw_cfg;
458
    uint8_t *smbios_table;
459
    size_t smbios_len;
460
    uint64_t *numa_fw_cfg;
461
    int i, j;
462

    
463
    register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
464
    register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
465
    register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
466
    register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
467
    register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
468

    
469
    register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
470
    register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
471
    register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
472
    register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
473

    
474
    fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
475

    
476
    fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
477
    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
478
    fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
479
                     acpi_tables_len);
480
    fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
481

    
482
    smbios_table = smbios_get_table(&smbios_len);
483
    if (smbios_table)
484
        fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
485
                         smbios_table, smbios_len);
486

    
487
    /* allocate memory for the NUMA channel: one (64bit) word for the number
488
     * of nodes, one word for each VCPU->node and one word for each node to
489
     * hold the amount of memory.
490
     */
491
    numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
492
    numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
493
    for (i = 0; i < smp_cpus; i++) {
494
        for (j = 0; j < nb_numa_nodes; j++) {
495
            if (node_cpumask[j] & (1 << i)) {
496
                numa_fw_cfg[i + 1] = cpu_to_le64(j);
497
                break;
498
            }
499
        }
500
    }
501
    for (i = 0; i < nb_numa_nodes; i++) {
502
        numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
503
    }
504
    fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
505
                     (1 + smp_cpus + nb_numa_nodes) * 8);
506

    
507
    return fw_cfg;
508
}
509

    
510
/* Generate an initial boot sector which sets state and jump to
511
   a specified vector */
512
static void generate_bootsect(target_phys_addr_t option_rom,
513
                              uint32_t gpr[8], uint16_t segs[6], uint16_t ip)
514
{
515
    uint8_t rom[512], *p, *reloc;
516
    uint8_t sum;
517
    int i;
518

    
519
    memset(rom, 0, sizeof(rom));
520

    
521
    p = rom;
522
    /* Make sure we have an option rom signature */
523
    *p++ = 0x55;
524
    *p++ = 0xaa;
525

    
526
    /* ROM size in sectors*/
527
    *p++ = 1;
528

    
529
    /* Hook int19 */
530

    
531
    *p++ = 0x50;                /* push ax */
532
    *p++ = 0x1e;                /* push ds */
533
    *p++ = 0x31; *p++ = 0xc0;        /* xor ax, ax */
534
    *p++ = 0x8e; *p++ = 0xd8;        /* mov ax, ds */
535

    
536
    *p++ = 0xc7; *p++ = 0x06;   /* movvw _start,0x64 */
537
    *p++ = 0x64; *p++ = 0x00;
538
    reloc = p;
539
    *p++ = 0x00; *p++ = 0x00;
540

    
541
    *p++ = 0x8c; *p++ = 0x0e;   /* mov cs,0x66 */
542
    *p++ = 0x66; *p++ = 0x00;
543

    
544
    *p++ = 0x1f;                /* pop ds */
545
    *p++ = 0x58;                /* pop ax */
546
    *p++ = 0xcb;                /* lret */
547
    
548
    /* Actual code */
549
    *reloc = (p - rom);
550

    
551
    *p++ = 0xfa;                /* CLI */
552
    *p++ = 0xfc;                /* CLD */
553

    
554
    for (i = 0; i < 6; i++) {
555
        if (i == 1)                /* Skip CS */
556
            continue;
557

    
558
        *p++ = 0xb8;                /* MOV AX,imm16 */
559
        *p++ = segs[i];
560
        *p++ = segs[i] >> 8;
561
        *p++ = 0x8e;                /* MOV <seg>,AX */
562
        *p++ = 0xc0 + (i << 3);
563
    }
564

    
565
    for (i = 0; i < 8; i++) {
566
        *p++ = 0x66;                /* 32-bit operand size */
567
        *p++ = 0xb8 + i;        /* MOV <reg>,imm32 */
568
        *p++ = gpr[i];
569
        *p++ = gpr[i] >> 8;
570
        *p++ = gpr[i] >> 16;
571
        *p++ = gpr[i] >> 24;
572
    }
573

    
574
    *p++ = 0xea;                /* JMP FAR */
575
    *p++ = ip;                        /* IP */
576
    *p++ = ip >> 8;
577
    *p++ = segs[1];                /* CS */
578
    *p++ = segs[1] >> 8;
579

    
580
    /* sign rom */
581
    sum = 0;
582
    for (i = 0; i < (sizeof(rom) - 1); i++)
583
        sum += rom[i];
584
    rom[sizeof(rom) - 1] = -sum;
585

    
586
    cpu_physical_memory_write_rom(option_rom, rom, sizeof(rom));
587
    option_rom_setup_reset(option_rom, sizeof (rom));
588
}
589

    
590
static long get_file_size(FILE *f)
591
{
592
    long where, size;
593

    
594
    /* XXX: on Unix systems, using fstat() probably makes more sense */
595

    
596
    where = ftell(f);
597
    fseek(f, 0, SEEK_END);
598
    size = ftell(f);
599
    fseek(f, where, SEEK_SET);
600

    
601
    return size;
602
}
603

    
604
#define MULTIBOOT_STRUCT_ADDR 0x9000
605

    
606
#if MULTIBOOT_STRUCT_ADDR > 0xf0000
607
#error multiboot struct needs to fit in 16 bit real mode
608
#endif
609

    
610
static int load_multiboot(void *fw_cfg,
611
                          FILE *f,
612
                          const char *kernel_filename,
613
                          const char *initrd_filename,
614
                          const char *kernel_cmdline,
615
                          uint8_t *header)
616
{
617
    int i, t, is_multiboot = 0;
618
    uint32_t flags = 0;
619
    uint32_t mh_entry_addr;
620
    uint32_t mh_load_addr;
621
    uint32_t mb_kernel_size;
622
    uint32_t mmap_addr = MULTIBOOT_STRUCT_ADDR;
623
    uint32_t mb_bootinfo = MULTIBOOT_STRUCT_ADDR + 0x500;
624
    uint32_t mb_cmdline = mb_bootinfo + 0x200;
625
    uint32_t mb_mod_end;
626

    
627
    /* Ok, let's see if it is a multiboot image.
628
       The header is 12x32bit long, so the latest entry may be 8192 - 48. */
629
    for (i = 0; i < (8192 - 48); i += 4) {
630
        if (ldl_p(header+i) == 0x1BADB002) {
631
            uint32_t checksum = ldl_p(header+i+8);
632
            flags = ldl_p(header+i+4);
633
            checksum += flags;
634
            checksum += (uint32_t)0x1BADB002;
635
            if (!checksum) {
636
                is_multiboot = 1;
637
                break;
638
            }
639
        }
640
    }
641

    
642
    if (!is_multiboot)
643
        return 0; /* no multiboot */
644

    
645
#ifdef DEBUG_MULTIBOOT
646
    fprintf(stderr, "qemu: I believe we found a multiboot image!\n");
647
#endif
648

    
649
    if (flags & 0x00000004) { /* MULTIBOOT_HEADER_HAS_VBE */
650
        fprintf(stderr, "qemu: multiboot knows VBE. we don't.\n");
651
    }
652
    if (!(flags & 0x00010000)) { /* MULTIBOOT_HEADER_HAS_ADDR */
653
        uint64_t elf_entry;
654
        int kernel_size;
655
        fclose(f);
656
        kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL);
657
        if (kernel_size < 0) {
658
            fprintf(stderr, "Error while loading elf kernel\n");
659
            exit(1);
660
        }
661
        mh_load_addr = mh_entry_addr = elf_entry;
662
        mb_kernel_size = kernel_size;
663

    
664
#ifdef DEBUG_MULTIBOOT
665
        fprintf(stderr, "qemu: loading multiboot-elf kernel (%#x bytes) with entry %#zx\n",
666
                mb_kernel_size, (size_t)mh_entry_addr);
667
#endif
668
    } else {
669
        /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_ADDR. */
670
        uint32_t mh_header_addr = ldl_p(header+i+12);
671
        mh_load_addr = ldl_p(header+i+16);
672
#ifdef DEBUG_MULTIBOOT
673
        uint32_t mh_load_end_addr = ldl_p(header+i+20);
674
        uint32_t mh_bss_end_addr = ldl_p(header+i+24);
675
#endif
676
        uint32_t mb_kernel_text_offset = i - (mh_header_addr - mh_load_addr);
677

    
678
        mh_entry_addr = ldl_p(header+i+28);
679
        mb_kernel_size = get_file_size(f) - mb_kernel_text_offset;
680

    
681
        /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_VBE.
682
        uint32_t mh_mode_type = ldl_p(header+i+32);
683
        uint32_t mh_width = ldl_p(header+i+36);
684
        uint32_t mh_height = ldl_p(header+i+40);
685
        uint32_t mh_depth = ldl_p(header+i+44); */
686

    
687
#ifdef DEBUG_MULTIBOOT
688
        fprintf(stderr, "multiboot: mh_header_addr = %#x\n", mh_header_addr);
689
        fprintf(stderr, "multiboot: mh_load_addr = %#x\n", mh_load_addr);
690
        fprintf(stderr, "multiboot: mh_load_end_addr = %#x\n", mh_load_end_addr);
691
        fprintf(stderr, "multiboot: mh_bss_end_addr = %#x\n", mh_bss_end_addr);
692
#endif
693

    
694
        fseek(f, mb_kernel_text_offset, SEEK_SET);
695

    
696
#ifdef DEBUG_MULTIBOOT
697
        fprintf(stderr, "qemu: loading multiboot kernel (%#x bytes) at %#x\n",
698
                mb_kernel_size, mh_load_addr);
699
#endif
700

    
701
        if (!fread_targphys_ok(mh_load_addr, mb_kernel_size, f)) {
702
            fprintf(stderr, "qemu: read error on multiboot kernel '%s' (%#x)\n",
703
                    kernel_filename, mb_kernel_size);
704
            exit(1);
705
        }
706
        fclose(f);
707
    }
708

    
709
    /* blob size is only the kernel for now */
710
    mb_mod_end = mh_load_addr + mb_kernel_size;
711

    
712
    /* load modules */
713
    stl_phys(mb_bootinfo + 20, 0x0); /* mods_count */
714
    if (initrd_filename) {
715
        uint32_t mb_mod_info = mb_bootinfo + 0x100;
716
        uint32_t mb_mod_cmdline = mb_bootinfo + 0x300;
717
        uint32_t mb_mod_start = mh_load_addr;
718
        uint32_t mb_mod_length = mb_kernel_size;
719
        char *next_initrd;
720
        char *next_space;
721
        int mb_mod_count = 0;
722

    
723
        do {
724
            next_initrd = strchr(initrd_filename, ',');
725
            if (next_initrd)
726
                *next_initrd = '\0';
727
            /* if a space comes after the module filename, treat everything
728
               after that as parameters */
729
            cpu_physical_memory_write(mb_mod_cmdline, (uint8_t*)initrd_filename,
730
                                      strlen(initrd_filename) + 1);
731
            stl_phys(mb_mod_info + 8, mb_mod_cmdline); /* string */
732
            mb_mod_cmdline += strlen(initrd_filename) + 1;
733
            if ((next_space = strchr(initrd_filename, ' ')))
734
                *next_space = '\0';
735
#ifdef DEBUG_MULTIBOOT
736
             printf("multiboot loading module: %s\n", initrd_filename);
737
#endif
738
            f = fopen(initrd_filename, "rb");
739
            if (f) {
740
                mb_mod_start = (mb_mod_start + mb_mod_length + (TARGET_PAGE_SIZE - 1))
741
                             & (TARGET_PAGE_MASK);
742
                mb_mod_length = get_file_size(f);
743
                mb_mod_end = mb_mod_start + mb_mod_length;
744

    
745
                if (!fread_targphys_ok(mb_mod_start, mb_mod_length, f)) {
746
                    fprintf(stderr, "qemu: read error on multiboot module '%s' (%#x)\n",
747
                            initrd_filename, mb_mod_length);
748
                    exit(1);
749
                }
750

    
751
                mb_mod_count++;
752
                stl_phys(mb_mod_info + 0, mb_mod_start);
753
                stl_phys(mb_mod_info + 4, mb_mod_start + mb_mod_length);
754
#ifdef DEBUG_MULTIBOOT
755
                printf("mod_start: %#x\nmod_end:   %#x\n", mb_mod_start,
756
                       mb_mod_start + mb_mod_length);
757
#endif
758
                stl_phys(mb_mod_info + 12, 0x0); /* reserved */
759
            }
760
            initrd_filename = next_initrd+1;
761
            mb_mod_info += 16;
762
        } while (next_initrd);
763
        stl_phys(mb_bootinfo + 20, mb_mod_count); /* mods_count */
764
        stl_phys(mb_bootinfo + 24, mb_bootinfo + 0x100); /* mods_addr */
765
    }
766

    
767
    /* Make sure we're getting kernel + modules back after reset */
768
    option_rom_setup_reset(mh_load_addr, mb_mod_end - mh_load_addr);
769

    
770
    /* Commandline support */
771
    stl_phys(mb_bootinfo + 16, mb_cmdline);
772
    t = strlen(kernel_filename);
773
    cpu_physical_memory_write(mb_cmdline, (uint8_t*)kernel_filename, t);
774
    mb_cmdline += t;
775
    stb_phys(mb_cmdline++, ' ');
776
    t = strlen(kernel_cmdline) + 1;
777
    cpu_physical_memory_write(mb_cmdline, (uint8_t*)kernel_cmdline, t);
778

    
779
    /* the kernel is where we want it to be now */
780

    
781
#define MULTIBOOT_FLAGS_MEMORY (1 << 0)
782
#define MULTIBOOT_FLAGS_BOOT_DEVICE (1 << 1)
783
#define MULTIBOOT_FLAGS_CMDLINE (1 << 2)
784
#define MULTIBOOT_FLAGS_MODULES (1 << 3)
785
#define MULTIBOOT_FLAGS_MMAP (1 << 6)
786
    stl_phys(mb_bootinfo, MULTIBOOT_FLAGS_MEMORY
787
                        | MULTIBOOT_FLAGS_BOOT_DEVICE
788
                        | MULTIBOOT_FLAGS_CMDLINE
789
                        | MULTIBOOT_FLAGS_MODULES
790
                        | MULTIBOOT_FLAGS_MMAP);
791
    stl_phys(mb_bootinfo + 4, 640); /* mem_lower */
792
    stl_phys(mb_bootinfo + 8, ram_size / 1024); /* mem_upper */
793
    stl_phys(mb_bootinfo + 12, 0x8001ffff); /* XXX: use the -boot switch? */
794
    stl_phys(mb_bootinfo + 48, mmap_addr); /* mmap_addr */
795

    
796
#ifdef DEBUG_MULTIBOOT
797
    fprintf(stderr, "multiboot: mh_entry_addr = %#x\n", mh_entry_addr);
798
#endif
799

    
800
    /* Pass variables to option rom */
801
    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_entry_addr);
802
    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, mb_bootinfo);
803
    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, mmap_addr);
804

    
805
    /* Make sure we're getting the config space back after reset */
806
    option_rom_setup_reset(mb_bootinfo, 0x500);
807

    
808
    option_rom[nb_option_roms] = "multiboot.bin";
809
    nb_option_roms++;
810

    
811
    return 1; /* yes, we are multiboot */
812
}
813

    
814
static void load_linux(void *fw_cfg,
815
                       target_phys_addr_t option_rom,
816
                       const char *kernel_filename,
817
                       const char *initrd_filename,
818
                       const char *kernel_cmdline,
819
               target_phys_addr_t max_ram_size)
820
{
821
    uint16_t protocol;
822
    uint32_t gpr[8];
823
    uint16_t seg[6];
824
    uint16_t real_seg;
825
    int setup_size, kernel_size, initrd_size = 0, cmdline_size;
826
    uint32_t initrd_max;
827
    uint8_t header[8192];
828
    target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
829
    FILE *f, *fi;
830
    char *vmode;
831

    
832
    /* Align to 16 bytes as a paranoia measure */
833
    cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
834

    
835
    /* load the kernel header */
836
    f = fopen(kernel_filename, "rb");
837
    if (!f || !(kernel_size = get_file_size(f)) ||
838
        fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
839
        MIN(ARRAY_SIZE(header), kernel_size)) {
840
        fprintf(stderr, "qemu: could not load kernel '%s'\n",
841
                kernel_filename);
842
        exit(1);
843
    }
844

    
845
    /* kernel protocol version */
846
#if 0
847
    fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
848
#endif
849
    if (ldl_p(header+0x202) == 0x53726448)
850
        protocol = lduw_p(header+0x206);
851
    else {
852
        /* This looks like a multiboot kernel. If it is, let's stop
853
           treating it like a Linux kernel. */
854
        if (load_multiboot(fw_cfg, f, kernel_filename,
855
                           initrd_filename, kernel_cmdline, header))
856
           return;
857
        protocol = 0;
858
    }
859

    
860
    if (protocol < 0x200 || !(header[0x211] & 0x01)) {
861
        /* Low kernel */
862
        real_addr    = 0x90000;
863
        cmdline_addr = 0x9a000 - cmdline_size;
864
        prot_addr    = 0x10000;
865
    } else if (protocol < 0x202) {
866
        /* High but ancient kernel */
867
        real_addr    = 0x90000;
868
        cmdline_addr = 0x9a000 - cmdline_size;
869
        prot_addr    = 0x100000;
870
    } else {
871
        /* High and recent kernel */
872
        real_addr    = 0x10000;
873
        cmdline_addr = 0x20000;
874
        prot_addr    = 0x100000;
875
    }
876

    
877
#if 0
878
    fprintf(stderr,
879
            "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
880
            "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
881
            "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
882
            real_addr,
883
            cmdline_addr,
884
            prot_addr);
885
#endif
886

    
887
    /* highest address for loading the initrd */
888
    if (protocol >= 0x203)
889
        initrd_max = ldl_p(header+0x22c);
890
    else
891
        initrd_max = 0x37ffffff;
892

    
893
    if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
894
            initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
895

    
896
    /* kernel command line */
897
    pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline);
898

    
899
    if (protocol >= 0x202) {
900
        stl_p(header+0x228, cmdline_addr);
901
    } else {
902
        stw_p(header+0x20, 0xA33F);
903
        stw_p(header+0x22, cmdline_addr-real_addr);
904
    }
905

    
906
    /* handle vga= parameter */
907
    vmode = strstr(kernel_cmdline, "vga=");
908
    if (vmode) {
909
        unsigned int video_mode;
910
        /* skip "vga=" */
911
        vmode += 4;
912
        if (!strncmp(vmode, "normal", 6)) {
913
            video_mode = 0xffff;
914
        } else if (!strncmp(vmode, "ext", 3)) {
915
            video_mode = 0xfffe;
916
        } else if (!strncmp(vmode, "ask", 3)) {
917
            video_mode = 0xfffd;
918
        } else {
919
            video_mode = strtol(vmode, NULL, 0);
920
        }
921
        stw_p(header+0x1fa, video_mode);
922
    }
923

    
924
    /* loader type */
925
    /* High nybble = B reserved for Qemu; low nybble is revision number.
926
       If this code is substantially changed, you may want to consider
927
       incrementing the revision. */
928
    if (protocol >= 0x200)
929
        header[0x210] = 0xB0;
930

    
931
    /* heap */
932
    if (protocol >= 0x201) {
933
        header[0x211] |= 0x80;        /* CAN_USE_HEAP */
934
        stw_p(header+0x224, cmdline_addr-real_addr-0x200);
935
    }
936

    
937
    /* load initrd */
938
    if (initrd_filename) {
939
        if (protocol < 0x200) {
940
            fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
941
            exit(1);
942
        }
943

    
944
        fi = fopen(initrd_filename, "rb");
945
        if (!fi) {
946
            fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
947
                    initrd_filename);
948
            exit(1);
949
        }
950

    
951
        initrd_size = get_file_size(fi);
952
        initrd_addr = (initrd_max-initrd_size) & ~4095;
953

    
954
        if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) {
955
            fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
956
                    initrd_filename);
957
            exit(1);
958
        }
959
        fclose(fi);
960

    
961
        stl_p(header+0x218, initrd_addr);
962
        stl_p(header+0x21c, initrd_size);
963
    }
964

    
965
    /* store the finalized header and load the rest of the kernel */
966
    cpu_physical_memory_write(real_addr, header, ARRAY_SIZE(header));
967

    
968
    setup_size = header[0x1f1];
969
    if (setup_size == 0)
970
        setup_size = 4;
971

    
972
    setup_size = (setup_size+1)*512;
973
    /* Size of protected-mode code */
974
    kernel_size -= (setup_size > ARRAY_SIZE(header)) ? setup_size : ARRAY_SIZE(header);
975

    
976
    /* In case we have read too much already, copy that over */
977
    if (setup_size < ARRAY_SIZE(header)) {
978
        cpu_physical_memory_write(prot_addr, header + setup_size, ARRAY_SIZE(header) - setup_size);
979
        prot_addr += (ARRAY_SIZE(header) - setup_size);
980
        setup_size = ARRAY_SIZE(header);
981
    }
982

    
983
    if (!fread_targphys_ok(real_addr + ARRAY_SIZE(header),
984
                           setup_size - ARRAY_SIZE(header), f) ||
985
        !fread_targphys_ok(prot_addr, kernel_size, f)) {
986
        fprintf(stderr, "qemu: read error on kernel '%s'\n",
987
                kernel_filename);
988
        exit(1);
989
    }
990
    fclose(f);
991

    
992
    /* generate bootsector to set up the initial register state */
993
    real_seg = real_addr >> 4;
994
    seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg;
995
    seg[1] = real_seg+0x20;        /* CS */
996
    memset(gpr, 0, sizeof gpr);
997
    gpr[4] = cmdline_addr-real_addr-16;        /* SP (-16 is paranoia) */
998

    
999
    option_rom_setup_reset(real_addr, setup_size);
1000
    option_rom_setup_reset(prot_addr, kernel_size);
1001
    option_rom_setup_reset(cmdline_addr, cmdline_size);
1002
    if (initrd_filename)
1003
        option_rom_setup_reset(initrd_addr, initrd_size);
1004

    
1005
    generate_bootsect(option_rom, gpr, seg, 0);
1006
}
1007

    
1008
static const int ide_iobase[2] = { 0x1f0, 0x170 };
1009
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
1010
static const int ide_irq[2] = { 14, 15 };
1011

    
1012
#define NE2000_NB_MAX 6
1013

    
1014
static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
1015
static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1016

    
1017
static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
1018
static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
1019

    
1020
static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
1021
static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
1022

    
1023
#ifdef HAS_AUDIO
1024
static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
1025
{
1026
    struct soundhw *c;
1027

    
1028
    for (c = soundhw; c->name; ++c) {
1029
        if (c->enabled) {
1030
            if (c->isa) {
1031
                c->init.init_isa(pic);
1032
            } else {
1033
                if (pci_bus) {
1034
                    c->init.init_pci(pci_bus);
1035
                }
1036
            }
1037
        }
1038
    }
1039
}
1040
#endif
1041

    
1042
static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
1043
{
1044
    static int nb_ne2k = 0;
1045

    
1046
    if (nb_ne2k == NE2000_NB_MAX)
1047
        return;
1048
    isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd);
1049
    nb_ne2k++;
1050
}
1051

    
1052
static int load_option_rom(const char *oprom, target_phys_addr_t start,
1053
                           target_phys_addr_t end)
1054
{
1055
        int size;
1056
        char *filename;
1057

    
1058
        filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, oprom);
1059
        if (filename) {
1060
            size = get_image_size(filename);
1061
            if (size > 0 && start + size > end) {
1062
                fprintf(stderr, "Not enough space to load option rom '%s'\n",
1063
                        oprom);
1064
                exit(1);
1065
            }
1066
            size = load_image_targphys(filename, start, end - start);
1067
            qemu_free(filename);
1068
        } else {
1069
            size = -1;
1070
        }
1071
        if (size < 0) {
1072
            fprintf(stderr, "Could not load option rom '%s'\n", oprom);
1073
            exit(1);
1074
        }
1075
        /* Round up optiom rom size to the next 2k boundary */
1076
        size = (size + 2047) & ~2047;
1077
        option_rom_setup_reset(start, size);
1078
        return size;
1079
}
1080

    
1081
int cpu_is_bsp(CPUState *env)
1082
{
1083
        return env->cpuid_apic_id == 0;
1084
}
1085

    
1086
static CPUState *pc_new_cpu(const char *cpu_model)
1087
{
1088
    CPUState *env;
1089

    
1090
    env = cpu_init(cpu_model);
1091
    if (!env) {
1092
        fprintf(stderr, "Unable to find x86 CPU definition\n");
1093
        exit(1);
1094
    }
1095
    if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
1096
        env->cpuid_apic_id = env->cpu_index;
1097
        /* APIC reset callback resets cpu */
1098
        apic_init(env);
1099
    } else {
1100
        qemu_register_reset((QEMUResetHandler*)cpu_reset, env);
1101
    }
1102
    return env;
1103
}
1104

    
1105
/* PC hardware initialisation */
1106
static void pc_init1(ram_addr_t ram_size,
1107
                     const char *boot_device,
1108
                     const char *kernel_filename,
1109
                     const char *kernel_cmdline,
1110
                     const char *initrd_filename,
1111
                     const char *cpu_model,
1112
                     int pci_enabled)
1113
{
1114
    char *filename;
1115
    int ret, linux_boot, i;
1116
    ram_addr_t ram_addr, bios_offset, option_rom_offset;
1117
    ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
1118
    int bios_size, isa_bios_size, oprom_area_size;
1119
    PCIBus *pci_bus;
1120
    PCIDevice *pci_dev;
1121
    ISADevice *isa_dev;
1122
    int piix3_devfn = -1;
1123
    CPUState *env;
1124
    qemu_irq *cpu_irq;
1125
    qemu_irq *i8259;
1126
    DriveInfo *dinfo;
1127
    BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
1128
    BlockDriverState *fd[MAX_FD];
1129
    int using_vga = cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled;
1130
    void *fw_cfg;
1131

    
1132
    if (ram_size >= 0xe0000000 ) {
1133
        above_4g_mem_size = ram_size - 0xe0000000;
1134
        below_4g_mem_size = 0xe0000000;
1135
    } else {
1136
        below_4g_mem_size = ram_size;
1137
    }
1138

    
1139
    linux_boot = (kernel_filename != NULL);
1140

    
1141
    /* init CPUs */
1142
    if (cpu_model == NULL) {
1143
#ifdef TARGET_X86_64
1144
        cpu_model = "qemu64";
1145
#else
1146
        cpu_model = "qemu32";
1147
#endif
1148
    }
1149

    
1150
    for (i = 0; i < smp_cpus; i++) {
1151
        env = pc_new_cpu(cpu_model);
1152
    }
1153

    
1154
    vmport_init();
1155

    
1156
    /* allocate RAM */
1157
    ram_addr = qemu_ram_alloc(0xa0000);
1158
    cpu_register_physical_memory(0, 0xa0000, ram_addr);
1159

    
1160
    /* Allocate, even though we won't register, so we don't break the
1161
     * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
1162
     * and some bios areas, which will be registered later
1163
     */
1164
    ram_addr = qemu_ram_alloc(0x100000 - 0xa0000);
1165
    ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
1166
    cpu_register_physical_memory(0x100000,
1167
                 below_4g_mem_size - 0x100000,
1168
                 ram_addr);
1169

    
1170
    /* above 4giga memory allocation */
1171
    if (above_4g_mem_size > 0) {
1172
#if TARGET_PHYS_ADDR_BITS == 32
1173
        hw_error("To much RAM for 32-bit physical address");
1174
#else
1175
        ram_addr = qemu_ram_alloc(above_4g_mem_size);
1176
        cpu_register_physical_memory(0x100000000ULL,
1177
                                     above_4g_mem_size,
1178
                                     ram_addr);
1179
#endif
1180
    }
1181

    
1182

    
1183
    /* BIOS load */
1184
    if (bios_name == NULL)
1185
        bios_name = BIOS_FILENAME;
1186
    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1187
    if (filename) {
1188
        bios_size = get_image_size(filename);
1189
    } else {
1190
        bios_size = -1;
1191
    }
1192
    if (bios_size <= 0 ||
1193
        (bios_size % 65536) != 0) {
1194
        goto bios_error;
1195
    }
1196
    bios_offset = qemu_ram_alloc(bios_size);
1197
    ret = load_image(filename, qemu_get_ram_ptr(bios_offset));
1198
    if (ret != bios_size) {
1199
    bios_error:
1200
        fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
1201
        exit(1);
1202
    }
1203
    if (filename) {
1204
        qemu_free(filename);
1205
    }
1206
    /* map the last 128KB of the BIOS in ISA space */
1207
    isa_bios_size = bios_size;
1208
    if (isa_bios_size > (128 * 1024))
1209
        isa_bios_size = 128 * 1024;
1210
    cpu_register_physical_memory(0x100000 - isa_bios_size,
1211
                                 isa_bios_size,
1212
                                 (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
1213

    
1214

    
1215

    
1216
    option_rom_offset = qemu_ram_alloc(0x20000);
1217
    oprom_area_size = 0;
1218
    cpu_register_physical_memory(0xc0000, 0x20000, option_rom_offset);
1219

    
1220
    if (using_vga) {
1221
        const char *vgabios_filename;
1222
        /* VGA BIOS load */
1223
        if (cirrus_vga_enabled) {
1224
            vgabios_filename = VGABIOS_CIRRUS_FILENAME;
1225
        } else {
1226
            vgabios_filename = VGABIOS_FILENAME;
1227
        }
1228
        oprom_area_size = load_option_rom(vgabios_filename, 0xc0000, 0xe0000);
1229
    }
1230
    /* Although video roms can grow larger than 0x8000, the area between
1231
     * 0xc0000 - 0xc8000 is reserved for them. It means we won't be looking
1232
     * for any other kind of option rom inside this area */
1233
    if (oprom_area_size < 0x8000)
1234
        oprom_area_size = 0x8000;
1235

    
1236
    /* map all the bios at the top of memory */
1237
    cpu_register_physical_memory((uint32_t)(-bios_size),
1238
                                 bios_size, bios_offset | IO_MEM_ROM);
1239

    
1240
    fw_cfg = bochs_bios_init();
1241

    
1242
    if (linux_boot) {
1243
        load_linux(fw_cfg, 0xc0000 + oprom_area_size,
1244
                   kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1245
        oprom_area_size += 2048;
1246
    }
1247

    
1248
    for (i = 0; i < nb_option_roms; i++) {
1249
        oprom_area_size += load_option_rom(option_rom[i], 0xc0000 + oprom_area_size,
1250
                                           0xe0000);
1251
    }
1252

    
1253
    for (i = 0; i < nb_nics; i++) {
1254
        char nic_oprom[1024];
1255
        const char *model = nd_table[i].model;
1256

    
1257
        if (!nd_table[i].bootable)
1258
            continue;
1259

    
1260
        if (model == NULL)
1261
            model = "ne2k_pci";
1262
        snprintf(nic_oprom, sizeof(nic_oprom), "pxe-%s.bin", model);
1263

    
1264
        oprom_area_size += load_option_rom(nic_oprom, 0xc0000 + oprom_area_size,
1265
                                           0xe0000);
1266
    }
1267

    
1268
    cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
1269
    i8259 = i8259_init(cpu_irq[0]);
1270
    ferr_irq = i8259[13];
1271

    
1272
    if (pci_enabled) {
1273
        pci_bus = i440fx_init(&i440fx_state, i8259);
1274
        piix3_devfn = piix3_init(pci_bus, -1);
1275
    } else {
1276
        pci_bus = NULL;
1277
    }
1278

    
1279
    /* init basic PC hardware */
1280
    register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1281

    
1282
    register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1283

    
1284
    if (cirrus_vga_enabled) {
1285
        if (pci_enabled) {
1286
            pci_cirrus_vga_init(pci_bus);
1287
        } else {
1288
            isa_cirrus_vga_init();
1289
        }
1290
    } else if (vmsvga_enabled) {
1291
        if (pci_enabled)
1292
            pci_vmsvga_init(pci_bus);
1293
        else
1294
            fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1295
    } else if (std_vga_enabled) {
1296
        if (pci_enabled) {
1297
            pci_vga_init(pci_bus, 0, 0);
1298
        } else {
1299
            isa_vga_init();
1300
        }
1301
    }
1302

    
1303
    rtc_state = rtc_init(0x70, i8259[8], 2000);
1304

    
1305
    qemu_register_boot_set(pc_boot_set, rtc_state);
1306

    
1307
    register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
1308
    register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
1309

    
1310
    if (pci_enabled) {
1311
        ioapic = ioapic_init();
1312
    }
1313
    pit = pit_init(0x40, i8259[0]);
1314
    pcspk_init(pit);
1315
    if (!no_hpet) {
1316
        hpet_init(i8259);
1317
    }
1318
    if (pci_enabled) {
1319
        pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
1320
    }
1321

    
1322
    for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1323
        if (serial_hds[i]) {
1324
            serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
1325
                        serial_hds[i]);
1326
        }
1327
    }
1328

    
1329
    for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1330
        if (parallel_hds[i]) {
1331
            parallel_init(parallel_io[i], i8259[parallel_irq[i]],
1332
                          parallel_hds[i]);
1333
        }
1334
    }
1335

    
1336
    watchdog_pc_init(pci_bus);
1337

    
1338
    for(i = 0; i < nb_nics; i++) {
1339
        NICInfo *nd = &nd_table[i];
1340

    
1341
        if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
1342
            pc_init_ne2k_isa(nd, i8259);
1343
        else
1344
            pci_nic_init(nd, "ne2k_pci", NULL);
1345
    }
1346

    
1347
    piix4_acpi_system_hot_add_init();
1348

    
1349
    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
1350
        fprintf(stderr, "qemu: too many IDE bus\n");
1351
        exit(1);
1352
    }
1353

    
1354
    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
1355
        dinfo = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
1356
        hd[i] = dinfo ? dinfo->bdrv : NULL;
1357
    }
1358

    
1359
    if (pci_enabled) {
1360
        pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
1361
    } else {
1362
        for(i = 0; i < MAX_IDE_BUS; i++) {
1363
            isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
1364
                         hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
1365
        }
1366
    }
1367

    
1368
    isa_dev = isa_create_simple("i8042", 0x60, 0x64);
1369
    isa_connect_irq(isa_dev, 0, i8259[1]);
1370
    isa_connect_irq(isa_dev, 1, i8259[12]);
1371
    DMA_init(0);
1372
#ifdef HAS_AUDIO
1373
    audio_init(pci_enabled ? pci_bus : NULL, i8259);
1374
#endif
1375

    
1376
    for(i = 0; i < MAX_FD; i++) {
1377
        dinfo = drive_get(IF_FLOPPY, 0, i);
1378
        fd[i] = dinfo ? dinfo->bdrv : NULL;
1379
    }
1380
    floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
1381

    
1382
    cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
1383

    
1384
    if (pci_enabled && usb_enabled) {
1385
        usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1386
    }
1387

    
1388
    if (pci_enabled && acpi_enabled) {
1389
        uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1390
        i2c_bus *smbus;
1391

    
1392
        /* TODO: Populate SPD eeprom data.  */
1393
        smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]);
1394
        for (i = 0; i < 8; i++) {
1395
            DeviceState *eeprom;
1396
            eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
1397
            qdev_prop_set_uint32(eeprom, "address", 0x50 + i);
1398
            qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
1399
            qdev_init(eeprom);
1400
        }
1401
    }
1402

    
1403
    if (i440fx_state) {
1404
        i440fx_init_memory_mappings(i440fx_state);
1405
    }
1406

    
1407
    if (pci_enabled) {
1408
        int max_bus;
1409
        int bus;
1410

    
1411
        max_bus = drive_get_max_bus(IF_SCSI);
1412
        for (bus = 0; bus <= max_bus; bus++) {
1413
            pci_create_simple(pci_bus, -1, "lsi53c895a");
1414
        }
1415
    }
1416

    
1417
    /* Add virtio balloon device */
1418
    if (pci_enabled && virtio_balloon) {
1419
        pci_dev = pci_create("virtio-balloon-pci", virtio_balloon_devaddr);
1420
        qdev_init(&pci_dev->qdev);
1421
    }
1422

    
1423
    /* Add virtio console devices */
1424
    if (pci_enabled) {
1425
        for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) {
1426
            if (virtcon_hds[i]) {
1427
                pci_create_simple(pci_bus, -1, "virtio-console-pci");
1428
            }
1429
        }
1430
    }
1431
}
1432

    
1433
static void pc_init_pci(ram_addr_t ram_size,
1434
                        const char *boot_device,
1435
                        const char *kernel_filename,
1436
                        const char *kernel_cmdline,
1437
                        const char *initrd_filename,
1438
                        const char *cpu_model)
1439
{
1440
    pc_init1(ram_size, boot_device,
1441
             kernel_filename, kernel_cmdline,
1442
             initrd_filename, cpu_model, 1);
1443
}
1444

    
1445
static void pc_init_isa(ram_addr_t ram_size,
1446
                        const char *boot_device,
1447
                        const char *kernel_filename,
1448
                        const char *kernel_cmdline,
1449
                        const char *initrd_filename,
1450
                        const char *cpu_model)
1451
{
1452
    pc_init1(ram_size, boot_device,
1453
             kernel_filename, kernel_cmdline,
1454
             initrd_filename, cpu_model, 0);
1455
}
1456

    
1457
/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
1458
   BIOS will read it and start S3 resume at POST Entry */
1459
void cmos_set_s3_resume(void)
1460
{
1461
    if (rtc_state)
1462
        rtc_set_memory(rtc_state, 0xF, 0xFE);
1463
}
1464

    
1465
static QEMUMachine pc_machine = {
1466
    .name = "pc-0.11",
1467
    .alias = "pc",
1468
    .desc = "Standard PC",
1469
    .init = pc_init_pci,
1470
    .max_cpus = 255,
1471
    .is_default = 1,
1472
};
1473

    
1474
static QEMUMachine pc_machine_v0_10 = {
1475
    .name = "pc-0.10",
1476
    .desc = "Standard PC, qemu 0.10",
1477
    .init = pc_init_pci,
1478
    .max_cpus = 255,
1479
    .compat_props = (CompatProperty[]) {
1480
        {
1481
            .driver   = "virtio-blk-pci",
1482
            .property = "class",
1483
            .value    = stringify(PCI_CLASS_STORAGE_OTHER),
1484
        },{
1485
            .driver   = "virtio-console-pci",
1486
            .property = "class",
1487
            .value    = stringify(PCI_CLASS_DISPLAY_OTHER),
1488
        },{
1489
            .driver   = "virtio-net-pci",
1490
            .property = "vectors",
1491
            .value    = stringify(0),
1492
        },
1493
        { /* end of list */ }
1494
    },
1495
};
1496

    
1497
static QEMUMachine isapc_machine = {
1498
    .name = "isapc",
1499
    .desc = "ISA-only PC",
1500
    .init = pc_init_isa,
1501
    .max_cpus = 1,
1502
};
1503

    
1504
static void pc_machine_init(void)
1505
{
1506
    qemu_register_machine(&pc_machine);
1507
    qemu_register_machine(&pc_machine_v0_10);
1508
    qemu_register_machine(&isapc_machine);
1509
}
1510

    
1511
machine_init(pc_machine_init);