root / hw / ioh3420.c @ 6bde6aaa
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1 | 8135aeed | Isaku Yamahata | /*
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2 | 8135aeed | Isaku Yamahata | * ioh3420.c
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3 | 8135aeed | Isaku Yamahata | * Intel X58 north bridge IOH
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4 | 8135aeed | Isaku Yamahata | * PCI Express root port device id 3420
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5 | 8135aeed | Isaku Yamahata | *
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6 | 8135aeed | Isaku Yamahata | * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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7 | 8135aeed | Isaku Yamahata | * VA Linux Systems Japan K.K.
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8 | 8135aeed | Isaku Yamahata | *
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9 | 8135aeed | Isaku Yamahata | * This program is free software; you can redistribute it and/or modify
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10 | 8135aeed | Isaku Yamahata | * it under the terms of the GNU General Public License as published by
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11 | 8135aeed | Isaku Yamahata | * the Free Software Foundation; either version 2 of the License, or
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12 | 8135aeed | Isaku Yamahata | * (at your option) any later version.
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13 | 8135aeed | Isaku Yamahata | *
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14 | 8135aeed | Isaku Yamahata | * This program is distributed in the hope that it will be useful,
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15 | 8135aeed | Isaku Yamahata | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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16 | 8135aeed | Isaku Yamahata | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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17 | 8135aeed | Isaku Yamahata | * GNU General Public License for more details.
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18 | 8135aeed | Isaku Yamahata | *
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19 | 8135aeed | Isaku Yamahata | * You should have received a copy of the GNU General Public License along
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20 | 8135aeed | Isaku Yamahata | * with this program; if not, see <http://www.gnu.org/licenses/>.
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21 | 8135aeed | Isaku Yamahata | */
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22 | 8135aeed | Isaku Yamahata | |
23 | 8135aeed | Isaku Yamahata | #include "pci_ids.h" |
24 | 8135aeed | Isaku Yamahata | #include "msi.h" |
25 | 8135aeed | Isaku Yamahata | #include "pcie.h" |
26 | 8135aeed | Isaku Yamahata | #include "ioh3420.h" |
27 | 8135aeed | Isaku Yamahata | |
28 | 8135aeed | Isaku Yamahata | #define PCI_DEVICE_ID_IOH_EPORT 0x3420 /* D0:F0 express mode */ |
29 | 8135aeed | Isaku Yamahata | #define PCI_DEVICE_ID_IOH_REV 0x2 |
30 | 8135aeed | Isaku Yamahata | #define IOH_EP_SSVID_OFFSET 0x40 |
31 | 8135aeed | Isaku Yamahata | #define IOH_EP_SSVID_SVID PCI_VENDOR_ID_INTEL
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32 | 8135aeed | Isaku Yamahata | #define IOH_EP_SSVID_SSID 0 |
33 | 8135aeed | Isaku Yamahata | #define IOH_EP_MSI_OFFSET 0x60 |
34 | 8135aeed | Isaku Yamahata | #define IOH_EP_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_MASKBIT
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35 | 8135aeed | Isaku Yamahata | #define IOH_EP_MSI_NR_VECTOR 2 |
36 | 8135aeed | Isaku Yamahata | #define IOH_EP_EXP_OFFSET 0x90 |
37 | 8135aeed | Isaku Yamahata | #define IOH_EP_AER_OFFSET 0x100 |
38 | 8135aeed | Isaku Yamahata | |
39 | 8135aeed | Isaku Yamahata | static void ioh3420_write_config(PCIDevice *d, |
40 | 8135aeed | Isaku Yamahata | uint32_t address, uint32_t val, int len)
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41 | 8135aeed | Isaku Yamahata | { |
42 | 8135aeed | Isaku Yamahata | pci_bridge_write_config(d, address, val, len); |
43 | 8135aeed | Isaku Yamahata | msi_write_config(d, address, val, len); |
44 | 6bde6aaa | Michael S. Tsirkin | pcie_cap_slot_write_config(d, address, val, len); |
45 | 8135aeed | Isaku Yamahata | /* TODO: AER */
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46 | 8135aeed | Isaku Yamahata | } |
47 | 8135aeed | Isaku Yamahata | |
48 | 8135aeed | Isaku Yamahata | static void ioh3420_reset(DeviceState *qdev) |
49 | 8135aeed | Isaku Yamahata | { |
50 | 8135aeed | Isaku Yamahata | PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev); |
51 | 8135aeed | Isaku Yamahata | msi_reset(d); |
52 | 8135aeed | Isaku Yamahata | pcie_cap_root_reset(d); |
53 | 8135aeed | Isaku Yamahata | pcie_cap_deverr_reset(d); |
54 | 8135aeed | Isaku Yamahata | pcie_cap_slot_reset(d); |
55 | 8135aeed | Isaku Yamahata | pci_bridge_reset(qdev); |
56 | 8135aeed | Isaku Yamahata | pci_bridge_disable_base_limit(d); |
57 | 8135aeed | Isaku Yamahata | /* TODO: AER */
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58 | 8135aeed | Isaku Yamahata | } |
59 | 8135aeed | Isaku Yamahata | |
60 | 8135aeed | Isaku Yamahata | static int ioh3420_initfn(PCIDevice *d) |
61 | 8135aeed | Isaku Yamahata | { |
62 | 8135aeed | Isaku Yamahata | PCIBridge* br = DO_UPCAST(PCIBridge, dev, d); |
63 | 8135aeed | Isaku Yamahata | PCIEPort *p = DO_UPCAST(PCIEPort, br, br); |
64 | 8135aeed | Isaku Yamahata | PCIESlot *s = DO_UPCAST(PCIESlot, port, p); |
65 | 8135aeed | Isaku Yamahata | int rc;
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66 | 8135aeed | Isaku Yamahata | |
67 | 8135aeed | Isaku Yamahata | rc = pci_bridge_initfn(d); |
68 | 8135aeed | Isaku Yamahata | if (rc < 0) { |
69 | 8135aeed | Isaku Yamahata | return rc;
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70 | 8135aeed | Isaku Yamahata | } |
71 | 8135aeed | Isaku Yamahata | |
72 | 8135aeed | Isaku Yamahata | d->config[PCI_REVISION_ID] = PCI_DEVICE_ID_IOH_REV; |
73 | 8135aeed | Isaku Yamahata | pcie_port_init_reg(d); |
74 | 8135aeed | Isaku Yamahata | |
75 | 8135aeed | Isaku Yamahata | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL); |
76 | 8135aeed | Isaku Yamahata | pci_config_set_device_id(d->config, PCI_DEVICE_ID_IOH_EPORT); |
77 | 8135aeed | Isaku Yamahata | |
78 | 8135aeed | Isaku Yamahata | rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET, |
79 | 8135aeed | Isaku Yamahata | IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID); |
80 | 8135aeed | Isaku Yamahata | if (rc < 0) { |
81 | 8135aeed | Isaku Yamahata | return rc;
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82 | 8135aeed | Isaku Yamahata | } |
83 | 8135aeed | Isaku Yamahata | rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR, |
84 | 8135aeed | Isaku Yamahata | IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, |
85 | 8135aeed | Isaku Yamahata | IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT); |
86 | 8135aeed | Isaku Yamahata | if (rc < 0) { |
87 | 8135aeed | Isaku Yamahata | return rc;
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88 | 8135aeed | Isaku Yamahata | } |
89 | 8135aeed | Isaku Yamahata | rc = pcie_cap_init(d, IOH_EP_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, p->port); |
90 | 8135aeed | Isaku Yamahata | if (rc < 0) { |
91 | 8135aeed | Isaku Yamahata | return rc;
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92 | 8135aeed | Isaku Yamahata | } |
93 | 8135aeed | Isaku Yamahata | pcie_cap_deverr_init(d); |
94 | 8135aeed | Isaku Yamahata | pcie_cap_slot_init(d, s->slot); |
95 | 8135aeed | Isaku Yamahata | pcie_chassis_create(s->chassis); |
96 | 8135aeed | Isaku Yamahata | rc = pcie_chassis_add_slot(s); |
97 | 8135aeed | Isaku Yamahata | if (rc < 0) { |
98 | 8135aeed | Isaku Yamahata | return rc;
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99 | 8135aeed | Isaku Yamahata | } |
100 | 8135aeed | Isaku Yamahata | pcie_cap_root_init(d); |
101 | 8135aeed | Isaku Yamahata | /* TODO: AER */
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102 | 8135aeed | Isaku Yamahata | return 0; |
103 | 8135aeed | Isaku Yamahata | } |
104 | 8135aeed | Isaku Yamahata | |
105 | 8135aeed | Isaku Yamahata | static int ioh3420_exitfn(PCIDevice *d) |
106 | 8135aeed | Isaku Yamahata | { |
107 | 8135aeed | Isaku Yamahata | /* TODO: AER */
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108 | 8135aeed | Isaku Yamahata | msi_uninit(d); |
109 | 8135aeed | Isaku Yamahata | pcie_cap_exit(d); |
110 | 8135aeed | Isaku Yamahata | return pci_bridge_exitfn(d);
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111 | 8135aeed | Isaku Yamahata | } |
112 | 8135aeed | Isaku Yamahata | |
113 | 8135aeed | Isaku Yamahata | PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction, |
114 | 8135aeed | Isaku Yamahata | const char *bus_name, pci_map_irq_fn map_irq, |
115 | 8135aeed | Isaku Yamahata | uint8_t port, uint8_t chassis, uint16_t slot) |
116 | 8135aeed | Isaku Yamahata | { |
117 | 8135aeed | Isaku Yamahata | PCIDevice *d; |
118 | 8135aeed | Isaku Yamahata | PCIBridge *br; |
119 | 8135aeed | Isaku Yamahata | DeviceState *qdev; |
120 | 8135aeed | Isaku Yamahata | |
121 | 8135aeed | Isaku Yamahata | d = pci_create_multifunction(bus, devfn, multifunction, "ioh3420");
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122 | 8135aeed | Isaku Yamahata | if (!d) {
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123 | 8135aeed | Isaku Yamahata | return NULL; |
124 | 8135aeed | Isaku Yamahata | } |
125 | 8135aeed | Isaku Yamahata | br = DO_UPCAST(PCIBridge, dev, d); |
126 | 8135aeed | Isaku Yamahata | |
127 | 8135aeed | Isaku Yamahata | qdev = &br->dev.qdev; |
128 | 8135aeed | Isaku Yamahata | pci_bridge_map_irq(br, bus_name, map_irq); |
129 | 8135aeed | Isaku Yamahata | qdev_prop_set_uint8(qdev, "port", port);
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130 | 8135aeed | Isaku Yamahata | qdev_prop_set_uint8(qdev, "chassis", chassis);
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131 | 8135aeed | Isaku Yamahata | qdev_prop_set_uint16(qdev, "slot", slot);
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132 | 8135aeed | Isaku Yamahata | qdev_init_nofail(qdev); |
133 | 8135aeed | Isaku Yamahata | |
134 | 8135aeed | Isaku Yamahata | return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br));
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135 | 8135aeed | Isaku Yamahata | } |
136 | 8135aeed | Isaku Yamahata | |
137 | 8135aeed | Isaku Yamahata | static const VMStateDescription vmstate_ioh3420 = { |
138 | 8135aeed | Isaku Yamahata | .name = "ioh-3240-express-root-port",
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139 | 8135aeed | Isaku Yamahata | .version_id = 1,
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140 | 8135aeed | Isaku Yamahata | .minimum_version_id = 1,
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141 | 8135aeed | Isaku Yamahata | .minimum_version_id_old = 1,
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142 | 6bde6aaa | Michael S. Tsirkin | .post_load = pcie_cap_slot_post_load, |
143 | 8135aeed | Isaku Yamahata | .fields = (VMStateField[]) { |
144 | 8135aeed | Isaku Yamahata | VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot), |
145 | 8135aeed | Isaku Yamahata | /* TODO: AER */
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146 | 8135aeed | Isaku Yamahata | VMSTATE_END_OF_LIST() |
147 | 8135aeed | Isaku Yamahata | } |
148 | 8135aeed | Isaku Yamahata | }; |
149 | 8135aeed | Isaku Yamahata | |
150 | 8135aeed | Isaku Yamahata | static PCIDeviceInfo ioh3420_info = {
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151 | 8135aeed | Isaku Yamahata | .qdev.name = "ioh3420",
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152 | 8135aeed | Isaku Yamahata | .qdev.desc = "Intel IOH device id 3420 PCIE Root Port",
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153 | 8135aeed | Isaku Yamahata | .qdev.size = sizeof(PCIESlot),
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154 | 8135aeed | Isaku Yamahata | .qdev.reset = ioh3420_reset, |
155 | 8135aeed | Isaku Yamahata | .qdev.vmsd = &vmstate_ioh3420, |
156 | 8135aeed | Isaku Yamahata | |
157 | 8135aeed | Isaku Yamahata | .is_express = 1,
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158 | 8135aeed | Isaku Yamahata | .is_bridge = 1,
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159 | 8135aeed | Isaku Yamahata | .config_write = ioh3420_write_config, |
160 | 8135aeed | Isaku Yamahata | .init = ioh3420_initfn, |
161 | 8135aeed | Isaku Yamahata | .exit = ioh3420_exitfn, |
162 | 8135aeed | Isaku Yamahata | |
163 | 8135aeed | Isaku Yamahata | .qdev.props = (Property[]) { |
164 | 8135aeed | Isaku Yamahata | DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0), |
165 | 8135aeed | Isaku Yamahata | DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), |
166 | 8135aeed | Isaku Yamahata | DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), |
167 | 8135aeed | Isaku Yamahata | /* TODO: AER */
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168 | 8135aeed | Isaku Yamahata | DEFINE_PROP_END_OF_LIST(), |
169 | 8135aeed | Isaku Yamahata | } |
170 | 8135aeed | Isaku Yamahata | }; |
171 | 8135aeed | Isaku Yamahata | |
172 | 8135aeed | Isaku Yamahata | static void ioh3420_register(void) |
173 | 8135aeed | Isaku Yamahata | { |
174 | 8135aeed | Isaku Yamahata | pci_qdev_register(&ioh3420_info); |
175 | 8135aeed | Isaku Yamahata | } |
176 | 8135aeed | Isaku Yamahata | |
177 | 8135aeed | Isaku Yamahata | device_init(ioh3420_register); |
178 | 8135aeed | Isaku Yamahata | |
179 | 8135aeed | Isaku Yamahata | /*
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180 | 8135aeed | Isaku Yamahata | * Local variables:
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181 | 8135aeed | Isaku Yamahata | * c-indent-level: 4
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182 | 8135aeed | Isaku Yamahata | * c-basic-offset: 4
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183 | 8135aeed | Isaku Yamahata | * tab-width: 8
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184 | 8135aeed | Isaku Yamahata | * indent-tab-mode: nil
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185 | 8135aeed | Isaku Yamahata | * End:
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186 | 8135aeed | Isaku Yamahata | */ |