root / hw / xio3130_downstream.c @ 6bde6aaa
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1 | 48ebf2f9 | Isaku Yamahata | /*
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2 | 48ebf2f9 | Isaku Yamahata | * x3130_downstream.c
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3 | 48ebf2f9 | Isaku Yamahata | * TI X3130 pci express downstream port switch
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4 | 48ebf2f9 | Isaku Yamahata | *
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5 | 48ebf2f9 | Isaku Yamahata | * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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6 | 48ebf2f9 | Isaku Yamahata | * VA Linux Systems Japan K.K.
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7 | 48ebf2f9 | Isaku Yamahata | *
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8 | 48ebf2f9 | Isaku Yamahata | * This program is free software; you can redistribute it and/or modify
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9 | 48ebf2f9 | Isaku Yamahata | * it under the terms of the GNU General Public License as published by
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10 | 48ebf2f9 | Isaku Yamahata | * the Free Software Foundation; either version 2 of the License, or
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11 | 48ebf2f9 | Isaku Yamahata | * (at your option) any later version.
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12 | 48ebf2f9 | Isaku Yamahata | *
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13 | 48ebf2f9 | Isaku Yamahata | * This program is distributed in the hope that it will be useful,
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14 | 48ebf2f9 | Isaku Yamahata | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 | 48ebf2f9 | Isaku Yamahata | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 | 48ebf2f9 | Isaku Yamahata | * GNU General Public License for more details.
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17 | 48ebf2f9 | Isaku Yamahata | *
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18 | 48ebf2f9 | Isaku Yamahata | * You should have received a copy of the GNU General Public License along
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19 | 48ebf2f9 | Isaku Yamahata | * with this program; if not, see <http://www.gnu.org/licenses/>.
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20 | 48ebf2f9 | Isaku Yamahata | */
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21 | 48ebf2f9 | Isaku Yamahata | |
22 | 48ebf2f9 | Isaku Yamahata | #include "pci_ids.h" |
23 | 48ebf2f9 | Isaku Yamahata | #include "msi.h" |
24 | 48ebf2f9 | Isaku Yamahata | #include "pcie.h" |
25 | 48ebf2f9 | Isaku Yamahata | #include "xio3130_downstream.h" |
26 | 48ebf2f9 | Isaku Yamahata | |
27 | 48ebf2f9 | Isaku Yamahata | #define PCI_DEVICE_ID_TI_XIO3130D 0x8233 /* downstream port */ |
28 | 48ebf2f9 | Isaku Yamahata | #define XIO3130_REVISION 0x1 |
29 | 48ebf2f9 | Isaku Yamahata | #define XIO3130_MSI_OFFSET 0x70 |
30 | 48ebf2f9 | Isaku Yamahata | #define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT
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31 | 48ebf2f9 | Isaku Yamahata | #define XIO3130_MSI_NR_VECTOR 1 |
32 | 48ebf2f9 | Isaku Yamahata | #define XIO3130_SSVID_OFFSET 0x80 |
33 | 48ebf2f9 | Isaku Yamahata | #define XIO3130_SSVID_SVID 0 |
34 | 48ebf2f9 | Isaku Yamahata | #define XIO3130_SSVID_SSID 0 |
35 | 48ebf2f9 | Isaku Yamahata | #define XIO3130_EXP_OFFSET 0x90 |
36 | 48ebf2f9 | Isaku Yamahata | #define XIO3130_AER_OFFSET 0x100 |
37 | 48ebf2f9 | Isaku Yamahata | |
38 | 48ebf2f9 | Isaku Yamahata | static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address, |
39 | 48ebf2f9 | Isaku Yamahata | uint32_t val, int len)
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40 | 48ebf2f9 | Isaku Yamahata | { |
41 | 48ebf2f9 | Isaku Yamahata | pci_bridge_write_config(d, address, val, len); |
42 | 48ebf2f9 | Isaku Yamahata | pcie_cap_flr_write_config(d, address, val, len); |
43 | 6bde6aaa | Michael S. Tsirkin | pcie_cap_slot_write_config(d, address, val, len); |
44 | 48ebf2f9 | Isaku Yamahata | msi_write_config(d, address, val, len); |
45 | 48ebf2f9 | Isaku Yamahata | /* TODO: AER */
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46 | 48ebf2f9 | Isaku Yamahata | } |
47 | 48ebf2f9 | Isaku Yamahata | |
48 | 48ebf2f9 | Isaku Yamahata | static void xio3130_downstream_reset(DeviceState *qdev) |
49 | 48ebf2f9 | Isaku Yamahata | { |
50 | 48ebf2f9 | Isaku Yamahata | PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev); |
51 | 48ebf2f9 | Isaku Yamahata | msi_reset(d); |
52 | 48ebf2f9 | Isaku Yamahata | pcie_cap_deverr_reset(d); |
53 | 48ebf2f9 | Isaku Yamahata | pcie_cap_slot_reset(d); |
54 | 48ebf2f9 | Isaku Yamahata | pcie_cap_ari_reset(d); |
55 | 48ebf2f9 | Isaku Yamahata | pci_bridge_reset(qdev); |
56 | 48ebf2f9 | Isaku Yamahata | } |
57 | 48ebf2f9 | Isaku Yamahata | |
58 | 48ebf2f9 | Isaku Yamahata | static int xio3130_downstream_initfn(PCIDevice *d) |
59 | 48ebf2f9 | Isaku Yamahata | { |
60 | 48ebf2f9 | Isaku Yamahata | PCIBridge* br = DO_UPCAST(PCIBridge, dev, d); |
61 | 48ebf2f9 | Isaku Yamahata | PCIEPort *p = DO_UPCAST(PCIEPort, br, br); |
62 | 48ebf2f9 | Isaku Yamahata | PCIESlot *s = DO_UPCAST(PCIESlot, port, p); |
63 | 48ebf2f9 | Isaku Yamahata | int rc;
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64 | 48ebf2f9 | Isaku Yamahata | |
65 | 48ebf2f9 | Isaku Yamahata | rc = pci_bridge_initfn(d); |
66 | 48ebf2f9 | Isaku Yamahata | if (rc < 0) { |
67 | 48ebf2f9 | Isaku Yamahata | return rc;
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68 | 48ebf2f9 | Isaku Yamahata | } |
69 | 48ebf2f9 | Isaku Yamahata | |
70 | 48ebf2f9 | Isaku Yamahata | pcie_port_init_reg(d); |
71 | 48ebf2f9 | Isaku Yamahata | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_TI); |
72 | 48ebf2f9 | Isaku Yamahata | pci_config_set_device_id(d->config, PCI_DEVICE_ID_TI_XIO3130D); |
73 | 48ebf2f9 | Isaku Yamahata | d->config[PCI_REVISION_ID] = XIO3130_REVISION; |
74 | 48ebf2f9 | Isaku Yamahata | |
75 | 48ebf2f9 | Isaku Yamahata | rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR, |
76 | 48ebf2f9 | Isaku Yamahata | XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, |
77 | 48ebf2f9 | Isaku Yamahata | XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT); |
78 | 48ebf2f9 | Isaku Yamahata | if (rc < 0) { |
79 | 48ebf2f9 | Isaku Yamahata | return rc;
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80 | 48ebf2f9 | Isaku Yamahata | } |
81 | 48ebf2f9 | Isaku Yamahata | rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, |
82 | 48ebf2f9 | Isaku Yamahata | XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); |
83 | 48ebf2f9 | Isaku Yamahata | if (rc < 0) { |
84 | 48ebf2f9 | Isaku Yamahata | return rc;
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85 | 48ebf2f9 | Isaku Yamahata | } |
86 | 48ebf2f9 | Isaku Yamahata | rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, |
87 | 48ebf2f9 | Isaku Yamahata | p->port); |
88 | 48ebf2f9 | Isaku Yamahata | if (rc < 0) { |
89 | 48ebf2f9 | Isaku Yamahata | return rc;
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90 | 48ebf2f9 | Isaku Yamahata | } |
91 | 48ebf2f9 | Isaku Yamahata | pcie_cap_flr_init(d); /* TODO: implement FLR */
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92 | 48ebf2f9 | Isaku Yamahata | pcie_cap_deverr_init(d); |
93 | 48ebf2f9 | Isaku Yamahata | pcie_cap_slot_init(d, s->slot); |
94 | 48ebf2f9 | Isaku Yamahata | pcie_chassis_create(s->chassis); |
95 | 48ebf2f9 | Isaku Yamahata | rc = pcie_chassis_add_slot(s); |
96 | 48ebf2f9 | Isaku Yamahata | if (rc < 0) { |
97 | 48ebf2f9 | Isaku Yamahata | return rc;
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98 | 48ebf2f9 | Isaku Yamahata | } |
99 | 48ebf2f9 | Isaku Yamahata | pcie_cap_ari_init(d); |
100 | 48ebf2f9 | Isaku Yamahata | /* TODO: AER */
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101 | 48ebf2f9 | Isaku Yamahata | |
102 | 48ebf2f9 | Isaku Yamahata | return 0; |
103 | 48ebf2f9 | Isaku Yamahata | } |
104 | 48ebf2f9 | Isaku Yamahata | |
105 | 48ebf2f9 | Isaku Yamahata | static int xio3130_downstream_exitfn(PCIDevice *d) |
106 | 48ebf2f9 | Isaku Yamahata | { |
107 | 48ebf2f9 | Isaku Yamahata | /* TODO: AER */
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108 | 48ebf2f9 | Isaku Yamahata | msi_uninit(d); |
109 | 48ebf2f9 | Isaku Yamahata | pcie_cap_exit(d); |
110 | 48ebf2f9 | Isaku Yamahata | return pci_bridge_exitfn(d);
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111 | 48ebf2f9 | Isaku Yamahata | } |
112 | 48ebf2f9 | Isaku Yamahata | |
113 | 48ebf2f9 | Isaku Yamahata | PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction, |
114 | 48ebf2f9 | Isaku Yamahata | const char *bus_name, pci_map_irq_fn map_irq, |
115 | 48ebf2f9 | Isaku Yamahata | uint8_t port, uint8_t chassis, |
116 | 48ebf2f9 | Isaku Yamahata | uint16_t slot) |
117 | 48ebf2f9 | Isaku Yamahata | { |
118 | 48ebf2f9 | Isaku Yamahata | PCIDevice *d; |
119 | 48ebf2f9 | Isaku Yamahata | PCIBridge *br; |
120 | 48ebf2f9 | Isaku Yamahata | DeviceState *qdev; |
121 | 48ebf2f9 | Isaku Yamahata | |
122 | 48ebf2f9 | Isaku Yamahata | d = pci_create_multifunction(bus, devfn, multifunction, |
123 | 48ebf2f9 | Isaku Yamahata | "xio3130-downstream");
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124 | 48ebf2f9 | Isaku Yamahata | if (!d) {
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125 | 48ebf2f9 | Isaku Yamahata | return NULL; |
126 | 48ebf2f9 | Isaku Yamahata | } |
127 | 48ebf2f9 | Isaku Yamahata | br = DO_UPCAST(PCIBridge, dev, d); |
128 | 48ebf2f9 | Isaku Yamahata | |
129 | 48ebf2f9 | Isaku Yamahata | qdev = &br->dev.qdev; |
130 | 48ebf2f9 | Isaku Yamahata | pci_bridge_map_irq(br, bus_name, map_irq); |
131 | 48ebf2f9 | Isaku Yamahata | qdev_prop_set_uint8(qdev, "port", port);
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132 | 48ebf2f9 | Isaku Yamahata | qdev_prop_set_uint8(qdev, "chassis", chassis);
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133 | 48ebf2f9 | Isaku Yamahata | qdev_prop_set_uint16(qdev, "slot", slot);
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134 | 48ebf2f9 | Isaku Yamahata | qdev_init_nofail(qdev); |
135 | 48ebf2f9 | Isaku Yamahata | |
136 | 48ebf2f9 | Isaku Yamahata | return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br));
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137 | 48ebf2f9 | Isaku Yamahata | } |
138 | 48ebf2f9 | Isaku Yamahata | |
139 | 48ebf2f9 | Isaku Yamahata | static const VMStateDescription vmstate_xio3130_downstream = { |
140 | 48ebf2f9 | Isaku Yamahata | .name = "xio3130-express-downstream-port",
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141 | 48ebf2f9 | Isaku Yamahata | .version_id = 1,
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142 | 48ebf2f9 | Isaku Yamahata | .minimum_version_id = 1,
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143 | 48ebf2f9 | Isaku Yamahata | .minimum_version_id_old = 1,
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144 | 6bde6aaa | Michael S. Tsirkin | .post_load = pcie_cap_slot_post_load, |
145 | 48ebf2f9 | Isaku Yamahata | .fields = (VMStateField[]) { |
146 | 48ebf2f9 | Isaku Yamahata | VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot), |
147 | 48ebf2f9 | Isaku Yamahata | /* TODO: AER */
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148 | 48ebf2f9 | Isaku Yamahata | VMSTATE_END_OF_LIST() |
149 | 48ebf2f9 | Isaku Yamahata | } |
150 | 48ebf2f9 | Isaku Yamahata | }; |
151 | 48ebf2f9 | Isaku Yamahata | |
152 | 48ebf2f9 | Isaku Yamahata | static PCIDeviceInfo xio3130_downstream_info = {
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153 | 48ebf2f9 | Isaku Yamahata | .qdev.name = "xio3130-downstream",
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154 | 48ebf2f9 | Isaku Yamahata | .qdev.desc = "TI X3130 Downstream Port of PCI Express Switch",
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155 | 48ebf2f9 | Isaku Yamahata | .qdev.size = sizeof(PCIESlot),
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156 | 48ebf2f9 | Isaku Yamahata | .qdev.reset = xio3130_downstream_reset, |
157 | 48ebf2f9 | Isaku Yamahata | .qdev.vmsd = &vmstate_xio3130_downstream, |
158 | 48ebf2f9 | Isaku Yamahata | |
159 | 48ebf2f9 | Isaku Yamahata | .is_express = 1,
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160 | 48ebf2f9 | Isaku Yamahata | .is_bridge = 1,
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161 | 48ebf2f9 | Isaku Yamahata | .config_write = xio3130_downstream_write_config, |
162 | 48ebf2f9 | Isaku Yamahata | .init = xio3130_downstream_initfn, |
163 | 48ebf2f9 | Isaku Yamahata | .exit = xio3130_downstream_exitfn, |
164 | 48ebf2f9 | Isaku Yamahata | |
165 | 48ebf2f9 | Isaku Yamahata | .qdev.props = (Property[]) { |
166 | 48ebf2f9 | Isaku Yamahata | DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0), |
167 | 48ebf2f9 | Isaku Yamahata | DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), |
168 | 48ebf2f9 | Isaku Yamahata | DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), |
169 | 48ebf2f9 | Isaku Yamahata | /* TODO: AER */
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170 | 48ebf2f9 | Isaku Yamahata | DEFINE_PROP_END_OF_LIST(), |
171 | 48ebf2f9 | Isaku Yamahata | } |
172 | 48ebf2f9 | Isaku Yamahata | }; |
173 | 48ebf2f9 | Isaku Yamahata | |
174 | 48ebf2f9 | Isaku Yamahata | static void xio3130_downstream_register(void) |
175 | 48ebf2f9 | Isaku Yamahata | { |
176 | 48ebf2f9 | Isaku Yamahata | pci_qdev_register(&xio3130_downstream_info); |
177 | 48ebf2f9 | Isaku Yamahata | } |
178 | 48ebf2f9 | Isaku Yamahata | |
179 | 48ebf2f9 | Isaku Yamahata | device_init(xio3130_downstream_register); |
180 | 48ebf2f9 | Isaku Yamahata | |
181 | 48ebf2f9 | Isaku Yamahata | /*
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182 | 48ebf2f9 | Isaku Yamahata | * Local variables:
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183 | 48ebf2f9 | Isaku Yamahata | * c-indent-level: 4
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184 | 48ebf2f9 | Isaku Yamahata | * c-basic-offset: 4
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185 | 48ebf2f9 | Isaku Yamahata | * tab-width: 8
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186 | 48ebf2f9 | Isaku Yamahata | * indent-tab-mode: nil
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187 | 48ebf2f9 | Isaku Yamahata | * End:
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188 | 48ebf2f9 | Isaku Yamahata | */ |