Revision 6bde6aaa

b/hw/ioh3420.c
39 39
static void ioh3420_write_config(PCIDevice *d,
40 40
                                   uint32_t address, uint32_t val, int len)
41 41
{
42
    uint16_t sltctl =
43
        pci_get_word(d->config + d->exp.exp_cap + PCI_EXP_SLTCTL);
44

  
45 42
    pci_bridge_write_config(d, address, val, len);
46 43
    msi_write_config(d, address, val, len);
47
    pcie_cap_slot_write_config(d, address, val, len, sltctl);
44
    pcie_cap_slot_write_config(d, address, val, len);
48 45
    /* TODO: AER */
49 46
}
50 47

  
......
142 139
    .version_id = 1,
143 140
    .minimum_version_id = 1,
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    .minimum_version_id_old = 1,
142
    .post_load = pcie_cap_slot_post_load,
145 143
    .fields = (VMStateField[]) {
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        VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
147 145
        /* TODO: AER */
b/hw/pcie.c
140 140
                                 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
141 141
}
142 142

  
143
static void hotplug_event_update_event_status(PCIDevice *dev)
144
{
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    uint32_t pos = dev->exp.exp_cap;
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    uint8_t *exp_cap = dev->config + pos;
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    uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
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    uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
149

  
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    dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) &&
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        (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED);
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}
153

  
154
static void hotplug_event_notify(PCIDevice *dev)
155
{
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    bool prev = dev->exp.hpev_notified;
157

  
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    hotplug_event_update_event_status(dev);
159

  
160
    if (prev == dev->exp.hpev_notified) {
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        return;
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    }
163

  
164
    /* Note: the logic above does not take into account whether interrupts
165
     * are masked. The result is that interrupt will be sent when it is
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     * subsequently unmasked. This appears to be legal: Section 6.7.3.4:
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     * The Port may optionally send an MSI when there are hot-plug events that
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     * occur while interrupt generation is disabled, and interrupt generation is
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     * subsequently enabled. */
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    if (!pci_msi_enabled(dev)) {
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        qemu_set_irq(dev->irq[dev->exp.hpev_intx], dev->exp.hpev_notified);
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    } else if (dev->exp.hpev_notified) {
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        pci_msi_notify(dev, pcie_cap_flags_get_vector(dev));
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    }
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}
176

  
143 177
/*
144 178
 * A PCI Express Hot-Plug Event has occured, so update slot status register
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 * and notify OS of the event if necessary.
......
149 183
 */
150 184
static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event)
151 185
{
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    uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
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    uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
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    uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
155

  
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    PCIE_DEV_PRINTF(dev,
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                    "sltctl: 0x%02"PRIx16" sltsta: 0x%02"PRIx16" event: %x\n",
158
                    sltctl, sltsta, event);
159

  
160
    if (pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, event)) {
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    /* Minor optimization: if nothing changed - no event is needed. */
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    if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap +
188
                                   PCI_EXP_SLTSTA, event)) {
161 189
        return;
162 190
    }
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    sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
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    PCIE_DEV_PRINTF(dev, "sltsta -> %02"PRIx16"\n", sltsta);
165

  
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    if ((sltctl & PCI_EXP_SLTCTL_HPIE) &&
167
        (sltctl & event & PCI_EXP_HP_EV_SUPPORTED)) {
168
        if (pci_msi_enabled(dev)) {
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            pci_msi_notify(dev, pcie_cap_flags_get_vector(dev));
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        } else {
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            qemu_set_irq(dev->irq[dev->exp.hpev_intx], 1);
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        }
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    }
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    hotplug_event_notify(dev);
174 192
}
175 193

  
176 194
static int pcie_cap_slot_hotplug(DeviceState *qdev,
......
258 276
    pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA,
259 277
                               PCI_EXP_HP_EV_SUPPORTED);
260 278

  
279
    dev->exp.hpev_notified = false;
280

  
261 281
    pci_bus_hotplug(pci_bridge_get_sec_bus(DO_UPCAST(PCIBridge, dev, dev)),
262 282
                    pcie_cap_slot_hotplug, &dev->qdev);
263 283
}
......
286 306
                                 PCI_EXP_SLTSTA_CC |
287 307
                                 PCI_EXP_SLTSTA_PDC |
288 308
                                 PCI_EXP_SLTSTA_ABP);
309

  
310
    hotplug_event_notify(dev);
289 311
}
290 312

  
291 313
void pcie_cap_slot_write_config(PCIDevice *dev,
292
                                uint32_t addr, uint32_t val, int len,
293
                                uint16_t sltctl_prev)
314
                                uint32_t addr, uint32_t val, int len)
294 315
{
295 316
    uint32_t pos = dev->exp.exp_cap;
296 317
    uint8_t *exp_cap = dev->config + pos;
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    uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
298 318
    uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
299 319

  
300 320
    if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) {
301 321
        return;
302 322
    }
303 323

  
304
    PCIE_DEV_PRINTF(dev,
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                    "addr: 0x%"PRIx32" val: 0x%"PRIx32" len: %d\n"
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                    "\tsltctl_prev: 0x%02"PRIx16" sltctl: 0x%02"PRIx16
307
                    " sltsta: 0x%02"PRIx16"\n",
308
                    addr, val, len, sltctl_prev, sltctl, sltsta);
309

  
310
    /* SLTCTL */
311
    PCIE_DEV_PRINTF(dev, "sltctl: 0x%02"PRIx16" -> 0x%02"PRIx16"\n",
312
                    sltctl_prev, sltctl);
313

  
314 324
    if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
315 325
                                     PCI_EXP_SLTCTL_EIC)) {
316 326
        sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */
......
320 330
                        sltsta);
321 331
    }
322 332

  
323
    /*
324
     * The events control bits might be enabled or disabled,
325
     * Check if the software notificastion condition is satisfied
326
     * or disatisfied.
327
     *
328
     * 6.7.3.4 Software Notification of Hot-plug events
329
     */
330
    if (pci_msi_enabled(dev)) {
331
        bool msi_trigger =
332
            (sltctl & PCI_EXP_SLTCTL_HPIE) &&
333
            ((sltctl_prev ^ sltctl) & sltctl & /* stlctl: 0 -> 1 */
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             sltsta & PCI_EXP_HP_EV_SUPPORTED);
335
        if (msi_trigger) {
336
            pci_msi_notify(dev, pcie_cap_flags_get_vector(dev));
337
        }
338
    } else {
339
        int int_level =
340
            (sltctl & PCI_EXP_SLTCTL_HPIE) &&
341
            (sltctl & sltsta & PCI_EXP_HP_EV_SUPPORTED);
342
        qemu_set_irq(dev->irq[dev->exp.hpev_intx], int_level);
343
    }
344

  
345
    if (!((sltctl_prev ^ sltctl) & PCI_EXP_SLTCTL_SUPPORTED)) {
346
        PCIE_DEV_PRINTF(dev,
347
                        "sprious command completion slctl "
348
                        "0x%"PRIx16" -> 0x%"PRIx16"\n",
349
                        sltctl_prev, sltctl);
350
    }
333
    hotplug_event_notify(dev);
351 334

  
352 335
    /* 
353 336
     * 6.7.3.2 Command Completed Events
......
368 351
    pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI);
369 352
}
370 353

  
354
int pcie_cap_slot_post_load(void *opaque, int version_id)
355
{
356
    PCIDevice *dev = opaque;
357
    hotplug_event_update_event_status(dev);
358
    return 0;
359
}
360

  
371 361
void pcie_cap_slot_push_attention_button(PCIDevice *dev)
372 362
{
373 363
    pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP);
b/hw/pcie.h
74 74
                                 * also initialize it when loaded as
75 75
                                 * appropreately.
76 76
                                 */
77
    bool hpev_notified; /* Logical AND of conditions for hot plug event.
78
                         Following 6.7.3.4:
79
                         Software Notification of Hot-Plug Events, an interrupt
80
                         is sent whenever the logical and of these conditions
81
                         transitions from false to true. */
77 82
};
78 83

  
79 84
/* PCI express capability helper functions */
......
89 94
void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot);
90 95
void pcie_cap_slot_reset(PCIDevice *dev);
91 96
void pcie_cap_slot_write_config(PCIDevice *dev,
92
                                uint32_t addr, uint32_t val, int len,
93
                                uint16_t sltctl_prev);
97
                                uint32_t addr, uint32_t val, int len);
98
int pcie_cap_slot_post_load(void *opaque, int version_id);
94 99
void pcie_cap_slot_push_attention_button(PCIDevice *dev);
95 100

  
96 101
void pcie_cap_root_init(PCIDevice *dev);
b/hw/xio3130_downstream.c
38 38
static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
39 39
                                         uint32_t val, int len)
40 40
{
41
    uint16_t sltctl =
42
        pci_get_word(d->config + d->exp.exp_cap + PCI_EXP_SLTCTL);
43

  
44 41
    pci_bridge_write_config(d, address, val, len);
45 42
    pcie_cap_flr_write_config(d, address, val, len);
46
    pcie_cap_slot_write_config(d, address, val, len, sltctl);
43
    pcie_cap_slot_write_config(d, address, val, len);
47 44
    msi_write_config(d, address, val, len);
48 45
    /* TODO: AER */
49 46
}
......
144 141
    .version_id = 1,
145 142
    .minimum_version_id = 1,
146 143
    .minimum_version_id_old = 1,
144
    .post_load = pcie_cap_slot_post_load,
147 145
    .fields = (VMStateField[]) {
148 146
        VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
149 147
        /* TODO: AER */

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