Revision 6bde6aaa hw/pcie.c
| b/hw/pcie.c | ||
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PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); |
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} |
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static void hotplug_event_update_event_status(PCIDevice *dev) |
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{
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uint32_t pos = dev->exp.exp_cap; |
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uint8_t *exp_cap = dev->config + pos; |
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uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); |
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uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); |
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dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) && |
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(sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED); |
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} |
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static void hotplug_event_notify(PCIDevice *dev) |
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{
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bool prev = dev->exp.hpev_notified; |
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hotplug_event_update_event_status(dev); |
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if (prev == dev->exp.hpev_notified) {
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return; |
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} |
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/* Note: the logic above does not take into account whether interrupts |
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* are masked. The result is that interrupt will be sent when it is |
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* subsequently unmasked. This appears to be legal: Section 6.7.3.4: |
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* The Port may optionally send an MSI when there are hot-plug events that |
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* occur while interrupt generation is disabled, and interrupt generation is |
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* subsequently enabled. */ |
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if (!pci_msi_enabled(dev)) {
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qemu_set_irq(dev->irq[dev->exp.hpev_intx], dev->exp.hpev_notified); |
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} else if (dev->exp.hpev_notified) {
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pci_msi_notify(dev, pcie_cap_flags_get_vector(dev)); |
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} |
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} |
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/* |
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* A PCI Express Hot-Plug Event has occured, so update slot status register |
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* and notify OS of the event if necessary. |
| ... | ... | |
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*/ |
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static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event) |
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{
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uint8_t *exp_cap = dev->config + dev->exp.exp_cap; |
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uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); |
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uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); |
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PCIE_DEV_PRINTF(dev, |
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"sltctl: 0x%02"PRIx16" sltsta: 0x%02"PRIx16" event: %x\n", |
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sltctl, sltsta, event); |
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if (pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, event)) {
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/* Minor optimization: if nothing changed - no event is needed. */ |
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if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap + |
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PCI_EXP_SLTSTA, event)) {
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return; |
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} |
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sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); |
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PCIE_DEV_PRINTF(dev, "sltsta -> %02"PRIx16"\n", sltsta); |
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if ((sltctl & PCI_EXP_SLTCTL_HPIE) && |
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(sltctl & event & PCI_EXP_HP_EV_SUPPORTED)) {
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if (pci_msi_enabled(dev)) {
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pci_msi_notify(dev, pcie_cap_flags_get_vector(dev)); |
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} else {
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qemu_set_irq(dev->irq[dev->exp.hpev_intx], 1); |
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} |
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} |
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hotplug_event_notify(dev); |
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} |
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static int pcie_cap_slot_hotplug(DeviceState *qdev, |
| ... | ... | |
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pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA, |
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PCI_EXP_HP_EV_SUPPORTED); |
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dev->exp.hpev_notified = false; |
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pci_bus_hotplug(pci_bridge_get_sec_bus(DO_UPCAST(PCIBridge, dev, dev)), |
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pcie_cap_slot_hotplug, &dev->qdev); |
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} |
| ... | ... | |
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PCI_EXP_SLTSTA_CC | |
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PCI_EXP_SLTSTA_PDC | |
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PCI_EXP_SLTSTA_ABP); |
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hotplug_event_notify(dev); |
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} |
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void pcie_cap_slot_write_config(PCIDevice *dev, |
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uint32_t addr, uint32_t val, int len, |
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uint16_t sltctl_prev) |
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uint32_t addr, uint32_t val, int len) |
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{
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uint32_t pos = dev->exp.exp_cap; |
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uint8_t *exp_cap = dev->config + pos; |
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uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL); |
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uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); |
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if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) {
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return; |
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} |
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PCIE_DEV_PRINTF(dev, |
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"addr: 0x%"PRIx32" val: 0x%"PRIx32" len: %d\n" |
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"\tsltctl_prev: 0x%02"PRIx16" sltctl: 0x%02"PRIx16 |
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" sltsta: 0x%02"PRIx16"\n", |
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addr, val, len, sltctl_prev, sltctl, sltsta); |
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/* SLTCTL */ |
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PCIE_DEV_PRINTF(dev, "sltctl: 0x%02"PRIx16" -> 0x%02"PRIx16"\n", |
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sltctl_prev, sltctl); |
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if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, |
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PCI_EXP_SLTCTL_EIC)) {
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sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */ |
| ... | ... | |
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sltsta); |
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} |
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/* |
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* The events control bits might be enabled or disabled, |
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* Check if the software notificastion condition is satisfied |
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* or disatisfied. |
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* |
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* 6.7.3.4 Software Notification of Hot-plug events |
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*/ |
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if (pci_msi_enabled(dev)) {
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bool msi_trigger = |
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(sltctl & PCI_EXP_SLTCTL_HPIE) && |
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((sltctl_prev ^ sltctl) & sltctl & /* stlctl: 0 -> 1 */ |
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sltsta & PCI_EXP_HP_EV_SUPPORTED); |
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if (msi_trigger) {
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pci_msi_notify(dev, pcie_cap_flags_get_vector(dev)); |
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} |
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} else {
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int int_level = |
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(sltctl & PCI_EXP_SLTCTL_HPIE) && |
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(sltctl & sltsta & PCI_EXP_HP_EV_SUPPORTED); |
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qemu_set_irq(dev->irq[dev->exp.hpev_intx], int_level); |
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} |
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if (!((sltctl_prev ^ sltctl) & PCI_EXP_SLTCTL_SUPPORTED)) {
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PCIE_DEV_PRINTF(dev, |
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"sprious command completion slctl " |
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"0x%"PRIx16" -> 0x%"PRIx16"\n", |
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sltctl_prev, sltctl); |
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} |
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hotplug_event_notify(dev); |
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/* |
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* 6.7.3.2 Command Completed Events |
| ... | ... | |
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pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI); |
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} |
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int pcie_cap_slot_post_load(void *opaque, int version_id) |
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{
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PCIDevice *dev = opaque; |
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hotplug_event_update_event_status(dev); |
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return 0; |
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} |
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|
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void pcie_cap_slot_push_attention_button(PCIDevice *dev) |
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{
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pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP); |
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