Revision 6bef0436
b/hw/apb_pci.c | ||
---|---|---|
418 | 418 |
/* PCI configuration space */ |
419 | 419 |
s->pci_config_handler.read = apb_pci_config_read; |
420 | 420 |
s->pci_config_handler.write = apb_pci_config_write; |
421 |
pci_config = cpu_register_io_memory_simple(&s->pci_config_handler); |
|
421 |
pci_config = cpu_register_io_memory_simple(&s->pci_config_handler, |
|
422 |
DEVICE_NATIVE_ENDIAN); |
|
422 | 423 |
assert(pci_config >= 0); |
423 | 424 |
/* at region 1 */ |
424 | 425 |
sysbus_init_mmio(dev, 0x1000000ULL, pci_config); |
b/hw/pci_host.c | ||
---|---|---|
187 | 187 |
{ |
188 | 188 |
pci_host_init(s); |
189 | 189 |
if (swap) { |
190 |
return cpu_register_io_memory_simple(&s->conf_handler); |
|
190 |
return cpu_register_io_memory_simple(&s->conf_handler, |
|
191 |
DEVICE_NATIVE_ENDIAN); |
|
191 | 192 |
} else { |
192 |
return cpu_register_io_memory_simple(&s->conf_noswap_handler); |
|
193 |
return cpu_register_io_memory_simple(&s->conf_noswap_handler, |
|
194 |
DEVICE_NATIVE_ENDIAN); |
|
193 | 195 |
} |
194 | 196 |
} |
195 | 197 |
|
... | ... | |
203 | 205 |
{ |
204 | 206 |
pci_host_init(s); |
205 | 207 |
if (swap) { |
206 |
return cpu_register_io_memory_simple(&s->data_handler); |
|
208 |
return cpu_register_io_memory_simple(&s->data_handler, |
|
209 |
DEVICE_NATIVE_ENDIAN); |
|
207 | 210 |
} else { |
208 |
return cpu_register_io_memory_simple(&s->data_noswap_handler); |
|
211 |
return cpu_register_io_memory_simple(&s->data_noswap_handler, |
|
212 |
DEVICE_NATIVE_ENDIAN); |
|
209 | 213 |
} |
210 | 214 |
} |
211 | 215 |
|
b/hw/unin_pci.c | ||
---|---|---|
154 | 154 |
pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1); |
155 | 155 |
s->data_handler.read = unin_data_read; |
156 | 156 |
s->data_handler.write = unin_data_write; |
157 |
pci_mem_data = cpu_register_io_memory_simple(&s->data_handler); |
|
157 |
pci_mem_data = cpu_register_io_memory_simple(&s->data_handler, |
|
158 |
DEVICE_NATIVE_ENDIAN); |
|
158 | 159 |
sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
159 | 160 |
sysbus_init_mmio(dev, 0x1000, pci_mem_data); |
160 | 161 |
|
... | ... | |
175 | 176 |
pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1); |
176 | 177 |
s->data_handler.read = unin_data_read; |
177 | 178 |
s->data_handler.write = unin_data_write; |
178 |
pci_mem_data = cpu_register_io_memory_simple(&s->data_handler); |
|
179 |
pci_mem_data = cpu_register_io_memory_simple(&s->data_handler, |
|
180 |
DEVICE_NATIVE_ENDIAN); |
|
179 | 181 |
sysbus_init_mmio(dev, 0x1000, pci_mem_config); |
180 | 182 |
sysbus_init_mmio(dev, 0x1000, pci_mem_data); |
181 | 183 |
|
b/rwhandler.c | ||
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35 | 35 |
&cpu_io_memory_simple_readl, |
36 | 36 |
}; |
37 | 37 |
|
38 |
int cpu_register_io_memory_simple(struct ReadWriteHandler *handler) |
|
38 |
int cpu_register_io_memory_simple(struct ReadWriteHandler *handler, int endian)
|
|
39 | 39 |
{ |
40 | 40 |
if (!handler->read || !handler->write) { |
41 | 41 |
return -1; |
42 | 42 |
} |
43 | 43 |
return cpu_register_io_memory(cpu_io_memory_simple_read, |
44 | 44 |
cpu_io_memory_simple_write, |
45 |
handler, DEVICE_NATIVE_ENDIAN);
|
|
45 |
handler, endian);
|
|
46 | 46 |
} |
47 | 47 |
|
48 | 48 |
RWHANDLER_WRITE(ioport_simple_writeb, 1, uint32_t); |
b/rwhandler.h | ||
---|---|---|
19 | 19 |
|
20 | 20 |
/* Helpers for when we want to use a single routine with length. */ |
21 | 21 |
/* CPU memory handler: both read and write must be present. */ |
22 |
int cpu_register_io_memory_simple(ReadWriteHandler *); |
|
22 |
int cpu_register_io_memory_simple(ReadWriteHandler *, int endian);
|
|
23 | 23 |
/* io port handler: can supply only read or write handlers. */ |
24 | 24 |
int register_ioport_simple(ReadWriteHandler *, |
25 | 25 |
pio_addr_t start, int length, int size); |
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